Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH077810B2 - Semiconductor device - Google Patents
[go: Go Back, main page]

JPH077810B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH077810B2
JPH077810B2 JP13014186A JP13014186A JPH077810B2 JP H077810 B2 JPH077810 B2 JP H077810B2 JP 13014186 A JP13014186 A JP 13014186A JP 13014186 A JP13014186 A JP 13014186A JP H077810 B2 JPH077810 B2 JP H077810B2
Authority
JP
Japan
Prior art keywords
ceramics
heat sink
metal
semiconductor device
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13014186A
Other languages
Japanese (ja)
Other versions
JPS62287649A (en
Inventor
正昭 高橋
守 沢畠
保敏 栗原
広一 井上
耕明 八野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13014186A priority Critical patent/JPH077810B2/en
Publication of JPS62287649A publication Critical patent/JPS62287649A/en
Publication of JPH077810B2 publication Critical patent/JPH077810B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は新規な半導体装置に係り、特に半導体素子搭載
用絶縁基板として熱膨張係数の低いSiCやAlNセラミツク
スを絶縁に使用した接続構造に関する。
The present invention relates to a novel semiconductor device, and more particularly to a connection structure using SiC or AlN ceramics having a low coefficient of thermal expansion for insulation as an insulating substrate for mounting a semiconductor element.

〔従来の技術〕[Conventional technology]

従来のセラミツクスと金属材料との接続は特開昭56−13
5948号等に記載されているようにセラミツクス表面をM
o,W,Ni,Mo−Mn合金のごとき金属を蒸着法やスクリーン
印刷法によつて金属化したのち、ヒートシンクとなるべ
き金属材料の表面に半田や銀ロウ等のロウ材を介して接
続する方法がとられている。しかし、SiCやAlN等熱膨張
係数の低いセラミツクスに於いては金属材料との整合性
が悪く、ロウ付時の熱処理等によりセラミツクス内部に
残る応力によつて、その後の熱サイクル試験等信頼性試
験でクラツクが発生し、気密もれや絶縁抵抗の低下等問
題が生じ苦慮していた。
The conventional connection between ceramics and metallic materials is disclosed in JP-A-56-13.
As described in 5948, etc.
After metalizing metal such as o, W, Ni, Mo-Mn alloy by vapor deposition or screen printing, connect it to the surface of the metal material to be the heat sink through solder material such as solder or silver solder. The method is taken. However, in ceramics with a low coefficient of thermal expansion such as SiC and AlN, the compatibility with metallic materials is poor, and due to the stress remaining inside the ceramics due to heat treatment during brazing, reliability tests such as the subsequent thermal cycle test are performed. This caused cracking, which caused problems such as leaking of airtightness and reduction of insulation resistance.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術はSiCやAlNセラミツクスの熱膨張係数に関
しては充分な配慮がなされておらずセラミツクスの破壊
による絶縁不良あるいは気密もれなど半導体装置のパツ
ケージ構成するに当り問題があつた。
The above-mentioned prior art does not give sufficient consideration to the coefficient of thermal expansion of SiC or AlN ceramics, and there is a problem in constructing a package of a semiconductor device such as insulation failure or airtightness due to destruction of the ceramics.

本発明の目的はSiCとAlN等低熱膨張のセラミツクスを破
壊することなく、異なる熱膨張係数をもつ材料、特にヒ
ートシンクとなる金属材料に接続した半導体装置を提供
するにある。
An object of the present invention is to provide a semiconductor device connected to a material having a different thermal expansion coefficient, in particular, a metal material serving as a heat sink, without breaking ceramics having a low thermal expansion such as SiC and AlN.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体素子と金属とからなるヒートシンク金
属との間に高熱伝導性セラミツクスを挿入して絶縁分離
されている半導体装置において、前記セラミツクス端部
を金属フレームで覆い、該フレームを前記ヒートシンク
に接続することにより前記セラミツクスをヒートシンク
に接続することを特徴とする半導体装置にある。
The present invention relates to a semiconductor device in which a high thermal conductive ceramics is inserted between a semiconductor element and a heat sink metal made of a metal for insulation separation, and the ceramics end portion is covered with a metal frame, and the frame is used as the heat sink. In the semiconductor device, the ceramics are connected to a heat sink by connecting them.

更に、本発明はセラミツクスとヒートシンクとの間に純
銅又は純銅より軟い金属箔を介在させることにある。
Furthermore, the present invention resides in that pure copper or a metal foil softer than pure copper is interposed between the ceramic and the heat sink.

セラミツクスとして、炭化ケイ素,窒化ケイ素,窒化ア
ルミ等の室温で0.05cal/cm,sec・℃以上の熱伝導率を有
し、室温の熱膨張係数が5×10-6/℃以下の焼結体が好
ましい。特に、熱伝導率は0.2cal/cm,sec・℃以上のも
のが好ましい。また、アルミナ,ジコニア焼結体でもよ
い。特に、セラミツクスとして厚さは0.4〜1mmが好まし
く、10mm角以上の大きさのものに対し本発明の効果が大
きく現われる。従つて、特に10〜30mm角に対し好ましい
結果が得られる。
Ceramics such as silicon carbide, silicon nitride, aluminum nitride, etc., which have a thermal conductivity of 0.05 cal / cm, sec · ° C or higher at room temperature, and a coefficient of thermal expansion at room temperature of 5 × 10 -6 / ° C or lower. Is preferred. Particularly, it is preferable that the thermal conductivity is 0.2 cal / cm, sec. ° C. or higher. Further, it may be an alumina or zirconia sintered body. In particular, the thickness of the ceramic is preferably 0.4 to 1 mm, and the effect of the present invention is greatly exhibited when the ceramic has a size of 10 mm square or more. Therefore, preferable results are obtained especially for 10 to 30 mm square.

ヒートシンクとしては金属が好ましく、銅,アルミニウ
ムが特に好ましく、板状又は放熱フインチ、セラミツク
スとヒートシンクとの間に介在させる金属箔は純銅又は
それより軟い材料からなる。具体的には、Cu,Al,Sn,Pb,
Au,Ag,Ni,Zn等が好ましく、0.01〜0.5mmの厚さが好まし
い。特に、0.1〜0.2mmが好ましい。
The heat sink is preferably made of metal, particularly preferably copper or aluminum. The plate-shaped or heat-dissipating fin, and the metal foil interposed between the ceramic and the heat sink are made of pure copper or a softer material. Specifically, Cu, Al, Sn, Pb,
Au, Ag, Ni, Zn and the like are preferable, and a thickness of 0.01 to 0.5 mm is preferable. Particularly, 0.1 to 0.2 mm is preferable.

上記した問題点は熱膨張係数の小さなSiC,AlN等のセラ
ミツクスを熱膨張係数の大きな金属材料に半田やAgロウ
で直接接続するがために残るストレスによつて発生する
ためである。
The above-mentioned problem is caused by residual stress caused by directly connecting ceramics such as SiC and AlN having a small coefficient of thermal expansion to a metal material having a large coefficient of thermal expansion with solder or Ag solder.

これに対して大型の電力用半導体装置に於いては一方の
電極をシリコンと比較的熱膨張係数の近いMo、又はW等
の緩衝板をロウ材によつて接続し主電極(Cu)との間は
圧接によつて導通をとる方法が一般的に用いられてい
る。
On the other hand, in a large power semiconductor device, one electrode is connected to a main electrode (Cu) by connecting a buffer plate such as Mo or W, which has a thermal expansion coefficient relatively close to that of silicon, with a brazing material. Generally, a method is used in which the spaces are electrically connected by pressure welding.

そこで発明者らは上記した目的を解決するため接続法に
着目した。つまり、メタライズ層を形成したセラミツク
スと半導体素子との接続は従来法と同じく半田,ロウ材
等を用いるが、セラミツクスをヒートシンク等金属材料
との接続は圧接構造にすることにした。
Therefore, the inventors have focused on the connection method in order to solve the above-mentioned object. That is, the ceramics on which the metallized layer is formed and the semiconductor element are connected by using solder, brazing material or the like as in the conventional method, but the ceramics are connected by pressure welding to the metal material such as the heat sink.

〔作用〕 SiCやAlN等のセラミツクスの熱膨張係数は半導体装置の
素材シリコンとほぼ等しいためそれらの接続に関しては
従来法がそのまま使用でき特に問題とはならない。
[Function] Since the coefficient of thermal expansion of ceramics such as SiC and AlN is almost the same as that of the material silicon of the semiconductor device, the conventional method can be used as it is for connecting them, and there is no particular problem.

一方、SiCやAlN等のセラミツクスとヒートシンク材、一
般的にはCu系,Fe系の金属材料との接続を半田やAgロウ
を介して行なうとこれまでのAl2O3とは異なり残留する
応力によりクラツクが発生する。この現象はセラミツク
スのサイズが大きいほど発生する割合が高く、又、熱サ
イクル試験等信頼性試験に於いてはクラツクの発生が初
期の段階に見られていた。そこで、ヒートシンク材とセ
ラミツクスの接続はロウ材等は用いず圧接構造とするこ
とにより、メタライズされたSiC又はAlNセラミツクスと
ヒートシンク材の間にAlやCu箔等のやわらかい金属材料
を挿入し、セラミツクス端部を覆うように構成されたフ
レーム自体をヒートシンクに接続するこでセラミツクス
とヒートシンクとのより高い密着が得られる。この方法
によれば例え金属材料の加熱され伸びてもセラミツクス
には影響を及ぼさずクラツクも発生しない。一方、この
方法によつてセラミツクスとヒートシンク間の熱伝導率
が若干低下するが、SiCやAlNセラミツクス等はAl2O3
対して4〜8倍程高いためあまり問題とはならない。
On the other hand, when connecting ceramics such as SiC and AlN with heat sink materials, generally Cu-based and Fe-based metallic materials through solder or Ag solder, residual stress is different from conventional Al 2 O 3 stress. This causes a crack. The larger the size of the ceramics, the higher the rate of occurrence of this phenomenon, and in reliability tests such as the heat cycle test, the occurrence of cracks was observed in the early stage. Therefore, by connecting the heat sink material and the ceramics with a pressure welding structure without using a brazing material or the like, a soft metal material such as Al or Cu foil is inserted between the metallized SiC or AlN ceramics and the heat sink material, and the ceramics end is connected. Higher adhesion between the ceramic and the heat sink can be obtained by connecting the frame itself configured to cover the part to the heat sink. According to this method, even if the metal material is heated and stretched, it does not affect the ceramics and cracks do not occur. On the other hand, this method slightly lowers the thermal conductivity between the ceramics and the heat sink, but since SiC and AlN ceramics are 4 to 8 times higher than Al 2 O 3 , it does not cause a problem.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す半導体装置の断面図で
ある。半導体チツプ15がSiCやAlN等の焼結体12で絶縁分
離された絶縁型半導体装置に於いて、セラミツクス12と
ヒートシンク10内にAl,Cu箔等の熱応力によつて変形し
緩和するやわらかい金属からなる緩衝板11を挿入し、セ
ラミツクス12とヒートシンク10との接続は金属フレーム
13の端部14をパーカツシヨン法、又は半田等によりヒー
トシンク10に接着させることによつて圧接固定される。
半導体チツプ15が搭載されるセラミツクスの主表面には
半田付可能なメタライズ層が形成されているが、本発明
の場合、緩衝板11と接する裏面には半田付する必要はな
い。緩衝板11はAl,Cu箔の2者に特定されるものでな
く、Ag,半田箔等やわらかく良熱伝導体の全層箔であれ
ば良い。一方、ヒートシンクの材料は半導体装置で一般
的に用いられているCu,Fe,Al等のいずれでも良い。
FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In an insulating semiconductor device in which the semiconductor chip 15 is insulated and separated by a sintered body 12 such as SiC or AlN, a soft metal that is deformed and relaxed by thermal stress such as Al or Cu foil in the ceramics 12 and the heat sink 10. Insert a buffer plate 11 consisting of, and connect the ceramics 12 and the heat sink 10 with a metal frame.
The end portion 14 of 13 is pressure-contacted and fixed by adhering the end portion 14 to the heat sink 10 by a percussion method, solder or the like.
Although a solderable metallization layer is formed on the main surface of the ceramic on which the semiconductor chip 15 is mounted, it is not necessary to solder the back surface in contact with the buffer plate 11 in the present invention. The buffer plate 11 is not limited to the two types of Al and Cu foils, and may be any soft, good heat conductor full-layer foil such as Ag or solder foil. On the other hand, the material of the heat sink may be any of Cu, Fe, Al and the like which are generally used in semiconductor devices.

第2図は他のパワー半導体装置の例を示す断面図であ
る。ヒートシンク10の凹部20を施け、これに緩衝板11、
セラミツクス12を落しこみ、フレームを接着することで
セラミツクスを圧接するよう構成されたものである。
FIG. 2 is a sectional view showing an example of another power semiconductor device. The concave portion 20 of the heat sink 10 is provided, and the cushion plate 11 and
The ceramics 12 is dropped and the frame is adhered to the ceramics so as to press the ceramics.

凹部20はセラミツクス12の位置決めが容易となり、その
深さはセラミツクスの位置決めができる程度でよい。
The recess 20 facilitates positioning of the ceramic 12, and the depth thereof may be such that the ceramic can be positioned.

以上、本発明の実施例をパワー半導体装置(サイリス
タ)の例で説明したが、半導体チツプ以外の抵抗体やコ
ンデンサ等他の電子部品を混載してなる半導体モジール
やハイブリツトICあるいは高圧IC,LSI,VLSI,ECL等を搭
載する基板して使用できる。
Although the embodiment of the present invention has been described with reference to the example of the power semiconductor device (thyristor), a semiconductor module or hybrid IC or high voltage IC, LSI, in which other electronic components such as a resistor or a capacitor other than the semiconductor chip are mixedly mounted, It can be used as a board on which VLSI, ECL, etc. are mounted.

セラミツクス12として使用したSiC又はAlN焼結体はいず
れもBeO2重量%を含み、ホツトプレス焼結によつて製造
されたものであり、前者は室温で約0.7cal/cm,sec・℃
及び後者は0.3cal/cm,sec・℃の熱伝導性を有する。こ
れらの焼結体として、厚さ0.6mm,15mm角のものを製造し
た。
All of the SiC or AlN sintered bodies used as the ceramics 12 contained 2% by weight of BeO and were manufactured by hot press sintering. The former is about 0.7 cal / cm, sec ・ ° C at room temperature.
And the latter has a thermal conductivity of 0.3 cal / cm, sec · ° C. As these sintered bodies, those having a thickness of 0.6 mm and a size of 15 mm square were manufactured.

金属フレーム13は焼結体12の端部が金属フレームに2mm
かかるように全周にわたつて接触するようになつてお
り、0.1mm厚さで、セラミツクス12と同じ大きさのAlか
らなる緩衝板11を介在させて若干加圧させた状態でろう
等によつて接続される。従つて、セラミツクス12はヒー
トシンク10に密着させることができ、放熱効果を向上さ
せることができる。なお、金属フレーム13は焼結体の両
端部でもよい。半導体素子12は、Au−Siろう,Au−Geろ
う,Au−Snはんだ,Pb−Snはんだ等によつて金属フレーム
13の接続の前後のいずれにおいてもセラミツクス上に接
合できる。半導体素子15をSiCセラミツクス12にはんだ
によつて接合する場合にはCrペーストによつてメタライ
ズして反応層を形成した後、その反応層上にNi,Cuめつ
きを施し、はんだで接合する。また、Au系合金によつて
接合する場合には10%以下のCdを含有させることによつ
て直接接合することができる。
In the metal frame 13, the end of the sintered body 12 is 2 mm in the metal frame.
As described above, the contact is made over the entire circumference, and the cushion plate 11 made of Al having a thickness of 0.1 mm and the same size as the ceramics 12 is interposed so that the pressure is slightly increased. Connected. Therefore, the ceramic 12 can be brought into close contact with the heat sink 10 and the heat radiation effect can be improved. The metal frame 13 may be both ends of the sintered body. The semiconductor element 12 is a metal frame made of Au-Si solder, Au-Ge solder, Au-Sn solder, Pb-Sn solder, etc.
It can be bonded on the ceramic either before or after connection of 13. When the semiconductor element 15 is joined to the SiC ceramics 12 by soldering, a reaction layer is formed by metallizing with a Cr paste, and then Ni and Cu are plated on the reaction layer and joined by soldering. Further, in the case of joining with an Au-based alloy, it can be joined directly by containing 10% or less of Cd.

第3図は本発明の他の一実施例を示すパワー半導体装置
の断面図である。SiC,AlN前述の焼結体等セラミツクス
の主表面の金属フレーム13と接触する部分と裏面全体に
Al等のやわらかい厚さ5〜30μmの金属膜30を形成す
る。この金属膜30は裏面に施いてはセラミツクス表面の
熱を緩衝板11に効率良く伝えるためであり、緩衝板11と
反応しないAl等が好的である。又、主表面の一部に施け
る金属膜30は金属フレーム13とセラミツクス12とが効果
的に接触させるためのもので基本的には裏面のAlと同じ
で良いが、この外に主表面に形成するCu系,Au系のやわ
らかい金属であつても良い。
FIG. 3 is a sectional view of a power semiconductor device showing another embodiment of the present invention. SiC, AlN The portion of the main surface of the ceramic such as the aforementioned sintered body that contacts the metal frame 13 and the entire back surface
A metal film 30 having a soft thickness of 5 to 30 μm such as Al is formed. This metal film 30 is provided on the back surface to efficiently transfer the heat of the ceramic surface to the buffer plate 11, and Al or the like that does not react with the buffer plate 11 is preferable. Further, the metal film 30 provided on a part of the main surface is for effectively contacting the metal frame 13 and the ceramic 12 and may be basically the same as the Al on the back surface. It may be a Cu-based or Au-based soft metal that is formed.

本発明の第2図に於ける緩衝板11を常温〜50℃では固体
でその後流体となる低融点金属を用いることによつても
実施できる。この場合は半導体装置の動作時に於いては
緩衝板11は液体となり、あたかも沸騰冷却構造と類似
し、セラミツクス上に搭載された発熱する半導体装置の
熱をヒートシンクに効率よく伝える媒体となり得る。
The buffer plate 11 in FIG. 2 of the present invention can also be implemented by using a low melting point metal that is solid at room temperature to 50 ° C. and then becomes a fluid. In this case, when the semiconductor device is in operation, the buffer plate 11 becomes a liquid, and similar to the boiling cooling structure, it can be a medium for efficiently transmitting the heat of the semiconductor device mounted on the ceramic to the heat sink.

一方本発明を遂行する上で重要な緩衝板11はPb,Sn,In,B
i,Cd等の中から選ばれた金属で構成された低融点合金で
液相点が65〜150℃の範囲にあるものが好適である。具
体的にはBi42.5〜67重量%,Pb17.2〜40.2重量%,Sn0〜5
0重量%,In0〜50重量%,Cd0〜12.5重量%から選ばれた
合金であれば良い。
On the other hand, the buffer plate 11 important for carrying out the present invention is Pb, Sn, In, B.
A low melting point alloy composed of a metal selected from i, Cd, etc., having a liquidus point in the range of 65 to 150 ° C. is preferable. Specifically, Bi42.5-67 wt%, Pb17.2-40.2 wt%, Sn0-5
Any alloy selected from 0% by weight, In0 to 50% by weight, and Cd0 to 12.5% by weight may be used.

以上説明したごとき材料を用いて構成された絶縁基板を
用いることによつて発熱する半導体装置を効果的に放熱
できる。
By using the insulating substrate made of the material as described above, it is possible to effectively radiate heat from the semiconductor device that generates heat.

〔発明の効果〕〔The invention's effect〕

本発明によればセラミツクスと比較的熱膨張係数の大き
な金属材料とを直接の接続をさけた圧接構造をとるた
め、比較的SiCやAlN等熱膨張係数の小さなセラミツクス
であつても容易に接続できることや大型セラミツクスの
使用が可能となる。このことは他数の電子部品が混載さ
れる半導体モジユールの熱放散に関する設計が容易にな
るという効果もある。
According to the present invention, since a pressure contact structure that avoids a direct connection between the ceramics and a metal material having a relatively large coefficient of thermal expansion is adopted, even a ceramic having a relatively small coefficient of thermal expansion such as SiC or AlN can be easily connected. And large ceramics can be used. This also has the effect of facilitating the design related to heat dissipation of the semiconductor module in which a different number of electronic components are mounted together.

【図面の簡単な説明】[Brief description of drawings]

第1図,第2図,第3図は本発明の一実施例を示すパワ
ー半導体装置の縦断面図である。 10……ヒートシンク、11……緩衝板、12……セラミツク
ス、13……フレーム、14……端部(接合部)、15……半
導体チツプ、16……カソード端子、17……ゲート端子、
18……アノード端子、20……凹部、30……金属膜。
1, 2 and 3 are vertical sectional views of a power semiconductor device showing an embodiment of the present invention. 10 ...... Heat sink, 11 ...... Buffer plate, 12 ...... Ceramics, 13 ...... Frame, 14 ...... End part (joint part), 15 ...... Semiconductor chip, 16 ...... Cathode terminal, 17 ...... Gate terminal,
18 …… Anode terminal, 20 …… Concave, 30 …… Metal film.

フロントページの続き (72)発明者 井上 広一 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (72)発明者 八野 耕明 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (56)参考文献 実開 昭60−79752(JP,U) 実公 昭59−3580(JP,Y2)Front Page Continuation (72) Inventor Koichi Inoue 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture, Hitachi Research Laboratory Ltd. In the laboratory (56) Bibliography Showa 60-79752 (JP, U) Showa 59-3580 (JP, Y2)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体素子と金属からなるヒートシンク金
属との間に高熱伝導性セラミツクスを挿入して絶縁分離
されている半導体装置において、前記セラミツクス端部
を金属フレームで覆い、該フレームを前記ヒートシンク
に接続することにより前記セラミツクスをヒートシンク
に接続することを特徴とする半導体装置。
1. In a semiconductor device in which a high thermal conductivity ceramic is inserted between a semiconductor element and a heat sink metal made of metal to be insulated and separated, the end portion of the ceramic is covered with a metal frame, and the frame is used as the heat sink. A semiconductor device, wherein the ceramics is connected to a heat sink by connecting.
【請求項2】半導体素子と金属からなるヒートシンクと
の間に高熱伝導性セラミツクスを挿入して絶縁分離され
ている半導体装置において、前記セラミツクスとヒート
シンクとの間に純銅又は純銅よりやわらかい金属箔を介
在させ、前記セラミツクス端部を金属フレームで覆い、
該フレームを前記ヒートシンクに接続することにより前
記セラミツクスをヒートシンクに接続することを特徴と
する半導体装置。
2. In a semiconductor device in which a ceramic having a high thermal conductivity is inserted between a semiconductor element and a heat sink made of metal for insulation separation, pure copper or a metal foil softer than pure copper is interposed between the ceramic and the heat sink. And cover the ceramic end with a metal frame,
A semiconductor device, wherein the ceramics is connected to a heat sink by connecting the frame to the heat sink.
JP13014186A 1986-06-06 1986-06-06 Semiconductor device Expired - Lifetime JPH077810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13014186A JPH077810B2 (en) 1986-06-06 1986-06-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13014186A JPH077810B2 (en) 1986-06-06 1986-06-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62287649A JPS62287649A (en) 1987-12-14
JPH077810B2 true JPH077810B2 (en) 1995-01-30

Family

ID=15026945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13014186A Expired - Lifetime JPH077810B2 (en) 1986-06-06 1986-06-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH077810B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE9114268U1 (en) * 1991-11-15 1992-01-09 Siemens AG, 8000 München High-voltage insulating disc
JP2000091485A (en) 1998-07-14 2000-03-31 Denso Corp Semiconductor device
US6072240A (en) 1998-10-16 2000-06-06 Denso Corporation Semiconductor chip package
JP4085536B2 (en) 1998-11-09 2008-05-14 株式会社日本自動車部品総合研究所 ELECTRIC DEVICE, ITS MANUFACTURING METHOD, AND PRESSURE SEMICONDUCTOR DEVICE
JP3769139B2 (en) * 1999-03-04 2006-04-19 三菱電機株式会社 Power semiconductor module
JP3919398B2 (en) * 1999-10-27 2007-05-23 三菱電機株式会社 Semiconductor module
US6703707B1 (en) 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
US6693350B2 (en) 1999-11-24 2004-02-17 Denso Corporation Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
JP4479121B2 (en) 2001-04-25 2010-06-09 株式会社デンソー Manufacturing method of semiconductor device
US7344296B2 (en) 2003-02-07 2008-03-18 Matsushita Electric Industrial Co., Ltd. Socket for led light source and lighting system using the socket
JP5050633B2 (en) * 2007-05-02 2012-10-17 三菱マテリアル株式会社 Power module substrate with heat sink and power module
CN108011035B (en) * 2017-12-13 2021-02-26 中国电子科技集团公司第二十六研究所 A kind of bonding method of piezoelectric ceramic sheet

Also Published As

Publication number Publication date
JPS62287649A (en) 1987-12-14

Similar Documents

Publication Publication Date Title
JP4015023B2 (en) ELECTRONIC CIRCUIT MEMBER, ITS MANUFACTURING METHOD, AND ELECTRONIC COMPONENT
JPH077810B2 (en) Semiconductor device
JP3793562B2 (en) Ceramic circuit board
JPS6318648A (en) Circuit board using aluminum nitride
JP3794454B2 (en) Nitride ceramic substrate
JP2005285885A (en) Semiconductor device
JPH0439783B2 (en)
JP2517024B2 (en) Ceramic package and its manufacturing method
JPH08222670A (en) Package for mounting semiconductor devices
JP2001053405A (en) Ceramic circuit board
JP3283119B2 (en) Circuit board
JP2001135902A (en) Ceramic circuit board
JP2002076213A (en) Semiconductor element module
JPH0738421B2 (en) Package for semiconductor device
JP4485893B2 (en) Electronic component storage package and electronic device
JPH07211822A (en) Package for storing semiconductor devices
JPH06105722B2 (en) Ceramic bonding method, ceramic package manufacturing method, and ceramic package
JP2001160676A (en) Ceramic circuit board
JP2005252121A (en) Package for housing semiconductor element and manufacturing method thereof
JPH10223809A (en) Power module
JP2000349098A (en) Joint of ceramic substrate and semiconductor element and method of manufacturing the same
JPH0810197Y2 (en) Package for storing semiconductor devices
JP3260512B2 (en) Aluminum nitride circuit board
JPH0793394B2 (en) Ceramic package for mounting semiconductor substrate
JPH0763080B2 (en) Semiconductor package structure