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JPH077811B2 - Semiconductor mounting board - Google Patents
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JPH077811B2 - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH077811B2
JPH077811B2 JP61297367A JP29736786A JPH077811B2 JP H077811 B2 JPH077811 B2 JP H077811B2 JP 61297367 A JP61297367 A JP 61297367A JP 29736786 A JP29736786 A JP 29736786A JP H077811 B2 JPH077811 B2 JP H077811B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
semiconductor mounting
metal cap
conductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61297367A
Other languages
Japanese (ja)
Other versions
JPS63150946A (en
Inventor
圭司 足立
昌留 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP61297367A priority Critical patent/JPH077811B2/en
Publication of JPS63150946A publication Critical patent/JPS63150946A/en
Publication of JPH077811B2 publication Critical patent/JPH077811B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、高密度実装が要求される半導体搭載用基板と
して、ピングリッドアレイ及びハイブリッドIC基板等の
パッケージ用基板に関するものである。
Description: TECHNICAL FIELD The present invention relates to a package substrate such as a pin grid array and a hybrid IC substrate as a semiconductor mounting substrate that requires high-density mounting.

(従来の技術) 半導体搭載用基板においては、その搭載部に半導体素子
を載置固定するとともに、この半導体素子と基板上に形
成した導体回路とをボンディングワイヤ等を使用して電
気的に接続して、半導体装置として利用されるものであ
る。ところで、この基板上に搭載される半導体素子、前
記基板に形成された導体回路及びボンディングワイヤ
は、外部から与えられる衝撃や空気中の湿気等に非常に
影響を受け易いものであるから、これらから当該ボンデ
ィングワイアを種々な方法によって保護しなければなら
ない。
(Prior Art) In a semiconductor mounting substrate, a semiconductor element is mounted and fixed on the mounting portion, and this semiconductor element and a conductor circuit formed on the substrate are electrically connected using a bonding wire or the like. And is used as a semiconductor device. By the way, the semiconductor element mounted on this substrate, the conductor circuit and the bonding wire formed on the substrate are very susceptible to external impacts, moisture in the air, etc. The bonding wire must be protected by various methods.

このような半導体素子等の保護は、通常次のようにして
行なわれている。すなわち、保護の必要な部分(通常半
導体素子の近傍が多い)に封止樹脂を滴下するか、ある
いは保護の必要な部分を金属キャップによって覆うこと
である。特に、金属キャップによって覆う場合にあって
は、半導体搭載用基板と金属キャップとが接着層を介し
て接合されている。この場合に使用される金属キャップ
としては、銅合金やアルミニウム等の材料によって形成
されており、このキャップの耐蝕性及び前記基板との絶
縁性を確保する為に、当該金属キャップの表面には酸化
皮膜又は樹脂皮膜が形成されている。
Such protection of semiconductor elements and the like is usually performed as follows. That is, the sealing resin is dropped onto a portion requiring protection (usually in the vicinity of the semiconductor element) or a portion requiring protection is covered with a metal cap. In particular, in the case of covering with a metal cap, the semiconductor mounting substrate and the metal cap are joined via an adhesive layer. The metal cap used in this case is made of a material such as copper alloy or aluminum, and in order to ensure the corrosion resistance of the cap and the insulation with the substrate, the surface of the metal cap is oxidized. A film or resin film is formed.

金属キャップを使用した封止構造としては、従来は、第
6図に示したようになる。すなわち、半導体搭載用基板
の従来の外形加工では、半導体素子搭載面側の外形周端
部(29)上にメッキ用リード線端部(23)が当該基板の
外周に露出した状態で残るのである。これは、半導体搭
載用基板の導体回路(24)を形成する上で必要なもので
あり、第2図に示された基板平面図及び第4図の基板断
面図にて示す如く、基板製造工程上最終外形加工にてメ
ッキ用リード線も同時に切断される為である。
Conventionally, a sealing structure using a metal cap is as shown in FIG. That is, in the conventional outer shape processing of the semiconductor mounting substrate, the plating lead wire end (23) remains on the outer peripheral edge (29) of the semiconductor element mounting surface side in an exposed state on the outer periphery of the board. . This is necessary for forming the conductor circuit (24) of the semiconductor mounting board, and as shown in the board plan view shown in FIG. 2 and the board sectional view shown in FIG. This is because the lead wire for plating is also cut at the same time as the final outer shape processing.

前記半導体搭載用基板に対して、金属キャップを用いた
封止構造を採った場合に、前記基板の外形と金属キャッ
プの内壁とのクリアランスが小さいと、前記基板上のメ
ッキ用リード線と金属キャップの内壁とが接触し電気的
短絡を発生したり、放電破壊を起し易く、半導体装置と
しての機能を停止させる場合がある。ところが、基板の
外形と金属キャップの内壁とのクリアランスを大きくと
ることは、この種の半導体搭載用基板が小さいことから
非常に困難なのである。
When the semiconductor mounting substrate has a sealing structure using a metal cap and the clearance between the outer shape of the substrate and the inner wall of the metal cap is small, the plating lead wire and the metal cap on the substrate are The inner wall of the semiconductor device may come into contact with the inner wall of the semiconductor device to cause an electrical short circuit or to easily cause discharge breakdown, which may stop the function of the semiconductor device. However, it is very difficult to increase the clearance between the outer shape of the substrate and the inner wall of the metal cap because this type of semiconductor mounting substrate is small.

(発明が解決しようとする問題点) 本発明は以上の様な実状に鑑みてなされたもので、その
解決しようとする問題点は、導体回路を形成した基板の
外形周上のメッキリード線端部が外形周端において露出
することにある。
(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances. The problem to be solved is that the end of a plated lead wire on the outer circumference of a substrate on which a conductor circuit is formed is formed. The part is exposed at the outer peripheral edge.

そして、本発明の目的とするところは、第1図〜第3図
に示すように、半導体搭載用基板上に形成された導体回
路の一部であるメッキ用リード線を含む基板部を積極的
に削除して、前記導体回路の一部であるメッキ用リード
線を切断することにより、前記半導体搭載用基板の外形
周端部に残るメッキ用リード線端部と半導体素子につな
がる導体回路を電気的に絶縁することによって、半導体
装置としての機能を劣化させる電気的短絡等を完全に防
ぐことの可能な半導体搭載用基板を提供することにあ
る。
The object of the present invention is, as shown in FIGS. 1 to 3, to positively set a substrate portion including a lead wire for plating, which is a part of a conductor circuit formed on a semiconductor mounting substrate. By cutting the lead wire for plating, which is a part of the conductor circuit, to electrically connect the end portion of the lead wire for plating remaining on the outer peripheral edge of the semiconductor mounting board to the conductor circuit connected to the semiconductor element. The purpose of the present invention is to provide a semiconductor mounting substrate capable of completely preventing an electrical short circuit or the like that deteriorates the function of the semiconductor device by electrically insulating the substrate.

(問題点を解決するための手段) 以上の問題点を解決するために、本発明の採った手段
は、 「基板に搭載した半導体素子がこの基板の外周に嵌合さ
れる金属キャップによって封止される半導体搭載用基板
において、 この半導体搭載用基板の前記金属キャップが接触する基
板端部の近傍であって、この半導体搭載用基板上に形成
された導体回路の一部を含む基板部を削除して前記導体
回路を部分的に切断する溝部を形成したことを特徴とす
る半導体搭載用基板」 である。
(Means for Solving the Problems) In order to solve the above problems, the means adopted by the present invention is that “a semiconductor element mounted on a substrate is sealed by a metal cap fitted to the outer periphery of the substrate. In the semiconductor mounting substrate, the substrate portion including a part of the conductor circuit formed on the semiconductor mounting substrate is deleted in the vicinity of the end of the substrate where the metal cap of the semiconductor mounting substrate contacts. And a groove portion for partially cutting the conductor circuit is formed.

以下、この手段を図面に示した具体例に従って詳細に説
明する。
Hereinafter, this means will be described in detail according to a specific example shown in the drawings.

第1図は本発明による半導体搭載用基板(1)の一実施
例を示す斜視図であり、一般にピングリッドアレイと呼
ばれるものである。この半導体搭載用基板(1)は、樹
脂素材からなる基板の上面に半導体搭載部と導体回路
(4)が形成されているもので、この半導体搭載用基板
(1)においてはその基板外周近傍に溝加工を施すこと
により溝部(10)が形成されている。これにより、この
半導体搭載用基板(1)にあっては、第2図に示すよう
な基板外周まで延びていた回路形成時に必要であるメッ
キ用リード線がその端部(3)近傍にて切断され、前記
導体回路(4)が基板の外形周端部に至っていない状態
となっている。
FIG. 1 is a perspective view showing an embodiment of a semiconductor mounting substrate (1) according to the present invention, which is generally called a pin grid array. This semiconductor mounting substrate (1) has a semiconductor mounting portion and a conductor circuit (4) formed on the upper surface of a substrate made of a resin material. The groove portion (10) is formed by performing groove processing. As a result, in this semiconductor mounting substrate (1), the lead wire for plating, which has been extended to the outer periphery of the substrate as shown in FIG. 2 and is necessary for forming a circuit, is cut near the end (3). The conductor circuit (4) does not reach the outer peripheral edge of the substrate.

前記基板(1)の溝加工は、この基板(1)の外形加工
後に行う場合もあるが、第2図の基板平面図と第3図の
基板断面図に示すように、外形加工前にシート状で多数
の半導体搭載用基板が連続的に配列されたプリント配線
用基板を、各半導体搭載用基板の外形となる外形線近傍
に溝加工を施すことにより、メッキ用リード線と前記基
板の溝部(10)となる部分を同時に削除した後に、切断
して各半導体搭載用基板(1)に分離する方法でもよ
い。
The groove processing of the substrate (1) may be performed after the outer shape processing of the substrate (1), but as shown in the substrate plan view of FIG. 2 and the substrate sectional view of FIG. The printed wiring board, in which a large number of semiconductor mounting boards are arranged in a continuous pattern, is grooved in the vicinity of the outline of the semiconductor mounting board so that the plating lead wire and the groove portion of the board are formed. It is also possible to remove the portion to be (10) at the same time and then cut and separate each semiconductor mounting substrate (1).

第4図及び第5図には本発明による半導体搭載用基板
(1)に半導体素子(5)を搭載し、この半導体搭載用
基板(5)を覆蓋すべく金属キャップ(2)を基板
(1)に被せた状態の縦断面図が示してある。この半導
体搭載用基板(1)は、樹脂素材から成る基板に半導体
搭載部と外部出力用の導体回路(4)が形成されている
ものであって、この基板外周近傍に溝加工を施して溝部
(10)を形成した後に半導体素子(5)を搭載し、基板
(1)上の導体回路(4)と半導体素子(5)とをボン
ディングワイヤー(6)で結線した後、金属キャップ
(2)により封止が行なわれた構造体である。
4 and 5, a semiconductor element (5) is mounted on a semiconductor mounting substrate (1) according to the present invention, and a metal cap (2) is mounted on the substrate (1) to cover the semiconductor mounting substrate (5). ) Is shown in a vertical cross-section. This semiconductor mounting substrate (1) is a substrate made of a resin material on which a semiconductor mounting portion and a conductor circuit (4) for external output are formed. After the semiconductor element (5) is mounted after forming (10) and the conductor circuit (4) on the substrate (1) and the semiconductor element (5) are connected by a bonding wire (6), a metal cap (2) is formed. The structure is sealed by.

(発明の作用) 前記基板(1)の外周近傍に溝部(10)を形成すること
により、外周端まで延びていたメッキ用リード線端部
(3)と前記基板(1)上の導体回路(4)とを電気的
に絶縁することが可能となり、このメッキ用リード線端
部(3)と金属キャップ(2)の内壁とが接触しても何
んら問題はなく、さらに切断された前記導体回路(4)
は金属キャップ(2)との接着層(7)に被覆されこの
金属キャップ(2)との絶縁性は更に向上する。
(Operation of the Invention) By forming the groove (10) in the vicinity of the outer periphery of the substrate (1), the plating lead wire end (3) extending to the outer periphery and the conductor circuit (on the substrate (1) ( 4) can be electrically insulated from each other, and there is no problem even if the end portion (3) of the lead wire for plating and the inner wall of the metal cap (2) come into contact with each other. Conductor circuit (4)
Is covered with an adhesive layer (7) with the metal cap (2) to further improve the insulating property from the metal cap (2).

次に、本発明を、図面に示した実施例に基づいて詳細に
説明する。
Next, the present invention will be described in detail based on the embodiments shown in the drawings.

(実施例) 実施例1 第2図及び第3図に示す如く、ガラス−エポキシ基板に
て半導体搭載部と導体回路(4)を連続的に形成し、こ
れを切断線(l)にて切断して単片としての基板(1)
を形成する。この単片としての基板(1)に、第4図に
示すように外部入出力端子として導体ピン(8)を設け
たプラスチックピングリッドアレイ用基板(1)を形成
し、この基板(1)の外形端部近傍に溝加工を施して溝
部(10)を形成した。この基板(1)の半導体搭載部に
半導体素子を搭載実装後、基板(1)の外形周端部
(9)を外側から包み込むタイプの金属キャップ(2)
により封止した。この場合、前記基板(1)の外形周端
部に露出していたメッキ用リード線端部(3)は、溝部
(10)により前記導体回路(4)から切断され、接着層
(7)にて前記導体回路(4)は被覆されて金属キャッ
プ(2)と導体回路(4)との電気的絶縁性は向上し
た。
(Example) Example 1 As shown in FIGS. 2 and 3, a semiconductor mounting portion and a conductor circuit (4) were continuously formed on a glass-epoxy substrate and cut along a cutting line (l). And then the substrate as a single piece (1)
To form. A plastic pin grid array substrate (1) provided with conductor pins (8) as external input / output terminals as shown in FIG. 4 is formed on the substrate (1) as a single piece. Groove processing was performed near the end of the outer shape to form a groove portion (10). After mounting and mounting a semiconductor element on the semiconductor mounting portion of the substrate (1), a metal cap (2) of the type enclosing the outer peripheral edge portion (9) of the substrate (1) from the outside.
It was sealed by. In this case, the plating lead wire end portion (3) exposed at the outer peripheral end portion of the substrate (1) is cut from the conductor circuit (4) by the groove portion (10) to form the adhesive layer (7). The conductor circuit (4) is coated so that the electrical insulation between the metal cap (2) and the conductor circuit (4) is improved.

実施例2 第5図に示す如く、ガラス−エポキシ基板にて半導体搭
載部と導体回路(4)を形成し、外部入出力端子として
導体ピン(8)を設けたプラスチックピングリッドアレ
イ用基板(1)を形成し、この基板(1)の外形端部近
傍に溝加工を施して溝部(10)を形成した。この基板
(1)の半導体搭載部に半導体素子を搭載実装後、半導
体素子搭載面側のみ金属キャップ(2)により封止し
た。この場合、基板外形周端部に露出していたメッキ用
リード線端部(3)は、溝部(10)によって前記導体回
路(4)から切断され、接着層にて前記導体回路(4)
は被覆されて導体回路の電気的信頼性は向上した。
Embodiment 2 As shown in FIG. 5, a plastic pin grid array substrate (1) in which a semiconductor mounting portion and a conductor circuit (4) are formed of a glass-epoxy substrate and conductor pins (8) are provided as external input / output terminals. 2) was formed, and a groove portion (10) was formed by subjecting the substrate (1) to groove processing in the vicinity of the outer end portion thereof. After mounting and mounting the semiconductor element on the semiconductor mounting portion of the substrate (1), only the semiconductor element mounting surface side was sealed with the metal cap (2). In this case, the plating lead wire end portion (3) exposed at the outer peripheral edge portion of the substrate is cut from the conductor circuit (4) by the groove portion (10), and the conductor circuit (4) is formed by an adhesive layer.
Was coated to improve the electrical reliability of the conductor circuit.

(発明の効果) 本発明によれば、導体回路(4)が形成された基板
(1)に半導体素子(5)を搭載し、この半導体素子
(5)をボンディングワイヤー(6)等によって結線し
た半導体搭載用基板(1)において、前記半導体素子を
保護する目的で金属キャップ(2)を接合した場合で
も、前記基板(1)の外形周上のメッキ用リード線端部
(3)と導体回路(4)とが溝部(10)によって切断さ
れ、前記メッキ用リード線端部(3)と金属キャップ
(2)が接触しても、導体回路(4)には何んら問題は
なく、さらに前記基板(1)と前記金属キャップ(2)
の接合面に形成される接着層(7)によって完全に絶縁
される。
According to the present invention, the semiconductor element (5) is mounted on the substrate (1) on which the conductor circuit (4) is formed, and the semiconductor element (5) is connected by the bonding wire (6) or the like. In the semiconductor mounting substrate (1), even when the metal cap (2) is joined for the purpose of protecting the semiconductor element, the lead wire end portion (3) for plating on the outer circumference of the substrate (1) and the conductor circuit Even if (4) and (4) are cut by the groove (10) and the plating lead wire end (3) and the metal cap (2) come into contact with each other, there is no problem in the conductor circuit (4). The substrate (1) and the metal cap (2)
It is completely insulated by the adhesive layer (7) formed on the joint surface of the.

これにより、半導体素子を搭載した半導体装置としての
機能を劣化させる電気的短絡等を完全に防ぐことの可能
な半導体搭載用基板が提供できるのである。
As a result, it is possible to provide a semiconductor mounting substrate that can completely prevent an electrical short circuit or the like that deteriorates the function of the semiconductor device mounting the semiconductor element.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る半導体搭載用基板の斜視図、第2
図は当該半導体搭載用基板を形成する状態を示した部分
平面図、第3図は第2図のIII−III線に沿って見た縦断
面図、第4図は第1図に示した半導体搭載用基板に金属
キャップを覆蓋した半導体装置の拡大縦断面図、第5図
は他の形式の半導体装置の拡大縦断面図、第6図は従来
の半導体搭載用基板に金属キャップを覆蓋した半導体装
置の拡大縦断面図である。 符号の説明 1……半導体搭載用基板、2……金属キャップ、3……
メッキ用リード線端部、4……導体回路、5……半導体
素子、6……ボンディングワイヤー、7……接着層、8
……導体ピン、10……溝部。
FIG. 1 is a perspective view of a semiconductor mounting substrate according to the present invention, and FIG.
FIG. 3 is a partial plan view showing a state in which the semiconductor mounting substrate is formed, FIG. 3 is a vertical sectional view taken along line III-III in FIG. 2, and FIG. 4 is a semiconductor shown in FIG. An enlarged vertical sectional view of a semiconductor device in which a mounting substrate is covered with a metal cap, FIG. 5 is an enlarged vertical sectional view of another type of semiconductor device, and FIG. 6 is a semiconductor in which a conventional semiconductor mounting substrate is covered with a metal cap. It is an expanded longitudinal cross-sectional view of an apparatus. Explanation of symbols 1 …… Semiconductor mounting board, 2 …… Metal cap, 3 ……
Lead wire end for plating, 4 ... Conductor circuit, 5 ... Semiconductor element, 6 ... Bonding wire, 7 ... Adhesive layer, 8
…… Conductor pin, 10 …… Groove.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板に搭載した半導体素子がこの基板の外
周に嵌合される金属キャップによって封止される半導体
搭載用基板において、 この半導体搭載用基板の前記金属キャップが接触する基
板端部の近傍であって、この半導体搭載用基板上に形成
された導体回路の一部を含む基板部を削除して前記導体
回路を部分的に切断する溝部を形成したことを特徴とす
る半導体搭載用基板。
1. A semiconductor mounting substrate in which a semiconductor element mounted on the substrate is sealed by a metal cap fitted to the outer periphery of the substrate, wherein a substrate end portion of the semiconductor mounting substrate, which is in contact with the metal cap. A semiconductor mounting substrate, which is formed in the vicinity of the semiconductor mounting substrate and includes a groove portion for partially cutting the conductor circuit by removing a substrate portion including a part of the conductor circuit. .
JP61297367A 1986-12-12 1986-12-12 Semiconductor mounting board Expired - Lifetime JPH077811B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61297367A JPH077811B2 (en) 1986-12-12 1986-12-12 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61297367A JPH077811B2 (en) 1986-12-12 1986-12-12 Semiconductor mounting board

Publications (2)

Publication Number Publication Date
JPS63150946A JPS63150946A (en) 1988-06-23
JPH077811B2 true JPH077811B2 (en) 1995-01-30

Family

ID=17845573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61297367A Expired - Lifetime JPH077811B2 (en) 1986-12-12 1986-12-12 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH077811B2 (en)

Also Published As

Publication number Publication date
JPS63150946A (en) 1988-06-23

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