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JPH0824151B2 - Semiconductor mounting board - Google Patents
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JPH0824151B2 - Semiconductor mounting board - Google Patents

Semiconductor mounting board

Info

Publication number
JPH0824151B2
JPH0824151B2 JP61204727A JP20472786A JPH0824151B2 JP H0824151 B2 JPH0824151 B2 JP H0824151B2 JP 61204727 A JP61204727 A JP 61204727A JP 20472786 A JP20472786 A JP 20472786A JP H0824151 B2 JPH0824151 B2 JP H0824151B2
Authority
JP
Japan
Prior art keywords
substrate
metal cap
semiconductor
lead wire
semiconductor mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61204727A
Other languages
Japanese (ja)
Other versions
JPS6360547A (en
Inventor
昌留 高田
一 矢津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP61204727A priority Critical patent/JPH0824151B2/en
Publication of JPS6360547A publication Critical patent/JPS6360547A/en
Publication of JPH0824151B2 publication Critical patent/JPH0824151B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、高密度実装が要求される半導体搭載用基板
として、ピングリッドアレイ及びハイブリッドIC基板等
のパッケージ用基板に関するものである。
Description: TECHNICAL FIELD The present invention relates to a package substrate such as a pin grid array and a hybrid IC substrate as a semiconductor mounting substrate that requires high-density mounting.

(従来の技術) 半導体搭載用基板においては、その搭載部に半導体素
子を載置固定するとともに、この半導体素子と基板上に
形成した導体回路とをボンディングワイヤー等を使用し
て電気的に接続して、半導体装置として利用されるもの
である。ところで、この基板上に搭載される半導体素
子、前記基板に形成された導体回路及びボンディングワ
イヤーは、外部から与えられる衝撃や空気中の湿気等に
非常に影響を受け易いものであるから、これらを種々な
方法によって保護しなければならない。
(Prior Art) In a semiconductor mounting substrate, a semiconductor element is mounted and fixed on the mounting portion, and the semiconductor element and a conductor circuit formed on the substrate are electrically connected using a bonding wire or the like. And is used as a semiconductor device. By the way, the semiconductor element mounted on this substrate, the conductor circuit and the bonding wire formed on the substrate are very susceptible to external impacts, moisture in the air, etc. It must be protected by various methods.

このような半導体素子等の保護は、通常次のようにし
て行なわれている。すなわち、保護の必要な部分(通常
半導体素子の近傍が多い)に封止樹脂を滴下するか、あ
るいは保護の必要な部分を金属キャップによって覆うこ
とである。特に、金属キャップによって覆う場合にあっ
ては、半導体搭載用基板と金属キャップとが接着層を介
して接合されている。この場合に使用される金属キャッ
プとしては、銅合金やアルミニウム等の材料によって形
成されており、このキャップの耐蝕性及び前記基板との
絶縁性を確保する為に、当該金属キャップの表面には酸
化皮膜又は樹脂皮膜が形成されている。
Such protection of semiconductor elements and the like is usually performed as follows. That is, the sealing resin is dropped onto a portion requiring protection (usually in the vicinity of the semiconductor element) or a portion requiring protection is covered with a metal cap. In particular, in the case of covering with a metal cap, the semiconductor mounting substrate and the metal cap are joined via an adhesive layer. The metal cap used in this case is made of a material such as copper alloy or aluminum, and in order to ensure the corrosion resistance of the cap and the insulation with the substrate, the surface of the metal cap is oxidized. A film or resin film is formed.

金属キャップを使用した封止構造としては、従来は、
第6図に示したようになる。すなわち、半導体搭載用基
板の従来の外形加工では、半導体素子搭載面側の外形周
縁部(29)上に導体回路(24)の一部であるメッキ用リ
ード線の端部(23)が当該基板の外周に露出した状態で
残るのである。これは、メッキ用リード線が半導体搭載
用基板の導体回路(24)にメッキを施すための電気的接
続を促すリード線として必要なものであり、また、第2
図の(a)に示された基板平面図及び第6図の基板断面
図にて示す如く、基板製造工程上最終外形加工にてこの
メッキ用リード線も同時に切断される為である。
Conventionally, as a sealing structure using a metal cap,
It becomes as shown in FIG. That is, in the conventional external processing of the semiconductor mounting board, the end portion (23) of the plating lead wire, which is a part of the conductor circuit (24), is formed on the outer peripheral edge portion (29) on the semiconductor element mounting surface side. Is left exposed on the outer periphery of. This is because the plating lead wire is necessary as a lead wire that promotes electrical connection for plating the conductor circuit (24) of the semiconductor mounting board.
This is because, as shown in the plan view of the board shown in FIG. 6A and the cross-sectional view of the board shown in FIG. 6, this lead wire for plating is also cut at the same time in the final outer shape processing in the board manufacturing process.

このような半導体搭載用基板に対して、金属キャップ
を用いた封止構造を採った場合に、前記基板の外形と金
属キャップの内壁とのクリアランスが小さいと、前記基
板上の導体回路の一部であるメッキ用リード線と金属キ
ャップの内壁とが接触し電気的短絡を発生したり、放電
破壊を起こし易く、半導体装置としての機能を停止させ
る場合がある。
When a sealing structure using a metal cap is adopted for such a semiconductor mounting substrate and the clearance between the outer shape of the substrate and the inner wall of the metal cap is small, a part of the conductor circuit on the substrate is formed. In some cases, the plating lead wire and the inner wall of the metal cap come into contact with each other to cause an electrical short circuit or electric discharge breakdown, which may cause the semiconductor device to stop functioning.

(発明が解決しようとする問題点) 本発明は以上の様な実情に鑑みてなされたもので、そ
の解決しようとする問題点は、半導体搭載用基板の外形
周縁部上に残置する導体回路(メッキ用リード線)の端
部と金属キャップとの近接のし過ぎである。
(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and the problem to be solved is that a conductor circuit left on the outer peripheral edge of the semiconductor mounting substrate ( It is too close to the end of the lead wire for plating) and the metal cap.

そして、本発明の目的とするところは、第1図〜第5
図に示すように、半導体搭載用基板の外形周縁部の一部
を、その表面上に形成された導体回路の一部であるメッ
キ用リード線の端部と共に積極的に削除することによ
り、導体回路(メッキ用リード線)の端部と金属キャッ
プとの間隙を大きくすることによって、半導体装置とし
ての機能を劣化させる電気的短絡等を完全に防ぐことの
可能な半導体搭載用基板を提供することにある。
And, the object of the present invention is that FIGS.
As shown in the figure, a part of the outer peripheral edge of the semiconductor mounting board is positively removed together with the end of the plating lead wire that is a part of the conductor circuit formed on the surface of the semiconductor mounting board. To provide a semiconductor mounting substrate capable of completely preventing an electrical short circuit or the like that deteriorates the function as a semiconductor device by increasing a gap between an end of a circuit (plating lead wire) and a metal cap. It is in.

(問題点を解決するための手段) 以上の問題点を解決するために、本発明の採った手段
は、 「搭載した半導体素子を金属キャップによって封止する
半導体搭載用基板において、 この半導体搭載用基板の外形周縁部の一部を、その表
面上に形成された導体回路と共に斜めに面取り又は段状
に加工して削除することにより、当該半導体搭載用基板
上の導体回路の端部と、前記金属キャップ間に間隙が形
成されるようにしたことを特徴とする半導体搭載用基
板」 である。
(Means for Solving the Problems) In order to solve the above problems, the means adopted by the present invention is, “In a semiconductor mounting substrate for sealing a mounted semiconductor element with a metal cap, A part of the outer peripheral edge portion of the substrate is chamfered or stepped obliquely together with the conductor circuit formed on the surface thereof to remove the end portion of the conductor circuit on the semiconductor mounting substrate, and The semiconductor mounting substrate is characterized in that a gap is formed between the metal caps. "

以下、この手段を図面に示した具体例に従って詳細に
説明する。
Hereinafter, this means will be described in detail according to a specific example shown in the drawings.

第1図は本発明による半導体搭載用基板(1)の一例
を示す斜視図であり、一般にピングリッドアレイの呼ば
れるものである。この半導体搭載用基板(1)は、樹脂
素材から成る基板の上面に半導体素子搭載部と導体回路
(4)が形成されているもので、この半導体搭載用基板
(1)においてはその基板の外形周縁部上に面取り加工
を施こすことにより、基板(1)の一部と共に導体回路
(4)(メッキ用リード線)の端部(3)が削除されて
面取り部(10)が形成されている。これにより、この半
導体搭載用基板(1)にあっては、第2図に示すよう
に、基板の外形周縁部まで延びていた導体回路(4)の
形成時に必要なメッキ用リード線がその端部(3)にて
切断され、この端部(3)が基板の外形より内方に位置
した状態となっている。
FIG. 1 is a perspective view showing an example of a semiconductor mounting substrate (1) according to the present invention, which is generally called a pin grid array. This semiconductor mounting substrate (1) has a semiconductor element mounting portion and a conductor circuit (4) formed on the upper surface of a substrate made of a resin material, and in the semiconductor mounting substrate (1), the outer shape of the substrate. By chamfering the peripheral portion, the end (3) of the conductor circuit (4) (plating lead wire) is removed together with a part of the substrate (1) to form a chamfered portion (10). There is. As a result, in this semiconductor mounting substrate (1), as shown in FIG. 2, the lead wire for plating necessary when forming the conductor circuit (4) extending to the outer peripheral edge of the substrate has its end. It is cut at the portion (3), and the end portion (3) is located inside the outer shape of the substrate.

前記基板の面取り加工は、この基板の外形加工後に行
なう場合もあるが、第2図(a)の基板平面図と第2図
(b)の基板断面図に示すように、外形加工前にシート
状で多数の半導体搭載用基板が連続的に配列されたプリ
ント配線用基板を各半導体搭載用基板の外形となる外形
線上に溝加工を施すことにより、メッキ用リード線と前
記基板の面取り部(10)となる部分を同時に削除した後
に、外形切断して各半導体搭載用基板(1)に分離する
方法でもよい。
The chamfering of the substrate may be performed after the outer shape of the substrate, but as shown in the plan view of the substrate of FIG. 2A and the substrate sectional view of FIG. A printed wiring board in which a large number of semiconductor mounting boards are continuously arranged in a circular pattern is formed on the contour line that is the outer shape of each semiconductor mounting board, so that the plating lead wire and the chamfered portion of the board ( A method may be used in which after removing the portion to be 10) at the same time, the outer shape is cut and separated into the respective semiconductor mounting substrates (1).

半導体搭載用基板の外形周縁部上の導体回路(4)
(メッキ用リード線)と前記基板の一部を削除して、以
上のような面取り部(10)を形成するに際しては、第1
図及び第3図に示すような斜めの面取り加工をするほか
に、第4図に示すような曲面加工により曲面部(11)を
形成することにより削除する方法や、第5図に示すよう
な切削加工により段部(12)を形成することによりメッ
キ用リード線と基板の一部を削除して、メッキ用リード
線の端部(3)を基板内側へ後退させる方法により、こ
のメッキ用リード線の端部(3)と金属キャップ(2)
の内壁との接触を防止して、この金属キャップ(2)と
の絶縁性を向上させる方法をとることも出来る。
Conductor circuit on outer peripheral edge of semiconductor mounting board (4)
When removing the (plating lead wire) and a part of the substrate to form the chamfered portion (10) as described above,
In addition to the diagonal chamfering process as shown in FIGS. 3 and 4, a method of removing by forming the curved surface portion (11) by the curved surface processing as shown in FIG. 4 and the method as shown in FIG. By forming a step (12) by cutting, the plating lead wire and a part of the substrate are deleted, and the end (3) of the plating lead wire is retracted to the inside of the substrate. Wire end (3) and metal cap (2)
It is also possible to adopt a method of preventing the contact with the inner wall of the metal and improving the insulation with the metal cap (2).

第3図には本発明による半導体搭載用基板(1)に半
導体素子(5)を搭載し、この半導体搭載用基板(5)
を覆蓋すべく金属キャップ(2)を基板(1)に被せた
状態の縦断面図が示してある。この半導体搭載用基板
(1)は、樹脂素材から成る基板に半導体素子搭載部と
外部出力用の導体回路(4)が形成されているものであ
って、この基板(1)の外周に面取り加工を施して面取
り部(10)を形成した後に半導体素子(5)を搭載し、
基板(1)上の導体回路(4)と半導体素子(5)とを
ボンディングワイヤー(6)で結線した後、金属キャッ
プ(2)により封止が行なわれた構造体である。
In FIG. 3, a semiconductor element (5) is mounted on a semiconductor mounting substrate (1) according to the present invention, and this semiconductor mounting substrate (5) is mounted.
There is shown a vertical cross-sectional view of the substrate (1) covered with a metal cap (2) to cover the substrate. This semiconductor mounting substrate (1) is a substrate made of a resin material on which a semiconductor element mounting portion and a conductor circuit (4) for external output are formed, and a chamfering process is performed on the outer periphery of the substrate (1). After forming the chamfered part (10), the semiconductor element (5) is mounted,
This is a structure in which a conductor circuit (4) on a substrate (1) and a semiconductor element (5) are connected by a bonding wire (6) and then sealed by a metal cap (2).

(発明の作用) 前記基板(1)の外形周縁部の一部を、その表面上の
導体回路(4)の一部であるメッキ用リード線と共に面
取り加工等することにより、外形周縁部まで延びていた
メッキ用リード線の端部(3)を後退させる事が可能と
なり、このメッキ用リード線の端部(3)と金属キャッ
プ(2)の内壁との接触を防止し又、後退したメッキ用
リード線の端部(3)の露出部は金属キャップ(2)と
の接着層(7)に被覆されることにより、導体回路
(4)と金属キャップ(2)との絶縁性は更に向上す
る。
(Operation of the Invention) A part of the outer peripheral edge portion of the substrate (1) is extended to the outer peripheral edge portion by chamfering the plating lead wire which is a part of the conductor circuit (4) on the surface thereof. It has become possible to retract the end portion (3) of the plating lead wire that had been used, to prevent contact between the end portion (3) of this plating lead wire and the inner wall of the metal cap (2), and to perform the recessed plating. The exposed portion of the end (3) of the lead wire for use is covered with the adhesive layer (7) with the metal cap (2), so that the insulation between the conductor circuit (4) and the metal cap (2) is further improved. To do.

(実施例) 実施例1 第3図に示す如く、ガラス−エポキシ基板により半導
体素子搭載部と導体回路(4)を形成し、外部出力端子
として導体ピン(8)を装着したプラスチックピングリ
ッドアレイ用基板(1)を形成し、この基板(1)の外
形周縁部に面取り加工を施し基板(1)の一部と共にメ
ッキ用リード線の端部(3)を削除して面取り部(10)
を形成した。この基板(1)の半導体素子搭載部に半導
体素子を搭載実装後、金属キャップ(2)により封止し
た。この場合、前記基板(1)の外形周縁部に露出して
いたメッキ用リード線の端部(3)は、基板(1)の外
形より後退し、接着層(7)にて露出していたメッキ用
リード線の端部(3)は被覆されて金属キャップ(2)
とメッキ用リード線の端部(3)との電気的絶縁性は向
上した。
(Example) Example 1 As shown in FIG. 3, for a plastic pin grid array in which a semiconductor element mounting portion and a conductor circuit (4) were formed from a glass-epoxy substrate and conductor pins (8) were mounted as external output terminals. A substrate (1) is formed, the outer peripheral edge of the substrate (1) is chamfered, and the end (3) of the plating lead wire is removed together with a part of the substrate (1) to remove the chamfered portion (10).
Was formed. After mounting and mounting the semiconductor element on the semiconductor element mounting portion of the substrate (1), the semiconductor element was sealed with the metal cap (2). In this case, the end portion (3) of the lead wire for plating, which was exposed at the peripheral portion of the outer shape of the substrate (1), was recessed from the outer shape of the substrate (1) and was exposed at the adhesive layer (7). The end portion (3) of the plating lead wire is covered with a metal cap (2).
The electrical insulation between the end part (3) of the lead wire for plating and the end part (3) was improved.

実施例2 第4図に示す如く、ガラス−エポキシ基板により半導
体素子搭載部と導体回路(4)を形成し、外部出力端子
として導体ピン(8)を装着したプラスチックピングリ
ッドアレイ用基板(1)を形成し、この基板(1)の外
形周縁部に曲面加工を施し基板(1)の一部と共にメッ
キ用リード線の端部(3)を削除して曲面部(11)を形
成した。この基板(11)に半導体素子を相対実装後、金
属キャップ(2)にて封止した。この場合、前記基板
(1)の外形周縁部に露出していたメッキ用リード線の
端部(3)は、基板(1)の外形より後退し、接着層
(7)にて露出していたメッキ用リード線の端部(3)
は被覆されて金属キャップ(2)とメッキ用リード線の
端部(3)との電気的絶縁性は向上した。
Example 2 As shown in FIG. 4, a plastic pin grid array substrate (1) in which a semiconductor element mounting portion and a conductor circuit (4) were formed of a glass-epoxy substrate and conductor pins (8) were mounted as external output terminals. Then, the outer peripheral edge of the substrate (1) was subjected to curved surface processing, and the end portion (3) of the lead wire for plating was removed together with a part of the substrate (1) to form the curved surface portion (11). A semiconductor element was mounted relative to the substrate (11) and then sealed with a metal cap (2). In this case, the end portion (3) of the lead wire for plating, which was exposed at the peripheral portion of the outer shape of the substrate (1), was recessed from the outer shape of the substrate (1) and was exposed at the adhesive layer (7). End of plating lead wire (3)
Was coated to improve the electrical insulation between the metal cap (2) and the end portion (3) of the plating lead wire.

実施例3 第5図に示す如く、ガラス−エポキシ基板により半導
体素子搭載部と導体回路(4)を形成し、外部出力端子
として導体ピン(8)を装着したプラスチックピングリ
ッドアレイ用基板(1)を形成し、この基板(1)の外
形周縁部にザグリ加工を施し基板(1)の一部と共にメ
ッキ用リード線の端部(3)を削除して段部(12)を形
成した。この基板(1)に導体素子を搭載実装後、金属
キャップ(2)にて封止した。この場合、前記基板
(1)の外形周縁部に露出していたメッキ用リード線の
端部(3)は、基板(1)の外形より後退し、接着層
(7)にて露出していたメッキ用リード線の端部(3)
は被覆されて、金属キャップ(2)とメッキ用リード線
の端部(3)との電気的絶縁性は向上した。
Embodiment 3 As shown in FIG. 5, a plastic pin grid array substrate (1) on which a semiconductor element mounting portion and a conductor circuit (4) are formed of a glass-epoxy substrate and conductor pins (8) are mounted as external output terminals. Then, the outer peripheral edge of the substrate (1) was subjected to counterboring, and the end (3) of the plating lead wire was removed together with a part of the substrate (1) to form a step (12). After mounting and mounting the conductor element on this substrate (1), it was sealed with a metal cap (2). In this case, the end portion (3) of the lead wire for plating, which was exposed at the peripheral portion of the outer shape of the substrate (1), was recessed from the outer shape of the substrate (1) and was exposed at the adhesive layer (7). End of plating lead wire (3)
Was coated to improve the electrical insulation between the metal cap (2) and the end (3) of the lead wire for plating.

(発明の構成) 本発明によれば、導体回路(4)が形成された基板
(1)に半導体素子(5)を搭載し、この半導体素子
(5)をボンディングワイヤー(6)等によって結線し
た半導体搭載用基板(1)において、前記半導体素子を
保護する目的で金属キャップ(2)を接合した場合で
も、前記基板(1)の外形周縁部上の導体回路(4)
(メッキ用リード線)の端部(3)と金属キャップ
(2)との間に十分な間隙を確保でき、さらに前記基板
(1)と前記金属キャップ(2)の接合面に形成される
接着層(7)によって完全に絶縁することができる。
(Structure of the Invention) According to the present invention, the semiconductor element (5) is mounted on the substrate (1) on which the conductor circuit (4) is formed, and the semiconductor element (5) is connected by a bonding wire (6) or the like. In the semiconductor mounting substrate (1), even if the metal cap (2) is joined for the purpose of protecting the semiconductor element, the conductor circuit (4) on the outer peripheral edge of the substrate (1).
A sufficient gap can be secured between the end portion (3) of the (plating lead wire) and the metal cap (2), and further, the bonding formed on the joint surface between the substrate (1) and the metal cap (2). It can be completely insulated by the layer (7).

これにより、半導体素子を搭載した半導体装置として
の機能を劣化させる電気的短絡等を完全に防ぐことの可
能な半導体搭載用基板が提供できる。
As a result, it is possible to provide a semiconductor mounting substrate that can completely prevent an electrical short circuit or the like that deteriorates the function of the semiconductor device mounting the semiconductor element.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る半導体搭載用基板の斜視図、第2
図の(a)及び(b)は当該半導体搭載用基板を形成す
る状態を示した部分平面図及び断面図、第3図は第1図
に示した半導体搭載用基板に金属キャップを覆蓋した状
態を示す拡大断面図、第4図及び第5図は本発明の他の
実施例を示す第3図に対応した断面図、第6図は従来の
半導体搭載用基板に金属キャップを覆蓋した状態を示す
断面図である。 符号の説明 1……半導体搭載用基板、2……金属キャップ、3……
メッキ用リード線の端部、4……導体回路、5……半導
体素子、6……ボンディングワイヤー、7……接着層、
8……導体ピン、10……面取り部、11……曲面部、12…
…段部。
FIG. 1 is a perspective view of a semiconductor mounting substrate according to the present invention, and FIG.
(A) and (b) of the figure are partial plan views and sectional views showing a state in which the semiconductor mounting substrate is formed, and FIG. 3 is a state in which a metal cap is covered on the semiconductor mounting substrate shown in FIG. FIG. 4 is an enlarged cross-sectional view showing FIG. 4 and FIG. 5 is a cross-sectional view corresponding to FIG. 3 showing another embodiment of the present invention. FIG. 6 shows a conventional semiconductor mounting substrate with a metal cap covered. It is sectional drawing shown. Explanation of symbols 1 …… Semiconductor mounting board, 2 …… Metal cap, 3 ……
End of plating lead wire, 4 ... Conductor circuit, 5 ... Semiconductor element, 6 ... Bonding wire, 7 ... Adhesive layer,
8 ... Conductor pin, 10 ... Chamfer part, 11 ... Curved part, 12 ...
… Steps.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】搭載した半導体素子を金属キャップによっ
て封止する半導体搭載用基板において、 この半導体搭載用基板の外形周縁部の一部を、その表面
上に形成された導体回路と共に斜めに面取り又は段状に
加工して削除することにより、当該半導体搭載用基板上
の導体回路の端部と、前記金属キャップ間に間隙が形成
されるようにしたことを特徴とする半導体搭載用基板。
1. A semiconductor mounting substrate in which a mounted semiconductor element is sealed with a metal cap. A part of an outer peripheral edge of the semiconductor mounting substrate is chamfered obliquely with a conductor circuit formed on the surface of the semiconductor mounting substrate. A semiconductor mounting board, characterized in that a gap is formed between an end portion of a conductor circuit on the semiconductor mounting board and the metal cap by processing and deleting the stepped shape.
JP61204727A 1986-08-30 1986-08-30 Semiconductor mounting board Expired - Lifetime JPH0824151B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61204727A JPH0824151B2 (en) 1986-08-30 1986-08-30 Semiconductor mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61204727A JPH0824151B2 (en) 1986-08-30 1986-08-30 Semiconductor mounting board

Publications (2)

Publication Number Publication Date
JPS6360547A JPS6360547A (en) 1988-03-16
JPH0824151B2 true JPH0824151B2 (en) 1996-03-06

Family

ID=16495310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61204727A Expired - Lifetime JPH0824151B2 (en) 1986-08-30 1986-08-30 Semiconductor mounting board

Country Status (1)

Country Link
JP (1) JPH0824151B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006922A (en) * 1990-02-14 1991-04-09 Motorola, Inc. Packaged semiconductor device having a low cost ceramic PGA package

Also Published As

Publication number Publication date
JPS6360547A (en) 1988-03-16

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