JPH0778510B2 - Frequency deviation identification circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is an input used for monitoring the frequency deviation of a reference oscillation wave for a frequency synthesizer of a wireless station, monitoring the rotation pulse cycle of a cooling fan motor, and the like. The present invention relates to a circuit for discriminating frequency deviation of signals.

[Conventional technology]

The monitoring function of the radio station constantly monitors the frequency of the oscillation wave for the frequency synthesizer and the rotation pulse of the cooling fan motor, and when it deviates from within the specified frequency deviation, it detects it and externally There may be a function to output an alarm to.

As a conventional method of identifying the frequency deviation to be used for the above application, a frequency discriminating circuit is used to convert the frequency deviation into a voltage value, which is compared with a predetermined voltage threshold value, or a frequency is measured using a frequency measuring instrument. Methods such as measuring and digitally determining the deviation have been considered.

[Problems to be Solved by the Invention]

However, although the former has a simple circuit, there is a problem in accuracy due to analog detection, and high-precision identification cannot be expected. On the contrary, the latter has no problem in accuracy, but has a problem that the circuit scale becomes large.

[Means for Solving the Problems]

The present invention has been made to solve the above problems,
An object of the present invention is to provide a circuit which has a small circuit scale, can be easily integrated into an IC, and can improve the accuracy of identifying frequency deviation.

That is, the circuit of the present invention inputs the reference oscillator 1 for outputting the reference oscillation wave for identifying the frequency deviation of the input frequency of the input signal IN as shown in FIG.
A variable frequency divider 2 that performs 1 / N ₁ and 1 / N ₂ frequency division corresponding to the binary state of the frequency division switching input from the frequency division period 3, and the frequency division pulse output of this variable frequency divider 2. Synchronized with 1/2 divider 3 which divides P _v into 1/2 and supplies it to the division switching input of the variable divider 2 and the trailing edge of the pulse of the divided pulse output Pv of the variable divider 2. And a wasshot trigger circuit 4 for generating a narrow one-shot pulse output R, and an input signal IN shaped into a binary logic using the one-shot pulse output R as a reset input.
Fixed frequency divider 5 that divides by 1 / N and outputs, and one-shot pulse output R as reset input and divided pulse output P _F of fixed frequency divider 5 as trigger input The first D-type flip-flop circuit 6 held in the state, the logic inverter 7 for logically inverting the 1/2 frequency-divided output G, and the cycle determination output DET of the first D-type flip-flop circuit 6 1/2 of the 1/2 divider 3 as input
It is composed of second and third D type flip-flop circuits 8 and 9 which respectively use the frequency dividing force G and the logic inversion output G of the logic inverter 7 as a trigger input, and the second and third D types. The belonging range of the frequency deviation of the input signal IN is discriminated into three types according to the 2-bit state consisting of the discrimination outputs D _θ and D _{1 of the} flip-flop circuits 8 and 9.

[Work]

The reference oscillator wave output from the reference oscillator 1 is a variable frequency divider 2
1 / N ₁ and 1 / N ₂ are respectively divided according to the binary state of the division switching input from the 1/2 divider 3. The frequency-divided pulse output Pv of the variable frequency divider 2 is input to the 1/2 frequency divider 3 and is frequency-divided by 1/2, and the 1/2 frequency division output is input to the variable frequency divider 2 as frequency division switching input. Added.

On the other hand, dividing the pulse output Pv of the variable frequency divider 2 is input to the one-shot trigger circuit 4, a thin one-shot pulse output R in synchronism with the pulse trailing edge of the frequency dividing pulse output P _v is generated. The one-shot pulse output R of the circuit 4 is applied to the fixed frequency divider 5 as a reset input and also to the first D-type flip-flop circuit 6 as a reset input. Since the one-shot pulse output R is applied as a reset input to the fixed frequency divider 5, an input signal shaped into binary logic when no pulse is generated in R.
Divide IN by 1 / N and output. The first D-type flip-flop circuit 6 uses the one-shot pulse output R as a reset input and the divided pulse peripheral force P _F of the fixed frequency divider 5 as a trigger input, and its data is always held in the “H” state. Therefore, the period judgment output DET which is the output is set to "H" when the trigger input of P _F occurs before the output of R.

The 1/2 frequency-divided output G of the 1/2 frequency divider 3 is input to the logic inverter 7 and outputs a logic inverted output. First D
The type flip-flop circuit 8 receives the cycle determination output DET of the second D-type flip-flop circuit 6 as a data input, and receives the 1/2 frequency-divided output G of the 1/2 frequency divider 3 as a trigger input. Output D _θ . The third D-type flip-flop circuit 9 receives the cycle determination output DET of the first D-type flip-flop circuit 6 as a data input and the logic inversion output of the logic inverter 7 as a trigger input, and outputs the output D ₁ . Output.

Output D of the second and third D type flip-flop circuits 8 and 9
_θ and D ₁ are 2-bit discrimination outputs for discriminating the belonging range of the frequency deviation of the input signal IN into three types according to the 2-bit state.

〔Example〕

 Hereinafter, the present invention will be described in detail.

FIG. 1 shows an example of the configuration of a frequency deviation identification circuit embodying the present invention. In the figure, IN is an input signal shaped into a binary logic, and its frequency (input frequency) is a signal whose frequency deviation is to be identified. Reference numeral 1 is a reference oscillator that outputs a reference oscillation wave for identifying the frequency deviation of the input frequency, 2 is the reference oscillation wave of this oscillator 1, and 2 of the frequency division switching inputs from the 1/2 divider 3 described later. Each time the rising or falling of the reference oscillation wave is counted N ₁ and N ₂ times corresponding to the value states “L” and “H”, the fine divided pulse output P _v
A variable frequency divider 3 having a function of outputting the divided frequency pulse output P _v is a 1/2 frequency divider that divides the divided pulse output P _v by 1/2, and the frequency division output G is the variable frequency divider. It is supplied to the frequency division switching input of the frequency divider 2.

Similarly, 4 is a one-shot trigger circuit that inputs the divided pulse output Pv and outputs a narrow one-shot pulse output R in synchronization with the trailing edge of the pulse. Reference numeral 5 is a reset input of the one-shot pulse output R Rise of signal IN,
Alternatively, a fixed frequency divider that outputs a divided pulse output P _F each time the falling change is counted N times, and reset input R is “L”
In the state of (no signal), 1 / N frequency division operation is continued and “H”
In the state of (with signal), the state is reset to the state of the initial value (count 0) at any time.

Reference numeral 6 is a first D-type flip-flop circuit having the one-shot pulse output R as a reset input and the divided pulse output P _F as a trigger input, and its data input (D) is always held in the “H” state. There is.

DET is the output of the flip-flop circuit 6 and is set to the "H" state when the rising of the divided pulse output P _F occurs within the time of the "L" state of the one-shot pulse output R. The cycle determination output detects that the frequency of the divided pulse output P _F is shorter than the cycle of the shot pulse output R in terms of time. 7 is a logic inverter, which is a 1/2 frequency divider 3
The 1/2 frequency-divided output G is input and the logically inverted output thereof is output. 8 and 9 are second and third similar to the flip-flop circuit 6.
D-type flip-flop circuit of
The frequency-divided output G and the logically inverted output are used as trigger inputs, the cycle determination output DET is used as data input, and the respective outputs D _θ and D ₁ are 2-bit identification for identifying the frequency deviation range of the input signal IN. It becomes an output.

Next, based on the configuration example of the present invention shown in FIG. 1, its operation and effect will be described with reference to FIG.

FIG. 2 is a time chart showing an example of the time variation of each signal P _v , G, R, P _F , DET of FIG. 1, where the horizontal axis shows the passage of time and the symbols on the left side correspond to each. The signal names and "H" and "L" attached to the right side indicate the respective binary states.

Here, if the magnitude relation of the frequency division numbers N ₁ and N ₂ designated by the binary states “L” and “H” of the frequency division switching input of the variable frequency divider 2 is N ₁ > N ₂ , The divided pulse output P _v is shown by _dividing the period change of the divided pulse output P _v shown in the uppermost part of FIG.
_{Since the} “L” and “H” states are repeated at each rising change of _v , the time period of the divided pulse output P _v corresponding to the binary state of the 1/2 divided output G is the reference period of the reference oscillator 1. When the frequency of the oscillating wave is set to f _r [Hz], it becomes N ₁ / f _r [second] and N ₂ / f _r [second], respectively, and the former is longer than the latter.

Since the one-shot pulse output R of the one-shot trigger circuit 4 in the third stage from the top of FIG. 2 generates a pulse output synchronized with the trailing edge of the trailing edge of the divided pulse output P _v ,
Its time period is the same as Pv. On the other hand, assuming that the frequency of the input signal IN is f _i , the time period of the divided pulse output P _F of the fixed frequency divider 5 that divides this by 1 / N is, when there is no reset operation by the one-shot pulse output R, N / f _i [seconds]. Now, there are two time periods N ₁ of large and small of the divided pulse output Pv.
/ f _r, in each of N ₂ / f _r, the value of f _i when the time period N / f _i of the divided pulse output P _F is equal putting the f ₁ and f _2, f _1, f ₂ is given by the following equation.

Since N ₁ > N ₂ , the magnitude relation between f ₁ and f ₂ is (1), (2)
From the formula, f ₁ <f ₂ .

Therefore, if the value of the input frequency f _i is f _i <f ₁ , f ₁ <f _i <f ₂ and f
The operation examples of the divided pulse output P _F and the period determination output DET in the case of each range of _i > f ₂ are as follows: the fourth and fifth stages from the top of FIG. 2, the sixth and seventh stages, respectively. Eyes, and the 8th row and the bottom row.

First, in the range of f _i <f ₁ , the period N / f _i of the divided pulse output P _F
Is longer than the longer cycle N ₁ / f _r of the one-shot pulse output R (N / f _i > N ₁ / f _r ), so before the rise of P _F ,
One-shot pulse output R always rises, fixed frequency divider 5
Since the D type flip-flop circuit 6 is reset, the divided pulse output P _F and the cycle judgment output DET are “L”.
It is always kept in the state.

Next, in the range of f ₁ <f _i <f ₂ , the divided pulse output P _F cycle N /
f _i is shorter than the cycle N ₁ / f _r of the longer of the one-shot pulse output R, also shorter longer than the cycle N ₂ / f _r of (N ₁ / f _r>
N / f _i > N ₂ / f _r ), therefore, during the longer period N ₁ / f _r of the one-shot pulse output R, be sure to wait N / f _i [seconds] after the one-shot pulse output R falls. The divided pulse output P _F rises, the cycle determination output DET is set to the “H” state, and this is held until the rising change of the one-shot pulse output R appears next. On the other hand, during the shorter period N ₂ / f _r of the one-shot pulse output R, the divided pulse output P _F1 and the period determination output DET are both in the “L” state, as in the case of f _i <f _1. Will remain held.

In the range of f _i <f ₂ , the divided pulse output P _F cycle N / f
_{Since i} becomes shorter than the shorter cycle N ₂ / f _r of the one-shot pulse output R (N / f _i <N ₂ / f _r ), both the long and short cycles of the one-shot pulse output R , N / f _i seconds after the fall of the one-shot pulse output R, the divided pulse output P _F always rises first, the cycle judgment output DET is set to the “H” state, and the next one-shot pulse output R Hold this until a rising change appears.

From the above, the cycle judgment output DET is indicated on the rising point of the divided pulse output P _v , that is, on the time chart of each cycle judgment output DET in the fifth, seventh and ninth steps from the top of FIG. At the timing marked, the time period N / f of the fixed frequency divider 5
and _i, the time period of the variable frequency divider 2 N ₁ / f _r, will indicate the magnitude comparison result between N ₁ / f _r.

Therefore, the D type flip-flop circuits 8 and 9 are
The symbols (D _θ ) and (D ₁ ) are shown at the bottom of FIG.
Sample the binary state of the cycle judgment output DET at the position marked with ○ at the rising and falling points of the 1/2 frequency-divided output G, and output them as identification outputs D _θ and D ₁ to the outside. Thus, it is possible to uniquely indicate which of the above three ranges the input frequency f _i belongs to by using a 2-bit combination of (D _θ , D ₁ ).

That is, in the example of FIG. 2, f _i <f ₁ , f ₁ <f _i <f ₂ and f _i > f
_For each range of 2, the 2-bit combination of D _θ and D ₁ (D _θ ,
As (D ₁ ), (“L”, “L”), (“H”, “L”) and (“H”, “H”) uniquely correspond to each other, and the deviation of the input frequency f _i is It turns out that they can be identified.

Here, the threshold for discriminating this deviation is substantially given by the above-mentioned f ₁ and f ₂ , and the arithmetic mean value f ₀ of f ₁ and f ₂ =
When (f ₁ + f ₂ ) / 2 is the reference center frequency, the absolute value of the difference between f ₀ and f _i | f _i −f ₀ | is the input frequency deviation, and the accuracy r (relative value) of the input frequency is Given in.

When f _i = f ₁ and f ₂ , the discrimination outputs D _θ and D ₁ change, so r at this time gives an allowable accuracy, and r _MAX
In other words, the following equation is obtained from the equations (1) to (3).

From the equation (4), it is understood that the allowable accuracy r _MAX can be set arbitrarily by appropriately selecting N ₁ and N ₂ .

As an example, the reference oscillator 1 uses a circuit that gives an oscillation frequency f _r that is more than one digit higher than the precision of the input frequency f _i , and sets the values of N ₁ and N ₂ to be sufficiently large, and
By bringing the values of ₁ and N ₂ close to each other, r _MAX can be set smaller than the target value, and discrimination with extremely high accuracy can be performed.

〔The invention's effect〕

As described above in detail, according to the present invention, the set value for identifying the frequency deviation can be given in a programmable manner, and it is possible to easily deal with the high accuracy, and in realizing this, the circuit All of general-purpose logic ICs (TTL, CMOS)
There is an advantage that it can be configured by a combination of and suitable for IC.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an example of the configuration of a frequency deviation discriminating circuit embodying the present invention, and FIG. 2 is a time chart showing an example of a time change of a signal of each part of FIG. 1 ... Reference oscillator, 2 ... Variable frequency divider, 3 ... 1/2 frequency divider, 4 ... One-shot trigger circuit, 5 ... Fixed frequency divider, 7 ... Logical inverter, 6,8 , 9 …… First, second, and third D-type flip-flop circuits, IN …… input signal, _Pv …… divided pulse output, G …… 1/2 divided output, …… logical inversion output, P _F …… Divided pulse output, R …… One-shot pulse output, DET …… Period determination output, D _θ , D ₁ …… Identification output of frequency deviation range.

Claims (1)

[Claims] 1. A reference oscillator 1 for outputting a reference oscillation wave for identifying a frequency deviation of an input frequency of an input signal IN, and a frequency division switching from a 1/2 frequency divider 3 to which the reference oscillation wave is input and which will be described later. A variable frequency divider 2 that performs 1 / N ₁ and 1 / N ₂ frequency division according to the binary state of the input, and the frequency division pulse output P _v of this variable frequency divider 2 is divided by 1/2. Then, a 1/2 frequency divider 3 to be supplied to the frequency division switching input of the variable frequency divider 2 and a thin one-shot pulse output R in synchronization with the trailing edge of the pulse of the frequency division pulse output Pv of the variable frequency divider 2 And a fixed frequency divider 5 for dividing the input signal IN shaped into a binary logic by 1 / N and outputting it by using the one-shot pulse output R as a reset input, and the one-shot data input constantly dividing the pulse output P _F of the fixed frequency divider 5 to a pulse output R a reset input as the trigger input "H" First D held in the state
Type flip-flop circuit 6 and the 1/2 frequency division output G
And a logic inverter 7 for logically inverting, and a period division output DET of the first D-type flip-flop circuit 6 as a data input, a 1/2 frequency division output G of the 1/2 frequency divider 3 and the logic inverter. 7 and second and third D-type flip-flop circuits 8 and 9, respectively, whose logically inverted outputs are used as trigger inputs, and the identification outputs D _{θ of} the second and third D-type flip-flop circuits 8 and 9 are provided. , D _{1 is} a 2-bit state, and the frequency deviation identification circuit is configured to identify the belonging range of the frequency deviation of the input signal IN into three types.