JPH0779327B2 - Branching transmission method for multiplexed signals - Google Patents

Description

The present invention relates to a main station including a digital time division multiplexer connected to a high-speed digital line, and a branch connection device provided in the middle of the high-speed digital line. The present invention relates to a branch relay transmission system for transmitting / receiving a digital time division signal between slave stations including a digital time division multiplexing device connected via a line.

[Conventional technology]

There is a branch service as a high-speed digital line service provided by NTT (Nippon Telegraph and Telephone Corporation).

In this branch service, a branch connection device is installed in the middle of the high-speed digital line, and the high-speed digital signal transmitting / receiving station M1 to M3
The transmission signal to the station is branched to the M2 station located midway between the M1 and M3 stations, or the signal from the M2 station to the M1 station and the M3 station is newly inserted. This service, that is, the function of the branch connection device, includes one that can perform only one-way branch and one that can perform two-way branch.

FIG. 7 shows an example of this kind of branch service. There are four high-speed digital signal transmitting / receiving stations M1 to M4 in which digital multiplexers 1 to 4 are installed, and the main station is a station having a function of managing the whole. It is shown that, in a system in which M1 is used and the others (M2 to M4) are slave stations, bidirectional branch connection devices 5 and 6 are installed in the middle of the transmission path 10 between M1 and M4. The bidirectional branch connection devices 5 and 6 will be described.

FIG. 8 is a functional block diagram of the two-way branch connection devices 5 and 6 shown in FIG.

5 will be described.

In the figure, 51 and 52 are input and output terminals for the A route, 53 and 54 are input and output terminals for the B route, and 55 and 56 are input and output terminals for the C route. In this case, the A, B, and C routes are, for the two-way branch connection device 5 in FIG.
4 stations direction, M2 station direction.

57 to 59 are AND gates. This bidirectional branch connection device 5
The operation of will be described. The signal transmitted from the M1 station enters the A route input terminal N-A51, is branched on the way, and is input to the AND gates 57 and 59. The signal from the M4 station direction is received by the B route input terminal IN-B53 and added to the AND gate 59, so when it is "1", the C route output terminal OUT-C56.
The A-route input terminal IN-A51 input is output as it is, but when it is "0", it becomes "0".

B route output terminal OUT-B54 output is the same as C route input terminal
It is distributed to the IN-C55 input signal. Therefore, when such a bidirectional branching / connecting device is provided in the middle of a line, the channel assignment of transmission signals and the transmission / reception status are as follows.

9 (a) and 9 (b) show a master station (M1), slave stations (M2, M3,
It shows the status of channel allocation and transmission / reception of signals between M4). The number of signal paths required for each route is 4C2 = 6 sets, specifically M1M2, M1M3, M1M4, M2M3, M2M4, M3M4
Is. The arrows indicate signal transmission in both the upward and downward directions. Therefore, the transmission signals sent and received between the master station and the slave stations are time-division multiplexed signals with a minimum of 6 channels. For example, channel 1 (CH1) is on the M1M2 route, channel 2 (CH2) is on the M1M3 route, Assign channel 3 (CH3) to the M1M4 route, channel 4 (CH4) to the M2M3 route, channel 5 (CH5) to the M2M4 route, and channel 6 (CH6) to the M3M4 route. To be In this example, only one channel is used for each route, but it is natural that two channels can be used when the amount of data is large.

Here, as shown in FIG. 9 (a), data A to L are input to the assigned channels, and all "1" is input to the hatched CHs. If the marked CHs are ignored, reception is performed as shown in FIGS. 9 (a) and 9 (b).

As a digital multiplexer capable of branch relay transmission as shown in FIGS. 9 (a) and 9 (b), transmission control is performed so that the transmission signal is data or all "1" corresponding to each channel. However, since it can be realized by controlling the reception so as to receive or ignore the received signal, a device as shown in FIG. 10 can be considered.

In FIG. 10, a multiplexing control circuit 100 controls the transmission frame structure. 104 is an address control memory (ACM ... Same below), 105 is a transmission line interface circuit, 106 is an address bus, 107 is a transmission bus for carrying transmission data, 108 is a reception bus for carrying reception data, 109 is a transmission control signal, 110 Indicates a reception control signal. The transmission control signal 109 controls the transmission signal of the corresponding CH from the multiplexing control circuit. When it is "0", the data from the terminal device is set, and when it is "1", the corresponding CH is set to all "1". The reception control signal 110 also controls the reception signal, and ignores reception, that is, does not output when it is "1", and normally outputs reception output when it is "0".

111-1 to n are 0th-order TDM, which are terminal devices (not shown)
Connect the low speed data from the multiplex data to the transmission bus. Alternatively, it is assumed that a device that demultiplexes the received data from the receiving bus and transfers the data to the terminal device is provided corresponding to the number of CHs.

Description will be given below by taking 111-1 as an example.

An address decoder 112-1 determines whether or not its own device is selected by a signal on the address bus. When the address signal coincides with that of the own device, it outputs the signal and opens the next stage 113-1 transmission gate and 114-1 reception gate. 115-1 is a transmission speed conversion circuit, 116-1 is NAND, 117-1 is OR, 118-1 is AN
Reference numerals D and 119-1 denote NAND gates. 120-1 is a reception buffer memory, 121-1 is a terminal device (not shown)
The multiplexing circuit for multiplexing the bearer rate low-speed data from 1 to 64 kb / s, 122-1 is a demultiplexing device, and 123-1 is an all "1" code for the CH. all "1" Indicates a code generator.

FIG. 11 is an example of a transmission signal of the apparatus shown in FIG. 10 and will be used to explain FIG. 9 in detail.

Next, the operation of the apparatus shown in FIG. 10 will be described with reference to FIG.

(A) About MDM station TDM1 Address decoder 112-1 for 0th-order TDM-1 (111-1)
Receives address data on the address bus 106 and outputs it when it matches the address of its own device, thereby opening the transmission gate 113-1 and the reception gate 114-1.

(Transmission operation) Low-speed data from the terminal device (not shown) is multiplexed by the multiplexing circuit 121-1 to the degree of 64 kb / s (this is referred to as data A), and the NAND gate 119-1 Entered in.

Since the NAND gate 119-1 opens when the transmission control signal 109 from the multiplexing control circuit 100 is "0", the data A is OR gate 117.
It is input to the transmission speed conversion circuit 115-1 via -1. Here, the speed of 64 kb / s is converted to the speed of the high-speed digital line 10, is output to the transmission bus 107 via the transmission gate 113-1 and is transmitted to the line 10 via the transmission line interface circuit 105.

Next, the address moves to CH2, so the address decoder 112-2
Coincides with its own device, and the 0th-order TDM 111-2 sends data B to the transmission bus 107. Similarly, data C is placed on CH3 by the 0th-order TDM111-3 and transmitted.

In the 0th-order TDM 111-4, since the transmission control signal 109 from the multiplexing control circuit 101 is set to "1", the NAND gate 119-4 is closed and the AND gate 118-4 is opened, all "1" encoding circuit 123- Four
Is output to the transmission speed conversion circuit 115-4 via the OR 117-4. Similarly, all “1” is added to CH4 and transmitted. The same applies to CH5 and CH6.

(Reception operation) The reception gate 114-1 of the 0th-order TDM 111-1 opens and the reception bus 108
The received data is input to the NAND gate 116-1. Since the reception control signal 110 from the multiplexing control circuit 100 is "0", the reception signal CH1 (data G) coming via BU5 is taken and input to the reception buffer memory 120-1. The data G of CH1 is demultiplexed into low speed data by the demultiplexing circuit 122-1 and sent to the terminal device. Similarly, 0th order TDM111-2
Then, the data H is received on CH2, and the data I is received on CH3 in the 0th-order TDM111-3. However, 0th order TDM111-4
Then, the reception control signal 110 from the multiplexing control circuit 100 is "1".
Therefore, the NAND gate 116-4 is not opened and the CH4 reception signal is not received. That is, the received signal is ignored. Similarly 0
In the next TDM114-5 and 114-6, the reception control signal 110 is "1",
All CH5 and CH6 received signals are ignored.

(A) About M2 station TDM2 (Transmission operation) Transmit the transmission control signal 109 of the M2 station TDM2 multiplexing control circuit 100 to CH1.
~ If you set 0,1,1,0,0,1 corresponding to CH6, 0th order TD
From each of M111-1 to 111-6, data G, all “1”, all “1”, data D, data E, all “1” are associated with CH1 to CH6 on line 1.
Dispatched to 0. When this signal goes through BU1 (5)
The AND gates 57 and 58 provide signals as shown at the output terminals 54 and 52.

(Reception operation) CH1 for the reception control signal 110 of the multiplexing control circuit 100 of the M2 station TDM2
~ If you set 0,1,1,0,1,1 corresponding to CH6, 0th order TD
From each of M111-1 to 111-6, data A, ignore, ignore, data J, data K, ignore and receive data A from M1 station, data J from M3 station, and data K from M4 station. It

Hereinafter, also for the M3 station TDM3 and the M4 station TDM4, similarly, the transmission signal and the reception signal are transmitted or received according to the preset transmission control signal 109 and reception control signal 110. Transmission control signal 109, reception control signal 110 from the multiplexing control circuit 100 of each TDM
Each has a fixed route.

In this way, the time-division-multiplexed signal is dropped or inserted at each branch point, and data is sent to each slave station.
It can also receive data from slave stations.

[Problems to be solved by the invention]

The conventional branch transmission system is configured as described above, and one route is assigned to each channel and fixed. For this reason, the transmission capacity for each route is fixed.For example, at night, when viewed from each slave station, the upward direction, that is, M2 → M
It was not possible to flexibly respond to the demand for increasing the amount of data in the direction of 1, M3 → M1, M4 → M1.

The present invention has been made to solve the above-mentioned problems, and can flexibly deal with the data amount of a route that changes depending on the time of day or time of day while maintaining the principle of constant-speed branching in the branch connection device. The purpose is to obtain a branch transmission system.

[Means for solving problems]

For this reason, the branch transmission method according to the present invention temporarily and temporarily allocates all or a part of the channels between the master station and the slave stations among the allocated channels to the specific slave station-the master station for each information route. The number should be increased, and it should be changed over time to send and receive multiplexed signals. In other words, the allocation of channels between the master station and each slave station should be changed at a predetermined time. It is characterized by.

[Action]

The number of channels assigned to each information route is changed with time. As a result, a plurality of channels can be assigned to one direction at a certain time (or a time zone), the data amount of a certain route is not congested, and the data can be transmitted smoothly.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, the same numbers as in FIG. 10 indicate the same contents. A multiplexing control circuit 101 includes a microprocessor 102 and a memory 103, and includes a transmission control signal 109 and a reception control signal 110.
Can be set in a wide range and can be made variable.

FIG. 2 shows an example of the setting pattern of each TDM1 to 4 of the M1 to M4 stations at each time or time zone of T0, T1, T2 and T3. Shows an output setting table of the reception control signal 110.

T0 to T3 are examples of set time (or time zone) patterns. For example, T0 is a normal state, T1 is a time pattern in which data is concentrated from the M2 station and transmitted to the M1 station, and T2 is M3.
Time pattern to centralize data from the station and send it to the M1 station,
T3 is a time pattern in which data is concentrated from the M4 station and transmitted to the M1 station. Memory 1 of each multiplexing control circuit 101 of M1 to M4 stations
The transmission control signal 109 shown in Tables (1) and (2) of FIG.
And the output setting table of the reception control signal 110 is input, and the microprocessor μp102 controls so as to output the memory outputs all at once when the corresponding time comes.

By doing so, the transmission signal can be made as shown in FIG. 3 in the time pattern T1. Similarly, time pattern T2
4 and the time pattern T3 can be as shown in FIG. This is summarized in FIG. 6 (a).

This is the number of transmission channels in the direction of M2 → M1 station, and the transmission CH in the direction of M3 → M1 station
Number, the number of transmission channels from M4 to M1 station is 6th
It becomes as shown in FIG. In other words, at time T1, M2 → CH to M1 station
Data can be transmitted using 3CH from 1 to CH3. At time T2, data can be transmitted from M3 to M1 station by using 3CH from CH1 to CH3. At time T3, the same can be done for the M4 → M1 station. In such a case the time T0, T
By changing the interval of 1, T2, T3, it is possible to increase the transmission amount for the route with a large amount of data.

In this embodiment, the two-way branch connecting device is as shown in FIG.
Since it is composed of AND gates, all “1” shall be transmitted for CHs with hatching as shown in FIG. 9 (a), and therefore, in 0th-order TDM111-1 to n shown in FIG. In this case, all "1" code generation circuits 123-1 to 123-n are provided.
Although all bits in CH are set to "1", if the two-way branch connection device is composed of NAND gates, all "0" will be transmitted instead of all "1". n
Is an all "0" code generator.

In FIGS. 2 and 3, the number of channels allocated to each station is one, but the same applies when a plurality of channels are allocated depending on the amount of data.

FIG. 6 (c) shows another pattern setting at time T0.
CH1 to M2 → M1 station and CH2 to M3 → M1 station (always)
Each CH assigned to M4 → M1 station is C at time T1.
It is shown that H1 and CH3 can be assigned to M2 → M1 station, CH2 can be assigned to M3 → M1 station, and CH1 can be assigned to M2 → M1 station and CH2 and CH3 can be assigned to M2 → M3 station at time T2. This is, for example, the case where the M4 station is normal in the daytime time zone T0, but when it becomes free in the nighttime time zones T1 and T2, it tries to effectively collect data from the M2 station and the M3 station, so that the route from M4 to M1 is used. CH3 assigned to is for data transmission of M2 → M1 station in T1 and M3 → M in T2
It intends to change the route and use it for the data transmission of one station. As a result, each data G, H, I is smoothly transmitted to the master station M1.

〔The invention's effect〕

As described above, according to the present invention, since the number of channels allocated for each information route is changed with time to transmit / receive a multiplexed signal, information can be efficiently transmitted / received in accordance with a time zone. Becomes

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexer for showing an embodiment of the present invention, FIGS. 2 (1) and 2 (2) are transmission / reception control signal setting charts, and FIGS. 3-5 are channel allocation and transmission signals. An example situation diagram, FIGS. 6 (a), (b), and (c) are channel assignment change charts, FIG. 7 is a transmission system diagram, FIG. 8 is a bidirectional branch connection device block diagram, and FIG. 9 (a). , (B) are channel allocation and transmission / reception status diagrams, FIG. 10 is a conventional multiplexer configuration diagram, and FIG. 11 is a channel allocation and transmission / reception status diagram according to the conventional method. M1 ... Master station, M2-M4 ... Slave stations, 1-4 ... Digital multiplexer (TDM), 5 ... Two-way branch connection (BU).

Claims (1)

[Claims] 1. When transmitting and receiving digital signals between a master station and a plurality of slave stations via a high-speed digital line, channels are provided according to the number of route combinations between the master station and the slave stations and the slave stations. Divide and multiplex to form a multiplexed signal,
In the branch transmission method of a digital signal that allocates information or control information for each transmission destination for each channel and that is transmitted via a branch connection device provided in the middle of a high-speed digital line, A branched transmission system for multiplexed signals, characterized in that the allocation of channels between a station and each slave station is changed.