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JPH078148B2 - Bridge inverter circuit - Google Patents
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JPH078148B2 - Bridge inverter circuit - Google Patents

Bridge inverter circuit

Info

Publication number
JPH078148B2
JPH078148B2 JP60025736A JP2573685A JPH078148B2 JP H078148 B2 JPH078148 B2 JP H078148B2 JP 60025736 A JP60025736 A JP 60025736A JP 2573685 A JP2573685 A JP 2573685A JP H078148 B2 JPH078148 B2 JP H078148B2
Authority
JP
Japan
Prior art keywords
semiconductor switch
semiconductor
switches
turned
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60025736A
Other languages
Japanese (ja)
Other versions
JPS61185077A (en
Inventor
隆裕 原
Original Assignee
池田電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 池田電機株式会社 filed Critical 池田電機株式会社
Priority to JP60025736A priority Critical patent/JPH078148B2/en
Publication of JPS61185077A publication Critical patent/JPS61185077A/en
Publication of JPH078148B2 publication Critical patent/JPH078148B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はブリツジ接続された半導体スイツチの交互導通
により直流電源から交流電圧を出力するブリツジインバ
ータ回路に関する。
The present invention relates to a bridge inverter circuit for outputting an AC voltage from a DC power supply by alternately conducting bridge-connected semiconductor switches.

〔従来の技術〕[Conventional technology]

第4図はブリツジインバータ回路の基本回路を示し、同
図において、(1)は第1半導体スイツチ、(2)は第
2半導体スイツチ、(3)は第3半導体スイツチ、
(4)は第4半導体スイツチで、これらはトランジスタ
により構成されている。(5)は100V〜200Vの直流電
源、(6)は負荷である。第1半導体スイツチ(1)及
び第2半導体スイツチ(2)は直流電源(5)のマイナ
ス側に接続され、第3半導体スイツチ(3)及び第4半
導体スイツチ(4)は直流電源(5)のプラス側に接続
されている。
FIG. 4 shows a basic circuit of the bridge inverter circuit. In FIG. 4, (1) is a first semiconductor switch, (2) is a second semiconductor switch, and (3) is a third semiconductor switch.
(4) is a fourth semiconductor switch, which is composed of a transistor. (5) is a DC power supply of 100V to 200V, and (6) is a load. The first semiconductor switch (1) and the second semiconductor switch (2) are connected to the negative side of the DC power supply (5), and the third semiconductor switch (3) and the fourth semiconductor switch (4) are connected to the DC power supply (5). It is connected to the plus side.

このインバータ回路では、半導体スイツチ(1)(2)
(3)(4)をオンオフさせて負荷(6)に交流電圧を
印加するのである。この場合第1及び第2半導体スイツ
チ(1)(2)はエミツタが電源(5)のマイナス端子
と接続されている為、第5図に示すように半導体スイツ
チ(7)(8)を設けることにより、第1及び第2半導
体スイツチ(1)(2)をオン、オフできるが、第3及
び第4半導体スイツチ(3)(4)は電源(5)によつ
てオン、オフすることは困難であり、通常第6図に示す
如くドライブ用の電源(9)(10)を別に設けている
(第1及び第2半導体スイツチ(1)(2)のドライブ
用としても約10V程度の別電源を設けることが多
い。)。又ドライブ用の半導体スイツチ(7)(8)
(11)(12)をオン、オフさせる制御回路(13)の電源
は直流電源(14)より得ていることが多い。半導体スイ
ツチ(7)(8)をオン、オフさせる信号は、電源
(5)(14)の一端が接続されている為、第7図に示す
ような回路構成によつて容易に得られるが、半導体スイ
ツチ(3)(4)をオン、オフさせるには、制御回路
(13)の電源(14)と電源(9)(10)とが直接接続さ
れていない為、従来フオトカプラー(15)やトランス等
を用い絶縁してオン、オフさせていた。
In this inverter circuit, semiconductor switches (1) (2)
(3) and (4) are turned on and off to apply an AC voltage to the load (6). In this case, since the emitters of the first and second semiconductor switches (1) and (2) are connected to the negative terminal of the power source (5), the semiconductor switches (7) and (8) should be provided as shown in FIG. Thus, the first and second semiconductor switches (1) and (2) can be turned on and off, but it is difficult to turn on and off the third and fourth semiconductor switches (3) and (4) by the power supply (5). Therefore, as shown in FIG. 6, a drive power source (9) (10) is usually provided separately (a separate power source of about 10 V is also used for driving the first and second semiconductor switches (1) and (2)). Often provided.). Also, semiconductor switches for driving (7) (8)
The power supply for the control circuit (13) that turns on (11) and (12) is often obtained from the DC power supply (14). A signal for turning on and off the semiconductor switches (7) and (8) can be easily obtained by the circuit configuration shown in FIG. 7 because one end of the power supplies (5) and (14) is connected. In order to turn the semiconductor switches (3) and (4) on and off, the power supply (14) of the control circuit (13) and the power supplies (9) and (10) are not directly connected, so the conventional photo coupler (15) and It was turned on and off with insulation using a transformer or the like.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従つて、従来ではフオトカプラ等を要し回路構成が非常
に複雑で、製造費も高く付いた。
Therefore, conventionally, a photo coupler or the like is required, the circuit configuration is very complicated, and the manufacturing cost is high.

本発明は上記問題点に鑑み、フオトカプラーやトランス
等を用いず簡単な回路構成で、プラス側の半導体スイツ
チをマイナス側の半導体スイツチに対応して確実にオ
ン、オフし得るようにしたものである。
In view of the above problems, the present invention has a simple circuit configuration without using a photocoupler, a transformer, etc., and is capable of reliably turning on and off the positive side semiconductor switch in correspondence with the negative side semiconductor switch. is there.

〔問題点を解決するための手段〕[Means for solving problems]

この技術的課題を解決する本発明の技術手段は、直流電
源(5)にブリツジ接続されたマイナス側の第1及び第
2半導体スイツチ(1)(2)とプラス側の第3及び第
4半導体スイツチ(3)(4)とを備え、第1及び第4
半導体スイツチ(1)(4)と第2及び第3半導体スイ
ツチ(2)(3)との交互導通により、第1及び第3半
導体スイツチ(1)(3)の接続点と第2及び第4半導
体スイツチ(2)(4)の接続点との間に、交流電圧を
出力するようにしたブリツジインバータ回路において、
前記第1、第2、第3及び第4半導体スイッチ1,2,3,4
が、夫々NPNトランジスタで構成され、第3及び第4半
導体スイッチ3,4の各ベースに、ベース電流を供給する
直流電源18,19が抵抗20,21を介して夫々接続され、第1
半導体スイッチ1のオン時に第3半導体スイッチ3への
ベース電流を阻止するように前記直流電源18から第1半
導体スイッチ1へ電流を流すダイオード22と、第2半導
体スイッチ2のオン時に第4半導体スイッチ4へのベー
ス電流を阻止するように前記直流電源19から第2半導体
スイッチ2へ電流を流すダイオード23とが、第3及び第
4半導体スイッチ3,4のベース側と第1及び第2半導体
スイッチ1,2との間に夫々接続され、第1半導体スイッ
チ1及び第2半導体スイッチ2の駆動によって第3半導
体スイッチ3及び第4半導体スイッチ4をオンオフさせ
るように、第1半導体スイッチ1及び第2半導体スイッ
チ2を交互導通させる制御回路が設けられている点にあ
る。
The technical means of the present invention for solving this technical problem is to provide negative side first and second semiconductor switches (1) and (2) and positive side third and fourth semiconductors which are bridge-connected to a DC power source (5). A switch (3) (4) and a first and a fourth
The alternating conduction between the semiconductor switches (1) (4) and the second and third semiconductor switches (2) (3) causes the connection points of the first and third semiconductor switches (1) (3) and the second and fourth semiconductor switches. In a bridge inverter circuit that outputs an AC voltage between the connection points of the semiconductor switches (2) and (4),
The first, second, third and fourth semiconductor switches 1, 2, 3, 4
Are respectively composed of NPN transistors, and DC power sources 18 and 19 for supplying a base current are respectively connected to the bases of the third and fourth semiconductor switches 3 and 4 via resistors 20 and 21, respectively.
A diode 22 for flowing a current from the DC power supply 18 to the first semiconductor switch 1 so as to block a base current to the third semiconductor switch 3 when the semiconductor switch 1 is turned on, and a fourth semiconductor switch when the second semiconductor switch 2 is turned on. A diode 23 for supplying a current from the DC power supply 19 to the second semiconductor switch 2 so as to block the base current to the fourth semiconductor switch 4, the base side of the third and fourth semiconductor switches 3 and 4, and the first and second semiconductor switches. The first semiconductor switch 1 and the second semiconductor switch 4 are connected between the first semiconductor switch 1 and the second semiconductor switch 2, respectively, so that the third semiconductor switch 3 and the fourth semiconductor switch 4 are turned on and off by driving the first semiconductor switch 1 and the second semiconductor switch 2. The point is that a control circuit for alternately conducting the semiconductor switches 2 is provided.

〔実施例〕〔Example〕

以下、本発明を図示の実施例に従つて説明すると、第1
図において、(18)(19)は10V程度のドライブ用の直
流電源で、第3及び第4半導体スイツチ(3)(4)の
ベースに夫々抵抗(20)(21)を介して接続され、半導
体スイツチ(3)(4)にベース電流を供給する。(2
2)(23)(24)(25)(26)(27)はダイオードで、
ダイオード(22)は第3半導体スイツチ(3)のベース
側と第1半導体スイツチ(1)との間に接続され、第1
半導体スイツチ(1)のオン時に第3半導体スイツチ
(3)へのベース電流を阻止するように直流電源(18)
から第1半導体スイツチ(1)へ電流を流す。ダイオー
ド(23)は第4半導体スイツチ(4)のベース側と第2
半導体スイツチ(2)との間に接続され、第2半導体ス
イツチ(2)のオン時に第4半導体スイツチ(4)への
ベース電流を阻止するように直流電源(19)から第2半
導体スイツチ(2)へ電流を流す。なお、第1半導体ス
イツチ(1)及び第2半導体スイツチ(2)は図示省略
の制御回路により従来と同様に交互導通するようにオン
オフ制御される。
The present invention will be described below with reference to the illustrated embodiment.
In the figure, (18) and (19) are direct current power supplies of about 10 V for driving, which are connected to the bases of the third and fourth semiconductor switches (3) and (4) via resistors (20) and (21), respectively. A base current is supplied to the semiconductor switches (3) and (4). (2
2) (23) (24) (25) (26) (27) are diodes,
The diode (22) is connected between the base side of the third semiconductor switch (3) and the first semiconductor switch (1).
DC power supply (18) so as to block the base current to the third semiconductor switch (3) when the semiconductor switch (1) is turned on.
To the first semiconductor switch (1). The diode (23) is connected to the base side of the fourth semiconductor switch (4) and the second semiconductor switch (4).
The second semiconductor switch (2) is connected between the semiconductor switch (2) and the DC power source (19) so as to block the base current to the fourth semiconductor switch (4) when the second semiconductor switch (2) is turned on. ) To the current. The first semiconductor switch (1) and the second semiconductor switch (2) are ON / OFF controlled by a control circuit (not shown) so that they are alternately conducted as in the conventional case.

次に動作を説明する。第1半導体スイツチ(1)がオフ
のとき、第2図に示す如く第3半導体スイツチ(3)に
直流電源(18)より抵抗(20)を介してベース電流IBが
流れ、該半導体スイツチ(3)がオンしている。第1半
導体スイツチ(1)がオフすると、ダイオード(22)
(24)がオンし、抵抗(20)を介して流れていた電流は
ダイオード(22)(24)を介して流れ、第3半導体スイ
ツチ(3)へのベース電流IBは流れなくなつて、第3半
導体スイツチ(3)はオフする。即ち、第2図に示す点
(b)の電圧は点(a)を基準として約0Vとなる(点
(c)は−0.6V、点(b)は−0.6V+0.6V=0V)。
Next, the operation will be described. When the first semiconductor switch (1) is off, the base current IB flows from the DC power source (18) through the resistor (20) to the third semiconductor switch (3) as shown in FIG. ) Is on. When the first semiconductor switch (1) is turned off, the diode (22)
(24) is turned on, the current flowing through the resistor (20) flows through the diodes (22) (24), and the base current IB to the third semiconductor switch (3) stops flowing. 3 The semiconductor switch (3) is turned off. That is, the voltage at the point (b) shown in FIG. 2 is about 0V with respect to the point (a) (point (c) is -0.6V, point (b) is -0.6V + 0.6V = 0V).

また、同様にして第2半導体スイツチ(2)がオフのと
き、第4半導体スイツチ(4)に直流電源(19)より抵
抗(21)を介してベース電流IBが流れ、該半導体スイツ
チ(4)がオンしている。第1半導体スイツチ(1)が
オフすると、ダイオード(23)(25)がオンし、抵抗
(7)を介して流れていた電流はダイオード(23)(2
5)を介して流れ、第4半導体スイツチ(4)へのベー
ス電流IBは流れなくなつて、第4半導体スイツチ(4)
はオフする。
Similarly, when the second semiconductor switch (2) is off, the base current IB flows from the DC power source (19) to the fourth semiconductor switch (4) through the resistor (21), and the semiconductor switch (4) is turned on. Is on. When the first semiconductor switch (1) is turned off, the diodes (23) (25) are turned on, and the current flowing through the resistor (7) is changed to the diode (23) (2
5), the base current IB to the fourth semiconductor switch (4) stops flowing, and the fourth semiconductor switch (4)
Turn off.

第3図は他の実施例を示し、ダイオード(30)(31)
(32)(33)(34)及びダイオード(35)(36)(37)
(38)(39)を設けたものである。前記第1図の回路で
は負荷(6)が接続されておらず負荷電流ILが流れてい
ない場合は、ダイオード(24)(25)がオフし、抵抗
(20)(21)を介して流れる電流は第3半導体スイツチ
(3)又は第4半導体スイツチ(4)のベースへ流れ、
第3及び第4半導体スイツチ(3)(4)がオンしてし
まうことになるが、第3図のような回路構成にすること
により、このような不都合を防止できる。即ち、この回
路の場合第1半導体スイツチ(1)がオンのとき、点
(a)を基準とする点(b)の電圧は、ダイオード(2
6)の電圧が0.6V、第1半導体スイツチ(1)のコレク
タ、エミツタ間電圧が約1V、ダイオード(22)の電圧が
0.6Vであるから、これらの電圧を加算して求めればよ
く、2.2Vとなるが、ダイオード(30)(31)(32)(3
3)により点(b)が3V以上にならないとオンしないよ
うすると、第1半導体スイツチ(1)がオンしたとき第
3半導体スイツチ(3)がオフしないようになる。また
第4半導体スイツチ(4)についても同様である。
FIG. 3 shows another embodiment, in which diodes (30) (31)
(32) (33) (34) and diodes (35) (36) (37)
(38) and (39) are provided. In the circuit shown in FIG. 1, when the load (6) is not connected and the load current IL is not flowing, the diodes (24) (25) are turned off and the current flowing through the resistors (20) (21). Flows to the base of the third semiconductor switch (3) or the fourth semiconductor switch (4),
Although the third and fourth semiconductor switches (3) and (4) will be turned on, such inconvenience can be prevented by using the circuit configuration shown in FIG. That is, in the case of this circuit, when the first semiconductor switch (1) is turned on, the voltage at the point (b) with respect to the point (a) becomes the diode (2
The voltage of 6) is 0.6V, the voltage between the collector of the first semiconductor switch (1) and the emitter is about 1V, and the voltage of the diode (22) is
Since it is 0.6V, it suffices to add these voltages to obtain 2.2V, but the diode (30) (31) (32) (3
If the point (b) is not turned on unless the point (b) becomes 3 V or more according to 3), the third semiconductor switch (3) is not turned off when the first semiconductor switch (1) is turned on. The same applies to the fourth semiconductor switch (4).

〔発明の効果〕〔The invention's effect〕

本発明によれば、第3及び第4半導体スイツチ(3)
(4)のベースにベース電流を供給する直流電源(18)
(19)と、第1半導体スイツチ(1)のオン時に第3半
導体スイツチ(3)へのベース電流を阻止するダイオー
ド(22)と、第2半導体スイツチ(2)のオン時に第4
半導体スイツチ(4)へのベース電流を阻止するダイオ
ード(23)とを設けているので、従来のようにフォトカ
プラーやトランス等を用いず、非常に簡単な回路構成
で、マイナス側の第1又は第2半導体スイッチ1,2がオ
ンしたとき、これに対応してプラス側の第3又は第4半
導体スイッチ3,4を確実にオフさせることができ、第1
半導体スイッチ1と第3半導体スイッチ3、第2半導体
スイッチ2と第4半導体スイッチ4が夫々同時に導通す
るのを防止できる。しかも、一方の第1半導体スイッチ
1及び第2半導体スイッチ2の駆動によって他方の第3
半導体スイッチ3及び第4半導体スイッチ4をオンオフ
させることができるので、第1半導体スイッチ1及び第
2半導体スイッチ2のみを交互導通するように制御すれ
ばよく、インバータ回路の制御回路が非常に簡単な構成
になるし、さらに、前記第1、第2、第3及び第4半導
体スイッチ1,2,3,4が、夫々NPNトランジスタで構成され
ているので、高耐圧のトランジスタを使用しても、PNP
トランジスタの場合と異なり安上りであり、従って、イ
ンバータ回路全体を製造容易でかつ安価に提供すること
ができる。また、上記の如く第1半導体スイッチ1及び
第2半導体スイッチ2の駆動によって他方の第3半導体
スイッチ3及び第4半導体スイッチ4をオンオフさせる
ことができるので、電源より半導体スイッチ1,3又は半
導体スイッチ2,4を介して短絡電流が流れる恐れがな
く、短絡電流による半導体スイッチ1,2,3,4の故障も防
止でき、その実用的効果は著大である。
According to the invention, third and fourth semiconductor switches (3)
DC power supply (18) that supplies base current to the base of (4)
(19), a diode (22) for blocking a base current to the third semiconductor switch (3) when the first semiconductor switch (1) is on, and a fourth diode (22) when the second semiconductor switch (2) is on.
Since the diode (23) for blocking the base current to the semiconductor switch (4) is provided, it is a very simple circuit configuration without using a photocoupler or a transformer as in the conventional case, and the first side on the minus side or When the second semiconductor switches 1 and 2 are turned on, the positive side third or fourth semiconductor switch 3 or 4 can be reliably turned off in response to this.
It is possible to prevent the semiconductor switch 1 and the third semiconductor switch 3, and the second semiconductor switch 2 and the fourth semiconductor switch 4 from being simultaneously conducted. Moreover, by driving one of the first semiconductor switch 1 and the second semiconductor switch 2, the other third
Since the semiconductor switch 3 and the fourth semiconductor switch 4 can be turned on and off, only the first semiconductor switch 1 and the second semiconductor switch 2 need to be controlled so as to be alternately conducted, and the control circuit of the inverter circuit is very simple. In addition, since the first, second, third and fourth semiconductor switches 1, 2, 3 and 4 are each composed of NPN transistors, even if high breakdown voltage transistors are used, PNP
Since it is cheaper than the case of using a transistor, the entire inverter circuit can be provided easily and at low cost. Moreover, since the other third semiconductor switch 3 and the fourth semiconductor switch 4 can be turned on and off by driving the first semiconductor switch 1 and the second semiconductor switch 2 as described above, the semiconductor switches 1, 3 or the semiconductor switches can be switched from the power source. There is no fear that a short circuit current will flow through 2,4 and the failure of the semiconductor switches 1,2,3,4 due to the short circuit current can be prevented, and its practical effect is remarkable.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す回路図、第2図は同動
作説明用の回路図、第3図は他の実施例を示す回路図、
第4図乃至第7図は従来例を示す回路図である。 (1)(2)(3)(4)……半導体スイツチ、(5)
……直流電源、(18)(19)……直流電源、(22)(2
3)……ダイオード。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram for explaining the same operation, FIG. 3 is a circuit diagram showing another embodiment,
4 to 7 are circuit diagrams showing a conventional example. (1) (2) (3) (4) …… Semiconductor switch, (5)
...... DC power supply, (18) (19) ...... DC power supply, (22) (2
3) …… Diode.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】直流電源(5)にブリッジ接続されたマイ
ナス側の第1及び第2半導体スイッチ(1)(2)とプ
ラス側の第3及び第4半導体スイッチ(3)(4)とを
備え、第1及び第4半導体スイッチ(1)(4)と第2
及び第3半導体スイッチ(2)(3)との交互導通によ
り、第1及び第3半導体スイッチ(1)(3)の接続点
と第2及び第4半導体スイッチ(2)(4)の接続点と
の間に、交流電圧を出力するようにしたブリッジインバ
ータ回路において、 前記第1、第2、第3及び第4半導体スイッチ(1)
(2)(3)(4)が、夫々NPNトランジスタで構成さ
れ、第3及び第4半導体スイッチ(3)(4)の各ベー
スに、ベース電流を供給する直流電源(18)(19)が抵
抗(20)(21)を介して夫々接続され、第1半導体スイ
ッチ(1)のオン時に第3半導体スイッチ(3)へのベ
ース電流を阻止するように前記直流電源(18)から第1
半導体スイッチ(1)へ電流を流すダイオード(22)
と、第2半導体スイッチ(2)のオン時に第4半導体ス
イッチ(4)へのベース電流を阻止するように前記直流
電源(19)から第2半導体スイッチ(2)へ電流を流す
ダイオード(23)とが、第3及び第4半導体スイッチ
(3)(4)のベース側と第1及び第2半導体スイッチ
(1)(2)との間に夫々接続され、第1半導体スイッ
チ(1)及び第2半導体スイッチ(2)の駆動によって
第3半導体スイッチ(3)及び第4半導体スイッチ
(4)をオンオフさせるように、第1半導体スイッチ
(1)及び第2半導体スイッチ(2)を交互導通させる
制御回路が設けられていることを特徴とするブリッジイ
ンバータ回路。
1. A negative-side first and second semiconductor switch (1) (2) and a positive-side third and fourth semiconductor switch (3) (4) bridge-connected to a DC power source (5). The first and fourth semiconductor switches (1) (4) and the second
And the connection points of the first and third semiconductor switches (1) and (3) and the connection points of the second and fourth semiconductor switches (2) and (4) by alternating conduction with the third and third semiconductor switches (2) and (3). A bridge inverter circuit configured to output an AC voltage between the first, second, third and fourth semiconductor switches (1)
(2), (3) and (4) are respectively composed of NPN transistors, and DC power supplies (18) and (19) for supplying a base current are provided to the bases of the third and fourth semiconductor switches (3) and (4), respectively. The DC power supply (18) is connected to the first semiconductor switch (1) via the resistors (20) (21) so as to block the base current to the third semiconductor switch (3) when the first semiconductor switch (1) is turned on.
Diode (22) that sends current to semiconductor switch (1)
And a diode (23) for flowing a current from the DC power supply (19) to the second semiconductor switch (2) so as to block a base current to the fourth semiconductor switch (4) when the second semiconductor switch (2) is turned on. Are connected between the base sides of the third and fourth semiconductor switches (3) and (4) and the first and second semiconductor switches (1) and (2), respectively. Control for alternately conducting the first semiconductor switch (1) and the second semiconductor switch (2) so that the third semiconductor switch (3) and the fourth semiconductor switch (4) are turned on and off by driving the second semiconductor switch (2). A bridge inverter circuit characterized in that a circuit is provided.
JP60025736A 1985-02-12 1985-02-12 Bridge inverter circuit Expired - Lifetime JPH078148B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60025736A JPH078148B2 (en) 1985-02-12 1985-02-12 Bridge inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60025736A JPH078148B2 (en) 1985-02-12 1985-02-12 Bridge inverter circuit

Publications (2)

Publication Number Publication Date
JPS61185077A JPS61185077A (en) 1986-08-18
JPH078148B2 true JPH078148B2 (en) 1995-01-30

Family

ID=12174100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60025736A Expired - Lifetime JPH078148B2 (en) 1985-02-12 1985-02-12 Bridge inverter circuit

Country Status (1)

Country Link
JP (1) JPH078148B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425499U (en) * 1990-06-21 1992-02-28

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571179A (en) * 1978-11-20 1980-05-29 Sanken Electric Co Ltd Transistor inverter

Also Published As

Publication number Publication date
JPS61185077A (en) 1986-08-18

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