JPH0782067B2 - Signal test circuit - Google Patents

Description

The present invention relates to a signal test circuit for failure diagnosis of a logic circuit or the like of an information processing device.

[Prior Art] Conventionally, in a failure diagnosis test of a logic circuit, a simulation is performed in advance on a large computer, and a test pattern necessary for the test is generated. This test pattern generation method includes a method of manually creating a pattern and a method of automatically creating a pattern called an automatic test generation (hereinafter referred to as ATG). This test pattern is created in order to find a failure in a circuit under test such as a gate array or a package, and is processed in advance by a large computer. Such a simulation is generally called a failure simulation, and is automatically processed. Since ATG requires almost no human labor, it is a powerful means for generating test patterns. This conventional technique is described in the paper "Fault diagnosis of logic devices" in the magazine "Information Processing Society of Japan" VOL25, No. 10 (October 1984).

[Problems to be solved by the invention]

The conventional ATG described above is a simulation for detecting a failure and has an algorithm for automatically performing it. This algorithm predefines a fault in each circuit, and in order to find the fault, it follows the fan-in side to find out what kind of pattern to put in the input terminal, and outputs at that time. Follow the fan-out side to get a pattern. At this time, if the clock is simply connected to the input terminal even in the case where only the combination circuit such as the gate is used, or in the sequential circuit where the flip-flop exists, the test pattern is easily created by the ATG to detect the failure. Although the rate is high, if the clock of the flip-flop is made of a logic circuit, the simulation of the ATG becomes a problem.

In ATG, the clock specification can be set to the input terminal, but the clock created by the logic circuit cannot be specified.Therefore, between the signal itself entering the clock of the flip-flop and the other input signal of the flip-flop. Racing occurs, which is an unstable signal condition. Therefore, the value in the simulation may be different from the value in the actual circuit, and the created pattern becomes defective data. Also, even if you can specify the clock,
In order to make the clock signal reach the clock of the flip-flop, it is necessary to fix it so as not to affect other signals, which has a drawback that the failure detection rate is significantly lowered.

An object of the present invention is to provide a signal test circuit that eliminates such drawbacks, prevents the occurrence of racing, and improves the failure detection rate.

[Means for solving problems]

According to the configuration of the present invention, in the signal test circuit configured so that the output of the logic circuit is input to the clock input terminal of the circuit under test including the next-stage flip-flop, the test input for inputting the test clock signal is used. A terminal, a switching circuit that directly switches the output signal of the logic circuit by the clock from the test input terminal and supplies the output to the circuit under test, and a test in which the output of the logic circuit is branched at the input terminal side of the switching circuit. And an output terminal for use.

〔Example〕

 The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, the input from the test clock terminal 1 and the logic circuit 4 are
Is used as the input of the clock switching circuit 2, and the output of the clock switching circuit 2 is connected to the clock input terminal of the flip-flop 5 which is the circuit under test. Also,
The test observation terminal 3 is connected by branching the signal output from the logic circuit 4 on the way.

As shown in this figure, a clock switching circuit 2 and a test clock terminal 1 are provided, and a pulse signal is designated by the ATG to be input from the test clock terminal 1. In the ATG, when the clock signal is output as a pulse signal, other data signals are not changed at the same time, so that the output from the logic circuit 4 is constant, so that racing does not occur.

The clock switching circuit 2 is shown in FIG.
Three types of circuits, (b) and (c), are possible. It is necessary to prevent the clock of the flip-flop from operating by mistake because the signal from the logic circuit 4 constantly changes in the state where the pulse signal as the clock is not input to the test clock terminal 1 during the test, that is, in the normal state. There is. Therefore, it is necessary to combine the clock phases of the test clock terminal 1 as shown in FIGS. 2 (a), (b) and (c).

In FIG. 2A, an AND gate 2 is used as a clock switching circuit.
This is the case when 1 is used and a positive phase clock is input. This is because the test clock terminal 1 is normally zero, so that the signal of the logic circuit 4 is suppressed. In order for the clock from the test clock terminal 1 to be input to the flip-flop 5 as a clock, the output of the logic circuit 4 must be "1", but this operation is automatically performed by the ATG algorithm.

In FIG. 2B, an OR gate is used as the clock switching circuit 2.
22 is used and the clock of the negative phase is input. Normally, the test clock terminal 1 is "1", so that the change in the output of the logic circuit 4 is not supplied to the flip-flop 5. On the other hand, the clock from the test clock terminal 1 is automatically simulated by the ATG algorithm so that it is input when the output of the logic circuit 4 is "0".

FIG. 2C shows the case where the selector 23 is used as the clock switching circuit 2. In this case, a select signal is required, and this signal needs to be made to instruct the test clock terminal 1 side at the time of testing, but in this case, the clock phase may be positive or negative.

On the other hand, the test observation terminal 3 is provided in order to avoid a decrease in the failure detection rate because the route for finding a failure in the logic circuit 4 is blocked by the inclusion of the clock switching circuit 2. The provision of this terminal 3 greatly contributes to the improvement of the failure detection rate.

Although the above description has dealt with the measures during the test, it is necessary that the signal operates normally in the device except during the test.
For this purpose, the clock input terminal 1 is created so as to be clamped, and the clamp value is "1" in FIG. 2 (a).
In FIG. 2 (b), it is set to “0”, and in FIG. 2 (c),
It can be either "1" or "0", but in this case the select signal must be fixed.

〔The invention's effect〕

As described above, in the present invention, the clock of the test circuit such as the flip-flop is provided with the clock switching circuit, and the clock from the test clock terminal is accurately input to the test circuit to input the data through this circuit. There is an effect that the ATG can be operated without causing the racing with and the detection rate can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 (a), (b) and (c) are circuit diagrams of the concrete example of FIG. In the figure, 1 ... Test clock terminal, 2 ... Clock switching circuit, 3 ... Test observation terminal, 4 ... Logic circuit, 5 ...
Flip-flops, 21 ... AND gates, 22 ... OR gates, 23 ... selectors.

Claims (1)

[Claims] 1. A test input terminal for inputting a test clock signal in a signal test circuit configured so that an output of a logic circuit is input to a clock input terminal of a circuit under test including a flip-flop in the next stage. And a switching circuit for directly switching the output signal of the logic circuit to the circuit under test by a clock from the test input terminal, and a test circuit for branching the output of the logic circuit at the input terminal side of the switching circuit. A signal test circuit having an output terminal.