JPH0782434B2 - Micro program controller - Google Patents

Description

The present invention relates to a microprogram controller, and more particularly to control for waiting for the start of execution of a microprogram.

<Prior Art> Control using a microprogram control device has an application in which a plurality of microprograms in which control contents are defined are prepared in advance and a certain microprogram is executed as necessary. In such an application, when the microprogram whose execution has started completes a series of processing, the microprogram controller enters a state of waiting for execution start designation of the next microprogram.

When a micro program control device is used for the instruction execution unit of the information processing device, different micro programs are prepared corresponding to each instruction (hereinafter, referred to as macro instruction) of the information processing device, and the macro program is prepared. An instruction decode unit that decodes instructions specifies the microprogram and, at the end of decoding the microprogram, specifies execution of the microprogram.

When the activated microprogram finishes the processing specified as the macro instruction, the next microprogram and the execution start designation are waited for. At this time, if the instruction decoding unit has finished decoding the next macro instruction, the execution of the corresponding microprogram can be started immediately.

By repeating such a sequence, the sequence of macro instructions can be executed one after another.

FIG. 4 is a block diagram showing the configuration of a conventional micro program controller used in the instruction execution unit.

Microinstruction address register (hereinafter called MAR) 4
00 is a register for storing the address of the next M-bit microinstruction to be executed. When the hold signal HOLD is 0,
The content obtained by adding 1 to the current MAR value is loaded into the MAR 400 by an m-bit incrementer (hereinafter referred to as INC) 401. This operation is performed when micro instructions are executed sequentially. When the load signal LDSTART is 1, the MAR 400 is loaded with the m-bit execution start address (start address) of the next microprogram. Hold signal HOLD is 1 and load signal LDSTART is 0
During this period, the contents of MAR400 remain unchanged.

Microprogram memory (hereinafter referred to as MMEM) 402
Is a storage device that stores a sequence of n-bit wide microinstructions that form a plurality of microprograms, and outputs microinstructions corresponding to the addresses specified by the contents of MAR400. Micro instruction register (hereinafter referred to as MDR) 403
Is an n-bit latch that holds the microinstruction output to the MMEM402 while the holding input STB is 1.

The 2-input AND gates 410, 411, 412, 413 ... Disable the output of the MDR 403 when the inhibition signal INHIBIT is 1. Two-input AND gates 411, 412, 413 outputs ₀ 1,
₀ 2, ₀ 3 ... Are signals for controlling each part of the instruction execution unit--micro-order. The output END of the 2-input AND gate 410 is a micro order indicating the end of execution of the micro program.

Micro program sequencer (hereinafter referred to as MSEQ)
Reference numeral 404 denotes a micro order ENDM indicating the end of execution of the micro program, a status signal V indicating the validity of the execution start address (start address), and a load signal LDSTART and a hold signal HOLD for controlling the micro program controller. This is the circuit that generates the inhibit signal INHIBIT.
Status signals ENDM and BSY indicating the status of 04 are generated at the same time.
Here, the status signal ENDM indicates the execution start timing of the microprogram, and is equivalent to the load signal LDSTART. The status signal BSY indicates that MSEQ404 is waiting for the valid status of the execution start address (start address).

The microinstruction used in this conventional example is composed of n bits as shown in FIG. Further, it is divided into a plurality of bit strings (hereinafter referred to as fields) according to the control target. In FIG. 5, an OPR field related to control of operations, a BRANCH field related to branch of a micro program, an E field related to end of a micro program (corresponding to micro order END), and a CONTROL field related to other control including transfer are shown. Will be divided.

In order to perform many controls at the same time for the purpose of high-speed execution, each field is designed so that 1 bit means 1 bit. Therefore, the bit width n of the micro instruction may exceed 100 in some cases.

FIG. 6 is a diagram showing a basic operation timing of the conventional micro program control device. Load signal LD ----
Is a signal for storing the execution start address (new address) of a new microprogram in MAR400. Sixth
In the figure, at the timing of cycle 1, the load signal LD-
When "-" occurs, the value N of the execution start address (new address) is loaded into the MAR 400 at the timing of cycle 2.

MMEM402 is latched by MDR403 in cycle 3 because there is a large delay from the address N being designated until the corresponding data n is output.

That is, when compared at the same timing, the storage address of the microinstruction stored in MAR400 is MMEM402.
Alternatively, it precedes the microinstruction output by the MDR 403 by one cycle. Such control in consideration of the deviation between the stored address of the micro instruction and the stored micro instruction is often called pipeline control of the micro instruction.

Next, the operation of the conventional micro program controller will be described with reference to FIG.

FIG. 7 shows the timing when a plurality of microprograms are sequentially executed in this conventional example.

When the micro instruction m including the micro order END is executed, the micro order END is output. At this time, the execution start address (start address) is already valid and has X. Further, the state signal V being 1 indicates that the execution start address (start address) is valid.

In this state, the load signal LDSTART is immediately issued, and the MAR 400 is loaded with X one clock after the load signal LDSTART. At this timing, the microinstruction m + 1 next to the microinstruction m including the microorder END is executed by the pipeline control of the microinstruction.

When one clock further elapses, the load signal LDSTART and the hold signal HOLD are both 0, so the MAR 400 is loaded with the value X + 1 incremented by 1 by the INC 401.
At this timing, the first microinstruction x of the new microprogram that is starting to be stored from the address X
Is executed.

Thereafter, the execution of the micro-instructions proceeds in sequence, and when the micro-instruction x + n including the micro-order END is executed, the micro-order END is output again. At this time, the execution start address (start address) is invalid and X is still held. Further, the state signal V being 0 indicates that the execution start address (start address) is invalid. MSEQ404 sets the status signal BST to 1 to indicate that the execution start address (start address) is waiting for the validity.

Hold signal HOLD to hold the microinstruction address and microinstruction being output at the timing when MAR400 outputs X + n + 2 and MDR403 for one clock period.
Is output. The hold signal HOLD remains 1 until the status signal BSY returns to 0.

The output of MMEM402 or MDR403 remains held, but the microinstruction X + n + 1 output to MDR403
Has only to be executed once, so the inhibit signal INHIBIT
Is output.

The inhibit signal INHIBIT is the state signal BSY delayed by two clocks.

When the inhibit signal INHIBIT becomes 1, 2-input AND gates 410, 4
Micro-order EN that is the output of 11, 412, 413 ...
D, ₀ 1, ₀ 2, ₀ 3, ... Are all 0.

When the status signal V becomes 1 in the waiting state described above, the suspended load signal LDSTART is output. The start address Y of the new microprogram is 1 clock later
Micro instruction y, y + while being loaded into MAR400
1, ... are sequentially executed. At this time, the status signal BSY returns to 0, the hold signal HOLD also returns to 0, and the inhibit signal INHIBIT returns to 0 after 2 clocks.

As described above, in the conventional microprogram control device, the microinstruction executed immediately before is retained and the microinstruction is invalidated by the prohibition signal until the microprogram specification to be newly executed is confirmed. It prohibited the execution of illegal micro-instructions.

As described above, if a microinstruction with a large bit width is adopted to obtain high-speed performance, a 2-input AND gate 410, 411, 4 that prohibits the bit width and microinstruction of MDR403 is adopted.
The number of 12,413, ... also increases accordingly. That is, the hardware required is in proportion to the bit width of the microinstruction.

<Problems to be Solved by the Invention> As described above, in the conventional microprogram control device, in order to wait for the designation for starting the execution of a new microprogram, hardware proportional to the bit width of the microinstruction is used. Had the drawback of requiring.

The present invention seeks to overcome the above drawbacks.

<Means for Solving Problems> At the end of execution of a microprogram, in a microprogram controller that externally supplies an execution start address of the next microprogram to be executed, the start of execution of the microprogram is in a waiting state. A read-only storage means for holding a microprogram containing an invalid microinstruction for the purpose of at least consuming only time, and a means for addressing the invalid microinstruction stored in the storage means. When the detection means detects that the start of execution of the microprogram is waiting, the invalid microprogram stored in the storage means by the address means instead of the execution start address of the microprogram. Address the instruction and invalid within that address It is characterized by executing instructions.

<Operation> In contrast to the above-described conventional microprogram control device, the present invention waits for the specification for starting the execution of a new microprogram, which is not proportional to the bit width of the microinstruction to be used, and with minimum hardware. It has an original content that it can be controlled for.

That is, in the microprogram control device having the above configuration, when the execution start address of the next microprogram to be executed at the end of execution of the microprogram is externally supplied, it is detected that the start of execution of the microprogram is in a waiting state. Address invalid microinstructions stored in the means for storing invalid microinstructions.

<Embodiment> Next, the configuration and operation of an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a drawing showing the configuration of the first embodiment of the present invention.

The MAR100 loads the m-bit constant M when the load signal LDEND is 1 and holds the hold signal HOLD to the MAR400 used in the conventional microprogram controller.
Is 1, the load signal LDSTART is 0, and the load signal LDEND is 0, the contents are the same except that the contents of the MAR 400 do not change.

In the area corresponding to the address M of the MROM 402, a no-operation (hereinafter referred to as nop) instruction that is meaningless to the microprogram controller is stored.

Further, the n-bit output of the MROM 402 directly corresponds to the micro-order END, ₀ 1, ₀ 2, ₀ 3, ...

MSEQ101 inputs micro order END and status signal V,
A circuit that generates load signals LDSTART and LDEND, hold signal HOLD, and inhibit signal INHIBIT, and at the same time status signal EN
D and BSY are generated.

Next, the operation of this embodiment will be described with reference to FIG. FIG. 3 is a diagram showing the timing of the operation in this embodiment.

Microinstruction x + n including micro-order END is MMEM402
, The state signal V is 0, that is, the execution start address (start address) of the new microprogram is invalid, so the state signal BSY becomes 1.

At this time, the load signal LDEND is issued, and one clock later, the constant M is loaded into the MAR100.

At this timing, the next microinstruction x + n + 1 after the microinstruction including the microorder END is 1 clock period MM.
Output to EM402.

When one more clock elapses, the micro instruction address M
The contents of MMEM 402 corresponding to, that is, the nop instruction is executed.

After that, since the hold signal HOLD becomes 1 until the state signal V becomes 0, the contents of MAR100 are held in M and MMEM
The 402 output also holds the nop instruction.

At the operation timing of the present invention, the state signal V is 1
The case where the load signal LDSTART is generated is equivalent to the operation timing in the conventional micro program control device.

As described above, in the present embodiment, unnecessary microinstruction execution can be avoided without prohibiting execution of microinstruction during the period of waiting for the start of execution of a new microprogram.

In this embodiment, it is assumed that the nop instruction is stored as the data corresponding to the address M in the MMEM402, but the data equivalent to the nop instruction is output to the address not corresponding to the MMEM402. By defining the code of the micro instruction, the area for storing the nop instruction can be omitted, and it can be realized with less hardware.

Next, a second embodiment of the present invention will be described. FIG. 2 shows a second embodiment of the present invention, which is characterized in that it has two systems of inputs as the MAR200 in the first embodiment, like the MAR400 in the conventional microprogram controller. .

The MAR 200 loads the output of the m-bit multiplexer (hereinafter referred to as MPX) 201 when the output of the 2-input OR gate 210 is 1.

The 2-input OR gate 210 has load signals LDSTART and LDEN.
D is connected.

The MPX201 outputs the execution start address (start address) of the microprogram when the load signal LDEND is 0, and outputs the address M where the nop instruction is stored in the MMEM402 when the load signal LDEND is 1.

In this embodiment, the structure of the MAR200 can be simpler than that of the first embodiment of the present invention, and the migration from the conventional microprogram controller can be easily performed. .

<Effects of the Invention> As described above, by using the present invention, it is possible to omit the microinstruction holding mechanism and the microinstruction invalidating circuit for the control of waiting for the start of the execution of the microprogram. It is possible to provide a micro program controller that can be realized by hardware.

Also, when a microinstruction with a larger bit width is adopted for high-speed execution of a microprogram, the bit width of the microinstruction address becomes relatively small,
The effect will be greater.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention, and FIG. 3 is a timing showing the operation timing of the first embodiment. FIG. 4 is a block diagram showing the structure of a conventional micro program control device, FIG. 5 is a block diagram showing an example of the format of a micro instruction, and FIG. 6 is a basic operation timing of the micro program control device. Timing chart, FIG. 7 is a timing chart showing the operation timing of the conventional microprogram controller. 100, 200, 400 ... Microinstruction address register, 101, 404 ... Microprogram sequencer, 201 ... Multiplexer, 210 ... 2-input OR gate, 401 ... Incrementer, 402 ... Microprogram memory, 403: Micro instruction register, 410, 411, 412, 413: 2-input AND gate, 420: Inverter.

Claims (1)

[Claims] 1. A microprogram controller for externally supplying an execution start address of a microprogram to be executed at the end of execution of the microprogram,
A means for detecting that the start of execution of the microprogram is in a waiting state, a read-only storage means for holding the microprogram containing an invalid microinstruction for the purpose of at least consuming only time, and a storage means stored in the storage means Means for addressing an invalid microinstruction, and when the detecting means detects that the start of execution of the microprogram is in a waiting state, the address means replaces the execution start address of the microprogram by the address means. A microprogram control device, which addresses an invalid microinstruction stored in the storage means and executes an invalid instruction within the address.