JPH0782743B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor recording device, and in particular, while storing sent data, the stored data is stored on a first-come-first-served basis in response to a request for output. FI to read
The present invention relates to a semiconductor recording device used as an FO memory or the like.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional example of a FIFO memory.
In the figure, 1 is a memory cell array in which a plurality of memory cells are arranged in a matrix of n bits × k rows, and 2 is a ring pointer which serves as a selection means for sequentially selecting each row (n bits) from the memory cell array 1. is there. And
This ring pointer 2 n bits memory cell selected by the input input data DI ₁ -DI _n of n bits via the input driver 3, or the data stored in the memory cells of the selected n bits , Output data DO _{1 to} DO _n
Is output via the output driver 4. In this operation, read selection is performed sequentially from the memory cell in which data is stored earlier. Reference numeral 5 is a control circuit for controlling the input driver 3 and the output driver 4.

FIG. 5 is a circuit diagram showing the configuration of the ring pointer 2 described above. In the ring pointer 2, the flip-flop 6 with the first reset terminal is used as the first-stage flip-flop, and the second reset is provided in the subsequent stage. The terminal-equipped flip-flop 7 is configured by k-stage master-slave flip-flops in which (k-1) stages are cascade-connected. Each of the above flip-flops 6 and 7 has a data input terminal 8, a master data output terminal 9, a slave data output terminal 10, a clock terminal 11, and a reset terminal 12. The slave data output terminal 10 of each flip-flop 6, 7 is connected to the data input terminal 8 of the next-stage flip-flop 7, and the slave data output terminal 10 of the k-th flip-flop 7 is connected to the first Flip-flop 6 of the stage
The data input terminal 8 is connected to form a ring-shaped connection. Also, each flip-flop
The clock terminals 11 of 6 and 7 and the reset terminals 12 are commonly connected to each other. Furthermore, it is connected to address lines AD ₁ to AD _k each of the master data output terminal 9 of the flip-flops 6, 7, the address lines AD ₁
..- AD _k are respectively connected to the memory cells forming each row of the memory cell array 1 of FIG.

FIG. 6 is a circuit diagram of the first flip-flop 6 with a reset terminal which forms the first stage of the ring pointer 2 and includes NMOS transmission gates 13 and 14, PMOS transmission gates 15 and 16 and four inverters 17 , 18,1
It consists of 9,20, NOR gate 21 and NAND gate 22. Then, when the reset signal ▲ ▼ input to the reset terminal 12 becomes the “L” level, the master data output terminal 9 is supplied to the master data output terminal 9 regardless of whether the clock signal φ supplied to the clock terminal 11 is the “H” level or the “L” level. It outputs an "H" level signal as master data output DO _M. On the other hand, when the reset signal ▲ ▼ becomes "H" level, it operates as a normal master-slave flip-flop.
That is, in the operation as the master-slave flip-flop, the clock signal φ input to the clock terminal 11 is
Rises, the data DI input to the data input terminal 8 is output to the master data output terminal 9 as the master data output DO _M , while when the clock signal φ falls, the master data output DO _M is latched in the master stage. The master data output DO _M to the slave stage.
Are transmitted and output as slave data output DO _S from the slave data output terminal 10, and the next stage flip-flop 7 is brought into a state in which the slave data output DO _S can be taken in at the next rising edge of the clock signal φ.

FIG. 7 shows the second stage to the k-th stage of the ring pointer 2 described above.
Second stage flip-flop with reset terminal 7
It is a circuit diagram of an NMOS transmission gate 23,2
4, PMOS transmission gates 25, 26, three inverters 27, 28, 29 and NAND gates 30, 31.
Then, the reset signal input to the reset terminal 12
When ▼ becomes "L" level, regardless of whether the clock signal φ applied to the clock terminal 11 is "H" level or "L" level, the master data output terminal 9 and the slave data output terminal 10 respectively have "L" level. The signal of is output. On the other hand, when the reset signal ▲ ▼ becomes "H" level, it operates as a normal master-slave flip-flop. That is, in the operation as the master-slave flip-flop, when the clock signal φ input to the clock terminal 11 rises, the data DI input to the data input terminal 8 is output to the master data output terminal 9 as the master data output DO _M. to the other hand, when the clock signal φ falls, with latches the master data output DO _M in the master stage, the output from the slave data output terminal 10 and transfers the master data output DO _M to the slave stage as slave data output DO _S Then, the flip-flop of the next stage is brought into a state in which the slave data output DO _S can be taken in at the next rise of the clock signal φ.

The ring pointer 2 which is the selecting means in the conventional FIFO memory is configured as described above, and its operation is as shown in the timing chart of FIG.

That is, first, when the reset signal ▲ ▼ input to the commonly connected reset terminals 12 of the flip-flops 6 and 7 becomes “L” level, the first-stage flip-flop 6
Only the master data output terminal 9 of the master data DO _M
As a result, a signal of "H" level is output, and the address line AD ₁ becomes "H" level. On the other hand, the master data output terminal 9 of the other flip-flop 7 outputs a signal of “L” level as the master data DO _M , and the address lines AD _{2 to} AD _k are set to “L” level.

Next, when the reset signal ▲ ▼ becomes "H" level, only the master data output terminal 9 of the second-stage flip-flop 7 serves as the master data output DO _{M due to} the rise of the clock signal φ input to the clock terminal 11. The "H" level signal is output and the address line AD ₂ becomes "H" level. At this time, all the master data outputs DO _M output from the other flip-flops 6, 7 become "L" level. Then, by the next fall of the clock signal φ,
Master data output DO _{M of} the second stage flip-flop
Is latched to the "H" level.

Further, at the next rise of the clock signal φ, only the master data output terminal 9 of the third-stage flip-flop 7 outputs a signal of “H” level, and only the address line AD ₃ becomes “H” level.

By the above operation, the address lines AD ₁ , AD ₂ , ..., AD _k are sequentially set to the “H” level one by one in synchronization with the clock signal φ, and the k-th clock signal φ falls to the k-th stage. Flip-flop master data output DO _M is "H"
Latched to level. Then, at the next fall of the clock signal φ, the master data output DO _M of the first-stage flip-flop 1 becomes "H" level.

As described above, unless the reset signal ▲ ▼ is set to the “L” level, the address lines AD _{1 to} AD _k are selected in a sequential and cyclic manner in synchronization with the clock signal φ, as shown in FIG. Each row of the memory cell array 1 shown in FIG. 4 is sequentially selected.

[Problems to be solved by the invention]

In the conventional FIFO memory, since the ring pointer 2 which is the selection means is configured as described above, even if a defective bit is found in a part of the memory cell at the inspection stage after the memory is manufactured, the defective bit is avoided. Since there is no way to select it as a whole, there is a problem that there is no redundancy because the whole must be treated as a defect. And such a problem is
The problem is not limited to the FIFO memory and is common to other semiconductor memory devices that sequentially select rows or columns of the memory cell array to input / output data.

The present invention has been made in order to solve such a problem, and even if a defective bit occurs in a part of the memory cell, there is redundancy that the memory cell can be selected while avoiding the defective bit. An object is to obtain a semiconductor recording device.

[Means for solving problems]

The semiconductor recording device according to the present invention has a memory cell array in which a plurality of memory cells are arranged in a matrix and a function of sequentially selecting the memory cells of the memory cell array, and by receiving an irreversible process from the outside. Selection means capable of sequentially selecting memory cells while avoiding some memory cells, input means for writing information to the memory cells selected by the selection means, and selection means selected by the selection means. And an output means for reading the information stored in the memory cell.

[Action]

According to the present invention, when a defective bit occurs in a part of the memory cells of the memory cell array, the selecting means performs an irreversible process from the outside, so that the selecting means has the defective bit. Selection is performed while avoiding the memory cells, and data input / output is normally performed without any trouble due to defective bits.

〔Example〕

FIG. 1 is a circuit diagram showing the overall structure of a ring pointer 2 as a selecting means used in a FIFO memory which is an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a block diagram of the FIFO memory. Ring pointer 2 shown in FIG.
Is a master-slave type first flip-flop with reset terminal 6 described in the conventional example, and a laser trimmer terminal.
A master blade type flip-flop 33 having a selector function having 32, and a switch circuit 35 also having a laser trimmer terminal 34, the flip-flop 6 having a reset terminal described above as a first stage flip-flop, and the selector described above at the subsequent stage. The flip-flops 33 with a function are cascade-connected (k-1) stages, and the flip-flop 33 with a selector function is cascade-connected to the subsequent stage through the switch circuit 35. Similarly to the flip-flop 6 with a reset terminal, the flip-flop 33 with a selector function also has a data input terminal 3
6, master data output terminal 9, slave data output terminal 3
The slave data output terminal 10 of the first-stage flip-flop 6 has a clock terminal 11 and a reset terminal 12, and the slave-data output terminal 10 of the next-stage flip-flop 33 receives the slave data of each subsequent flip-flop 33. The output terminal 10 is connected to the data input terminal 36 of the flip-flop 33 at the next stage, and the slave data output terminal 37 of the flip-flop 33 at the kth stage is the input terminal of the switch circuit 35.
It is connected to the I _N.

On the other hand, the output terminal O _N of the switching circuit 35 is connected to the data input terminal 36 of the (k + 1) th stage flip-flop 33,
In this transition, the flip-flops 33 of each stage are sequentially connected to the (k + m) th stage by the above connection procedure, the slave data output terminal 37 of the flip-flop 33 of the (k + m) th stage is folded back and the switch circuit 35 is folded back. is connected to the input terminal I _R, more folded output terminal O _R of the switching circuit 35 is connected to the data input terminal 8 of the first-stage flip-flop 6 as a whole (k + m) flip-flop 6, 33 of the stage switching circuit 35 It is configured to be connected in a ring shape via.

The clock terminals 11 and the reset terminals 12 of the flip-flops 6 and 33 are commonly connected. Further, address lines AD _{1 to} AD _{k + m} are connected to the master data output terminals 9 of the flip-flops 6 and 33, respectively. The flip-flop 33 and the laser trimmer terminals 32 and 34 of the switch circuit 35 are formed of polysilicon fuses that can be disconnected by laser irradiation.

The switch circuit 35 has an input terminal I _N · folded output terminal O NMOS transmission gate 38 connecting the _R, input terminals I _N · output terminal O connecting the _N PMOS transmission gates 39 and folding the input terminal I _R · folded output terminal O _It has a PMOS transmission gate 40 connecting between _R , and each gate electrode of these transmission gates is connected to a common node N, and this node N is pulled up to a power supply voltage V _cc via a laser trimmer terminal 34. Therefore, in the normally laser trimming terminal 34 is not disconnected state, NMOS transmission gate 38 is turned on, PMOS transmission gate 39 and 40 is turned off and becomes the input terminal I _N · folded-output terminal O _R becomes electrically conductive state The slave data output terminal 37 of the k-th stage flip-flop 33 is connected to the data input terminal 8 of the first-stage flip-flop 6 and operates as a k-stage ring pointer.

On the other hand, when the laser trimmer terminal 34 of the switch circuit 35 is disconnected, the gate electrodes of the transmission gates 38.39 and 40 are pulled down to GND, the NMOS transmission gate 38 is turned off, and the PMOS transmission gate is turned off.
39 and 40 is used as the input terminal I _N · output terminal O _N and between the folded input terminal I _R · folding the output terminal O _R between the electrically conductive state respectively turned off, the slave data of the k-th stage flip-flop 33 The output terminal 37 is the data input terminal 36 of the (k + 1) th stage flip-flop 33, and the slave data output terminal 37 of the (k + m) th stage flip-flop 33 is the data input terminal 8 of the first stage flip-flop 6. The ring pointers 2 connected to each other form a ring pointer of (k + m) stages as a whole. However, as will be described later, not all (k + m) stages are used simultaneously. The m-stage flip-flop 33 and the switch circuit 35 form an alternative selecting means for using / selecting a redundant cell instead of a defective cell (details will be described later).

FIG. 3 is a circuit diagram showing the specific configuration of the l-th stage of the flip-flops with selector function 33 that composes the ring pointer 2 shown in FIG. Slave type second flip-flop with reset terminal 7, laser trimmer terminal 32, PMO
Latch circuit 44 including S transmission gate 41, NMOS transmission gate 42, pull-up resistor 43, etc.
And a gate circuit 49 composed of NMOS transmission gates 45, 46, 47, 48. Then, in the latch circuit 44, when the power supply voltage V _cc is applied in the normal state where the laser trimmer terminal 32 is not disconnected, the node S
_l (select signal node) is pulled up to “H” level, which turns off the PMOS transmission sensor 41,
NMOS transmission 42 turned on and node Is latched in a state in which it becomes the "L" level. On the other hand, when the laser trimmer terminal 32 is disconnected, the node S _l is pulled down to "L" level, thereby PMOS transmission gate 41 is turned on, NMOS transmission gate 42
Turned off the node Is latched in a state in which it becomes "H" level.

In the gate circuit 49, the node S _l of the latch circuit 44 is at the “H” level, When the laser trimmer terminal 32 is not disconnected, which becomes "L" level, the NMOS transmission gates 45 and 47 are turned on, the NMOS transmission gate 46 is turned off, and the input terminal and the output terminal of the flip-flop 7 are the data input terminal 36 and the slave. Directly connected to the data output terminal 37, the entire flip-flop 33 operates as a normal master-slave flip-flop. On the other hand, the node S _l of the latch circuit 44
Is at "L" level, node When the terminal 32 for the laser trimmer is disconnected at the "H" level, the NMOS transmission gates 45 and 47 are turned off, the NMOS transmission gate 46 is turned on, and the slave data of the flip-flop 33 at the previous stage ((l-1) stage) The output terminal 37 is skipped over the 1st stage to the next stage ((l + 1)
The flip-flop 33 is directly connected to the data input terminal 36, and at this time, the NMOS transmission gate 42 having a sufficiently small on-resistance is turned on so that the output of the master data output terminal 9 is at "H" level or "L". The row selection line AD ₁ is forcibly fixed to the “L” level regardless of the “L” level.

Further, in FIG. 2 showing the overall configuration of the FIFO memory in a block diagram, in the memory cell array 1, there are m rows corresponding to the respective row selection lines AD _{1 to} AD _{k + m} of the ring pointer 2 serving as selection means. N bits including redundant memory cell 1a x (k
The memory cells are arranged in a matrix of + m) rows, and the row selection lines AD _{1 to} AD _{k + m} are connected to the memory cells of the corresponding rows of the memory cell array 1, respectively. Input driver
3, the output driver 4, the control circuit 5, etc. are the same as in the conventional example.

Next, the operation of the FIFO memory of the above embodiment will be described.

In the first test after manufacturing, when it is determined that the memory cell is a good product without defective bits, the laser trimmer device does not perform disconnection processing of the laser trimmer terminals 32 and 34. Thus the ring pointer 2, the input terminal I _N · folded output terminal of the switch circuit 35 in FIG. 1
The O and _R are electrically connected to each other to operate as a k-stage ring pointer including the flip-flops 6 and 33 from the first stage to the k-th stage. That is, the reset signal ▲
When ▼ is input and the row selection line AD ₁ of the first stage is selected _first , and then the reset signal ▲ ▼ rises, the row selection lines AD ₂ , AD ₃ , ... AD _k , AD ₁ are synchronized in the order of the clock signal φ. The selection is performed sequentially and sequentially, and it operates as a FIFO memory of n bits × k rows as a whole. At this time, the m rows of redundant memory cells 1a are not used.

Next, in the first test after manufacturing, for example, when a defective bit is found in the l-th row of the memory cell array 1, first in the l-th stage flip-flop 33 of the ring pointer 2 for the memory cell in which the defective bit exists. The laser trimmer terminal 32 is irreversibly broken by an external laser trimmer device. As a result, in the l-th stage flip-flop 33, as described above, the NMOS transmission gate 46 of the gate circuit 49 in FIG. 3 is turned on, and the slave data output of the (l-1) -th stage flip-flop 33 is output. Since the terminal 37 jumps over the l-th stage flip-flop 33 and is connected to the data input terminal 36 of the (l + 1) -th stage flip-flop 33, at this time, the ring pointer 2 becomes a (k-1) -th stage ring pointer. It will work. That is, the row selection lines are selected as AD ₁ , AD ₂ , ..., A
Rows having defective bits, such as D _l-1 , AD _{l + 1} , AD _k , and AD ₁ , are avoided in sequence.

In this way, the function as a FIFO memory can be sufficiently achieved even in the usage mode, but here, by further performing the following processing, the row in which the defective bit exists is replaced with one row in the redundant memory 1a, and n bits are used. Used as × k rows of FIFO memory.

That is, in addition to the disconnection of the laser trimmer terminal 32 of the l-th stage flip-flop 33 described above, the laser trimmer terminal of the switch circuit 35 of the ring pointer 2 in FIG.
Similarly, 34 is irreversibly disconnected. As a result, the input terminal T _N and the output terminal O _N of the switch circuit 35 and the folded input terminal I _R and the folded output terminal O _R are electrically connected to each other, and m stages after the kth flip-flop 33. Minute flip-flop 33 is connected. Of the added m-stage flip-flops 33, the flip-flop 33 that replaces the l-th stage flip-flop 33.
In order to disable the other flip-flop 33 while leaving one, the laser trimmer terminal 32 of any (m−1) th flip-flop 33 among the (k + 1) th to (k + m) th stages has the same laser trimmer terminal 32. The device disconnects the wire. For example, when the laser trimmer terminal 32 of the (k + 1) th stage flip-flop 33 is left and the laser trimmer terminal 32 of the (k + 2) th to (k + m) th stage flip-flops 33 is disconnected, In the ring pointer 2 in this case, the row selection line AD ₁ is first selected by the input of the reset signal ▲ ▼, and then AD ₂ , AD ₃ , ..., A in synchronization with the clock signal φ after the reset signal ▲ ▼ has risen.
Row selection lines are sequentially selected in the order of D _l-1 , AD _{l + 1} , ..., AD _k , AD _{k + 1} , AD ₁ . Therefore, by performing such alternative selection, the entire memory cell operates as an n-bit × k-row FIFO memory. When M memory cells among the memory cells of n bits × k rows are defective,
The laser trimmer terminal 32 of the flip-flop 33 corresponding to them is disconnected, and (m) of the m flip-flops 33 corresponding to the memory cells of n bits × m rows is (m
-M) Laser trimmer terminal 32 of flip-flops 33
Should be disconnected. (The disconnection process of the laser trimmer terminal 34 in the switch circuit 35 is also performed in the same manner.) The function of the FIFO memory for reading data in the order in which the data is stored is the same as the conventional one.

In the above embodiment, an example in which the row pointer of the memory cell array 1 is selected by the ring pointer 2 having the flip-flop 33 with a selector function having the laser trimmer terminal 32 as a constituent element has been described, but the ring pointer 2 is not limited to this. The same operation can be performed when used for column selection.

Further, although the write and read operations are not described in the above embodiment, it is possible to perform write and read asynchronously by preparing two ring pointers 2 for write and read.

Further, in the above embodiment, as a means for changing the functions of the flip-flop 33 with a selector function and the switch circuit 35 by an irreversible process from the outside, a polysilicon fuse for disconnecting by laser irradiation (laser blow) to perform an irreversible program is used. Although the laser trimmer terminals 32 and 34 are used, an electric fuse that can be electrically disconnected can be used, or a polysilicon fuse that can be electrically cut off by laser annealing can be used.

〔The invention's effect〕

As described above, according to the present invention, as the selection means for sequentially selecting the memory cells of the memory cell array, one that can perform selection avoiding an arbitrary memory cell by an irreversible process from the outside is used. Even if a defective bit occurs in a part of the cells, it is possible to avoid the memory cell having the defective bit and select a semiconductor memory device having redundancy.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall structure of a ring pointer as a selection means used in a FIFO memory according to an embodiment of the present invention, and FIG. 2 is an overall block diagram of the FIFO memory.
FIG. 4 is a circuit diagram showing a concrete configuration of a flip-flop with selector function, FIG. 4 is a block diagram showing a conventional FIFO memory, FIG. 5 is a circuit diagram showing its ring pointer, and FIG. 6 is its ring pointer. FIG. 7 is a circuit diagram of a first flip-flop with a reset terminal, FIG. 7 is a circuit diagram of a second flip-flop with a reset terminal that constitutes the ring pointer, and FIG. 8 is a timing chart showing the operation of the ring pointer. . In the figure, 1 is a memory cell array, 2 is a ring pointer which is a selection means, 3 is an input driver, and 4 is an output driver. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A memory cell array having a plurality of memory cells arranged in a matrix, and a function of sequentially selecting the memory cells of the memory cell array, and a part of the memory by receiving an irreversible process from the outside. Selection means capable of sequentially selecting memory cells while avoiding cells, input means for writing information to the memory cells selected by the selection means, and memory cells selected by the selection means Output means for reading the stored information, and the selection means has one master-slave flip-flop with a reset terminal and a laser trimmer terminal, and whether or not each laser trimmer terminal is disconnected. Depending on whether the input signal is input to the master-slave flip-flop with the reset terminal Luke, the semiconductor memory device is a ring pointer that includes a plurality of flip-flops with selector function for selecting whether to output as not input to the master-slave flip-flop with a reset terminal. 2. The flip-flop with selector function outputs a signal of a first logic level when the flip-flop with reset terminal and the laser trimmer terminal are not disconnected, and when the laser trimmer terminal is disconnected. A latch circuit for outputting a second logic level complementary to the signal of the first logic level, and an output signal of the latch circuit for converting the input signal into a master-slave flip-flop with a reset terminal of the flip-flop with selector function. 2. A semiconductor memory device according to claim 1, further comprising a gate circuit for selecting whether to input to a master-slave flip-flop with a reset terminal and to output as it is without inputting to a master-slave flip-flop. 3. The memory cell array has a redundant memory cell, and the selection means receives an irreversible process from the outside to select the redundant memory cell as a substitute for a memory cell avoiding selection. The semiconductor memory device according to claim 1 or 2, further comprising an alternative selecting means to perform.