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JPH0783017B2 - Compound semiconductor microfabrication method - Google Patents
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JPH0783017B2 - Compound semiconductor microfabrication method - Google Patents

Compound semiconductor microfabrication method

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Publication number
JPH0783017B2
JPH0783017B2 JP2255093A JP2255093A JPH0783017B2 JP H0783017 B2 JPH0783017 B2 JP H0783017B2 JP 2255093 A JP2255093 A JP 2255093A JP 2255093 A JP2255093 A JP 2255093A JP H0783017 B2 JPH0783017 B2 JP H0783017B2
Authority
JP
Japan
Prior art keywords
gaas
electron beam
etching
compound semiconductor
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2255093A
Other languages
Japanese (ja)
Other versions
JPH06236862A (en
Inventor
喜正 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2255093A priority Critical patent/JPH0783017B2/en
Publication of JPH06236862A publication Critical patent/JPH06236862A/en
Publication of JPH0783017B2 publication Critical patent/JPH0783017B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子ビームを用いた化
合物半導体の微細加工方法に関し、さらに詳しくはナノ
メータスケールの精度で微細な加工をGaAs等の化合
物半導体に施す方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of finely processing a compound semiconductor using an electron beam, and more particularly to a method of finely processing a compound semiconductor such as GaAs with a precision of nanometer scale.

【0002】[0002]

【従来の技術】化合物半導体の微細加工技術は半導体プ
ロセス上重要である。特に最近のトピックとして電子ビ
ームを用いた微細加工が注目されている。この様な電子
ビームを用いたドライエッチングにはGaAs化合物半
導体上にInGaAs成長層をマスクとしてこれを電子
ビームでパターニングし、更に下地の化合物半導体材料
に転写する方法が第53回応用物理学会学術講演会予稿
集に掲載の河本等による技術論文“InGaAs薄膜マ
スクを用いたGaAsのEB励起エッチング”に提案さ
れている。
2. Description of the Related Art Microfabrication technology for compound semiconductors is important for semiconductor processes. In particular, microfabrication using electron beams has attracted attention as a recent topic. For such dry etching using an electron beam, a method of patterning the InGaAs growth layer on a GaAs compound semiconductor with an electron beam as a mask and then transferring it to the underlying compound semiconductor material is the 53rd Annual Meeting of the Japan Society of Applied Physics. It is proposed in the technical paper "EB excited etching of GaAs using InGaAs thin film mask" by Kawamoto et al.

【0003】図3は、この従来例の工程図である。図3
(a)に示すようにGaAs基板1上にGaAs半導体
層2を成長し、更にその上にInGaAs層33を成長
する。次に同図(b)に示すように電子ビーム4と塩素
ガス5を同時に照射しInGaAs層33をエッチング
する。その後同図(c)に示すように電子ビームを切
り、塩素ガス5だけで下地のGaAsをエッチングす
る。このときInGaAs層33のマスクは塩素ガス5
に対して耐性を持つ。従って以上のプロセスからGaA
sのパターニングが実現されている。
FIG. 3 is a process diagram of this conventional example. Figure 3
As shown in (a), a GaAs semiconductor layer 2 is grown on a GaAs substrate 1, and an InGaAs layer 33 is further grown thereon. Next, as shown in FIG. 6B, the InGaAs layer 33 is etched by simultaneously irradiating the electron beam 4 and the chlorine gas 5. After that, the electron beam is turned off and the underlying GaAs is etched only with the chlorine gas 5, as shown in FIG. At this time, the mask of the InGaAs layer 33 is chlorine gas 5
Resistant to. Therefore, from the above process, GaA
s patterning has been realized.

【0004】この様な電子ビームを用いた微細加工で
は、イオンに比べて1万倍以上も軽い電子を照射するか
ら従来のイオンを用いたドライエッチングの様なイオン
照射損傷がなく、損傷の少ない加工が可能である。
In such fine processing using an electron beam, electrons are irradiated 10,000 times as light as compared with ions, so that there is no damage due to ion irradiation unlike the conventional dry etching using ions. It can be processed.

【0005】[0005]

【発明が解決しようとする課題】InGaAs層をマス
クとして用いる従来技術では、InGaAs層がGaA
s基板に格子整合しない歪系であるから、混晶組成およ
び成長膜厚を精密に制御する必要がある。歪の度合いが
大きすぎるとInGaAs層にクラックが入りマスクと
して機能しなくなる事も起こる。
In the prior art using the InGaAs layer as a mask, the InGaAs layer is GaA.
Since it is a strain system that does not lattice match with the s substrate, it is necessary to precisely control the mixed crystal composition and the grown film thickness. If the degree of strain is too large, the InGaAs layer may crack and fail to function as a mask.

【0006】また、InGaAs層における成長膜内の
組成は均一でなく、表面近傍ほどInの組成が大きくな
り、いわゆるIn偏析が起きる事が知られている。その
ためマスク効果としての再現性の無いInGaAs層が
成長する事もありマスクの再現性および制御性を保持す
るのはなかなか困難であり、ひいては化合物半導体の微
細加工の再現性および制御性を保持するのは容易でなか
った。本発明の目的は、Inの表面偏析の無い、再現性
および制御性に優れた半導体マスクを形成し、このマス
クにより化合物半導体を微細に加工する方法を提供する
事にある。
Further, it is known that the composition in the growth film of the InGaAs layer is not uniform, and the In composition increases near the surface, and so-called In segregation occurs. Therefore, it may be difficult to maintain the reproducibility and controllability of the mask because an InGaAs layer that does not have reproducibility as a mask effect may grow, and thus the reproducibility and controllability of fine processing of compound semiconductors should be maintained. Was not easy. An object of the present invention is to provide a method for forming a semiconductor mask which is free from segregation of In and is excellent in reproducibility and controllability, and finely processing a compound semiconductor using this mask.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明による微細加工方法では、GaAs又はGa
As/AlGaAsのヘテロ構造若しくは量子井戸構造
の化合物半導体表面にInAsとGaAsの超格子構造
を積層する工程と、前記超格子構造にハロゲン原子を含
む反応性ガス中で電子ビームを照射して前記超格子構造
を部分的にエッチングする事によりパターンを形成する
固定と、このパターン形成工程により形成された超格子
構造をマクスとして前記GaAs又はGaAs/AlG
aAsのヘテロ構造若しくは量子井戸構造の化合物半導
体のエッチングをする工程とを有するものである。
In order to achieve the above object, in the fine processing method according to the present invention, GaAs or Ga is used.
A step of stacking a superlattice structure of InAs and GaAs on a compound semiconductor surface of an As / AlGaAs heterostructure or a quantum well structure, and irradiating the superlattice structure with an electron beam in a reactive gas containing a halogen atom Fixing to form a pattern by partially etching the lattice structure, and the GaAs or GaAs / AlG using the superlattice structure formed by this pattern forming process as a mask.
and a step of etching a compound semiconductor having a hetero structure or quantum well structure of aAs.

【0008】GaAs又はGaAs/AlGaAsのヘ
テロ構造若しくは量子井戸構造の化合物半導体のエッチ
ングは、ハロゲン原子を含む反応性ガスによるガスエッ
チングによって行ってもよいし、又はGaAs又はGa
As/AlGaAsのヘテロ構造若しくは量子井戸構造
の化合物半導体のエッチングはハロゲン原子を含む反応
性ガス中で電子ビームを照射して行う電子ビームアシス
トエッチングで行ってもよい。
The etching of a compound semiconductor of GaAs or a heterostructure of GaAs / AlGaAs or a quantum well structure may be carried out by gas etching using a reactive gas containing a halogen atom, or GaAs or Ga.
The compound semiconductor having a heterostructure or quantum well structure of As / AlGaAs may be etched by electron beam assisted etching performed by irradiating an electron beam in a reactive gas containing a halogen atom.

【0009】[0009]

【作用】本発明では、InAsとGaAsの超格子構造
をマスクとして用いる事でInGaAsマスクで問題と
なった表面偏析を回避し、制御性および再現性に優れた
電子ビームパターニングプロセスが実現できる。
In the present invention, by using the superlattice structure of InAs and GaAs as a mask, the surface segregation, which is a problem with the InGaAs mask, can be avoided and an electron beam patterning process excellent in controllability and reproducibility can be realized.

【0010】[0010]

【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図1は、本発明の第1の実施例を示す工程
図である。図1(a)に示すようにGaAs基板1上に
GaAs層2を結晶成長し、更にその表面にInAs/
GaAsの単原子層超格子を5周期成長してマスク層3
とした。結晶成長には分子線結晶成長法(MBE)を用
いた。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a process diagram showing a first embodiment of the present invention. As shown in FIG. 1A, a GaAs layer 2 is crystal-grown on a GaAs substrate 1, and InAs /
The mask layer 3 is formed by growing a GaAs monoatomic layer superlattice for 5 periods.
And A molecular beam crystal growth method (MBE) was used for crystal growth.

【0011】次に、同図(b)に示すように基板温度を
160℃に加熱し、5×10-5Torrの塩素ガス5中
で加速電圧3kVの電子ビーム4を表面に部分的に照射
し、電子ビームアシストエッチングを5分間行った。こ
の結果、電子ビーム4を照射した部分の超格子構造マス
ク層3だけがエッチングされ、パターンが形成できた。
一方、電子ビーム4が照射されなかった超格子構造マス
ク層3には塩素ガス5によるエッチングは起こらなかっ
た。
Next, as shown in FIG. 3B, the substrate temperature is heated to 160 ° C., and the surface is partially irradiated with an electron beam 4 with an accelerating voltage of 3 kV in chlorine gas 5 of 5 × 10 -5 Torr. Then, electron beam assisted etching was performed for 5 minutes. As a result, only the portion of the superlattice structure mask layer 3 irradiated with the electron beam 4 was etched and a pattern could be formed.
On the other hand, the superlattice structure mask layer 3 which was not irradiated with the electron beam 4 was not etched by the chlorine gas 5.

【0012】次に同図(c)に示すように基板温度を1
00℃に下げ、5×10-5Torrの塩素ガス5でガス
エッチングを行った。この結果、電子ビームアシストエ
ッチングにより形成した超格子構造マスク層の開口部6
を通してのみGaAs成長層2のガスエッチングができ
た。
Next, the substrate temperature is set to 1 as shown in FIG.
The temperature was lowered to 00 ° C., and gas etching was performed with chlorine gas 5 of 5 × 10 −5 Torr. As a result, the openings 6 of the superlattice structure mask layer formed by electron beam assisted etching
The GaAs growth layer 2 was gas-etched only through.

【0013】図2は、本発明の第2の実施例を示す工程
図である。
FIG. 2 is a process diagram showing a second embodiment of the present invention.

【0014】図2(a)に示すようにGaAs基板1上
にGaAs層2を結晶成長し、更にその表面にInAs
/GaAsの単原子層超格子を5周期成長してマスク層
3とした。結晶成長には分子線結晶成長法(MBE)を
用いた。
As shown in FIG. 2A, a GaAs layer 2 is crystal-grown on a GaAs substrate 1 and InAs is further formed on the surface thereof.
As a mask layer 3, a monoatomic layer superlattice of / GaAs was grown for 5 cycles. A molecular beam crystal growth method (MBE) was used for crystal growth.

【0015】次に、同図(b)に示すように基板温度を
160℃に加熱し、5×10-5Torrの塩素ガス5中
で加速電圧3kVの電子ビーム4を表面に部分的に照射
し、電子ビームアシストエッチングを5分間行った。こ
の結果、電子ビーム4を照射した部分の超格子構造マス
ク層3だけがエッチングされ、パターンが形成できた。
一方、電子ビーム4が照射されなかった超格子構造マス
ク層3には塩素ガス5によるエッチングは起こらなかっ
た。
Next, as shown in FIG. 2B, the substrate temperature is heated to 160 ° C., and the surface is partially irradiated with an electron beam 4 with an accelerating voltage of 3 kV in a chlorine gas 5 of 5 × 10 -5 Torr. Then, electron beam assisted etching was performed for 5 minutes. As a result, only the portion of the superlattice structure mask layer 3 irradiated with the electron beam 4 was etched and a pattern could be formed.
On the other hand, the superlattice structure mask layer 3 which was not irradiated with the electron beam 4 was not etched by the chlorine gas 5.

【0016】次に同図(c)に示すように基板温度を5
0℃に下げ、5×10-5Torrの塩素ガス5中で加速
電圧500Vのシャワー状電子ビーム27を基板前面に
照射し、30分間電子ビームアシストエッチングを行っ
た。この結果、電子ビームアシストエッチングにより形
成した超格子構造マスク層3の開口部6を通してのみG
aAs成長層2のガスエッチングができた。一方、超格
子構造マスク層3が残っている部分ではエッチングは進
行せずマスク効果が十分ある事が確認できた。以上の実
施例ではGaAs層の加工の例を示しているが、本発明
の方法によれば、GaAs/AlGaAsのヘテロ構造
または量子井戸構造の加工ができる事は言うまでもな
い。
Next, as shown in FIG. 3C, the substrate temperature is set to 5
The temperature was lowered to 0 ° C., and the front surface of the substrate was irradiated with a shower-shaped electron beam 27 with an acceleration voltage of 500 V in chlorine gas 5 of 5 × 10 −5 Torr, and electron beam assisted etching was performed for 30 minutes. As a result, G is formed only through the openings 6 of the superlattice structure mask layer 3 formed by electron beam assisted etching.
Gas etching of the aAs growth layer 2 was completed. On the other hand, it was confirmed that etching did not proceed in the portion where the superlattice structure mask layer 3 remained, and the mask effect was sufficient. Although the example of processing the GaAs layer is shown in the above embodiments, it goes without saying that the method of the present invention can process a GaAs / AlGaAs heterostructure or a quantum well structure.

【0017】[0017]

【発明の効果】以上に実施例を挙げて詳しく説明したよ
うに、本発明の微細加工方法によれば、InAsとGa
Asとの超格子構造をマスクとして用いる事で従来問題
となっていた、マスクの制御性および再現性の問題を回
避し、GaAs又はGaAs/AlGaAsのヘテロ構
造若しくは量子井戸構造をナノメータスケールの精度で
優れた制御性および再現性をもって微細に加工できた。
As described above in detail with reference to the embodiments, according to the fine processing method of the present invention, InAs and Ga are formed.
By using the superlattice structure with As as a mask, the problems of controllability and reproducibility of the mask, which had been a problem in the past, are avoided, and a heterostructure or a quantum well structure of GaAs or GaAs / AlGaAs with a nanometer scale accuracy is obtained. Fine processing was possible with excellent controllability and reproducibility.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の微細加工方法を示す工
程図である。
FIG. 1 is a process drawing showing a fine processing method according to a first embodiment of the present invention.

【図2】本発明の第2の実施例の微細加工方法を示す工
程図である。
FIG. 2 is a process drawing showing the fine processing method according to the second embodiment of the present invention.

【図3】従来例の微細加工方法を示す工程図である。FIG. 3 is a process diagram showing a conventional fine processing method.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 GaAs成長層 3 超格子構造マスク層 33 InAsマスク層 4 電子ビーム 5 塩素ガス 6 開口部 27 シャワー状電子ビーム 1 GaAs Substrate 2 GaAs Growth Layer 3 Superlattice Structure Mask Layer 33 InAs Mask Layer 4 Electron Beam 5 Chlorine Gas 6 Opening 27 Shower Electron Beam

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/778 29/80 29/812 9171−4M H01L 29/80 A 9171−4M H ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 29/778 29/80 29/812 9171-4M H01L 29/80 A 9171-4MH

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 GaAs又はGaAs/AlGaAsの
ヘテロ構造若しくは量子井戸構造の化合物半導体表面に
InAsとGaAsとの超格子構造を積層する工程と、
前記超格子構造にハロゲン原子を含む反応性ガス中で電
子ビームを照射して前記超格子構造を部分的にエッチン
グする事によりパターンを形成する工程と、このパター
ン形成工程により形成されたパターン化超格子構造をマ
スクとして前記GaAs又はGaAs/AlGaAsの
ヘテロ構造若しくは量子井戸構造の化合物半導体のエッ
チングをする工程とを含むことを特徴とする化合物半導
体の微細加工方法。
1. A step of laminating a superlattice structure of InAs and GaAs on a compound semiconductor surface of GaAs or a heterostructure of GaAs / AlGaAs or a quantum well structure,
A step of forming a pattern by partially etching the superlattice structure by irradiating the superlattice structure with an electron beam in a reactive gas containing a halogen atom; and a patterned superstructure formed by the pattern forming step. And a step of etching the compound semiconductor having the GaAs or GaAs / AlGaAs heterostructure or quantum well structure using the lattice structure as a mask.
【請求項2】 GaAs又はGaAs/AlGaAsの
ヘテロ構造若しくは量子井戸構造の化合物半導体のエッ
チングは、ハロゲン原子を含む反応性ガスによるガスエ
ッチングである請求項1に記載の微細加工方法。
2. The microfabrication method according to claim 1, wherein the etching of the compound semiconductor having a hetero structure or a quantum well structure of GaAs or GaAs / AlGaAs is gas etching using a reactive gas containing a halogen atom.
【請求項3】 GaAs又はGaAs/AlGaAsの
ヘテロ構造若しくは量子井戸構造の化合物半導体のエッ
チングはハロゲン原子を含む反応性ガス中で電子ビーム
を照射して行う電子ビームアシストエッチングである請
求項1に記載の微細加工方法。
3. The etching of a compound semiconductor of GaAs or a heterostructure of GaAs / AlGaAs or a quantum well structure is electron beam assisted etching performed by irradiating an electron beam in a reactive gas containing a halogen atom. Fine processing method.
JP2255093A 1993-02-10 1993-02-10 Compound semiconductor microfabrication method Expired - Fee Related JPH0783017B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2255093A JPH0783017B2 (en) 1993-02-10 1993-02-10 Compound semiconductor microfabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2255093A JPH0783017B2 (en) 1993-02-10 1993-02-10 Compound semiconductor microfabrication method

Publications (2)

Publication Number Publication Date
JPH06236862A JPH06236862A (en) 1994-08-23
JPH0783017B2 true JPH0783017B2 (en) 1995-09-06

Family

ID=12085956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2255093A Expired - Fee Related JPH0783017B2 (en) 1993-02-10 1993-02-10 Compound semiconductor microfabrication method

Country Status (1)

Country Link
JP (1) JPH0783017B2 (en)

Also Published As

Publication number Publication date
JPH06236862A (en) 1994-08-23

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