JPH0783056B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0783056B2 JPH0783056B2 JP16531588A JP16531588A JPH0783056B2 JP H0783056 B2 JPH0783056 B2 JP H0783056B2 JP 16531588 A JP16531588 A JP 16531588A JP 16531588 A JP16531588 A JP 16531588A JP H0783056 B2 JPH0783056 B2 JP H0783056B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- signal line
- signal lines
- line
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] この発明は複数の対を成す信号線(例えばデータバス,
アドレス等)を有する半導体装置において、信号線間の
クロストークの低減に関するものである。The present invention relates to a plurality of pairs of signal lines (for example, data bus, data bus,
The present invention relates to reduction of crosstalk between signal lines in a semiconductor device having an address or the like).
[従来の技術] 第4図は、従来の半導体装置内での2本で対を成す信号
線(例えばデータバス,アドレス)の配置の一例を示し
た平面図である。[Prior Art] FIG. 4 is a plan view showing an example of an arrangement of signal lines (for example, a data bus and an address) paired by two lines in a conventional semiconductor device.
図中(1)は半導体基板(あるいは絶縁膜)、(2)は
信号線である。In the figure, (1) is a semiconductor substrate (or an insulating film), and (2) is a signal line.
また第5図は、第4図に示すZ・Zにおける断面図であ
る。図中(4)は絶縁膜である。Further, FIG. 5 is a sectional view taken along line ZZ shown in FIG. In the figure, (4) is an insulating film.
次に図を用いて、従来の半導体装置の説明を行なう。Next, a conventional semiconductor device will be described with reference to the drawings.
第4,5図に示した例では、複数の信号線(2)の対 は各々半導体基板(1)の同一平面上に平行に配置され
た場合について示してある。通常多くの信号線(2)
は、レイアウトの都合上、第4図に示したように半導体
装置内にて集中して配置される場合が多い。In the example shown in FIGS. 4 and 5, a pair of signal lines (2) Shows the case where they are arranged in parallel on the same plane of the semiconductor substrate (1). Usually many signal lines (2)
In many cases, due to the layout, they are arranged in a concentrated manner in the semiconductor device as shown in FIG.
[発明が解決しようとする課題] 近年の急激なまでの半導体装置の大容量化、高集積化に
伴い、半導体装置内部の信号線も高密度化を強いられ、
その結果第5図中の信号線(2)の線間距離L2も小さく
ならざるを得ない。これに伴い各々の線間浮遊容量C2は
大きくなり、その結果クロストークによる悪影響が大き
な問題となってきている。そのため第4図に示したよう
な一対の信号線(2)(例えば に対して各々異なるノイズが加わるため、半導体装置の
誤動作を引き起こす結果となっており、その対策が課題
であった。[Problems to be Solved by the Invention] With the rapid increase in capacity and integration of semiconductor devices in recent years, the signal lines inside the semiconductor devices are also required to have higher density.
As a result, the line distance L 2 of the signal line (2) in FIG. 5 is unavoidable. Along with this, the line-to-line stray capacitance C 2 has increased, and as a result, the adverse effect of crosstalk has become a serious problem. Therefore, a pair of signal lines (2) as shown in FIG. However, different noises are added to each of them, resulting in malfunction of the semiconductor device, and a countermeasure against the problem has been a problem.
この発明は、上記のような課題を解決するためになされ
たもので、信号線(2)間のクロストークによる悪影響
を緩和することを目的としている。The present invention has been made to solve the above problems, and an object thereof is to mitigate the adverse effects of crosstalk between signal lines (2).
[課題を解決する為の手段] この発明に係る半導体装置は、上述した一対から成る信
号線群に対し、各々を半導体基板内で縦方向に分離して
配置し、かつツイスト(Twist)するようにした。[Means for Solving the Problems] In the semiconductor device according to the present invention, each of the above-described pair of signal lines is arranged separately in the vertical direction in the semiconductor substrate, and twisted (Twist). I chose
[作用] この発明における半導体装置の信号線群は、各群を半導
体基板内で縦方向に分離して配置し、かつ、ツイストす
ることにより、一対の信号線両方に同一のノイズが加わ
るようにし、半導体装置の誤動作の発生を押さえようと
したものである。[Operation] The signal line groups of the semiconductor device according to the present invention are arranged such that the groups are vertically separated in the semiconductor substrate and twisted so that the same noise is applied to both of the pair of signal lines. It is intended to suppress the occurrence of malfunction of the semiconductor device.
[実施例] 以下この発明の一実施例を図について説明する。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例である半導体装置の内部信
号線配置を示した平面図である。また、第2図は第1図
のX・Xにおける断面図、第3図は第1図のY・Yにお
ける断面図である。図中(1)は半導体基板(あるいは
絶縁膜)、(2)は信号線、(3)はコンタクトホー
ル、(4)は絶縁膜である。FIG. 1 is a plan view showing the arrangement of internal signal lines of a semiconductor device according to an embodiment of the present invention. 2 is a sectional view taken along line XX of FIG. 1, and FIG. 3 is a sectional view taken along line YY of FIG. In the figure, (1) is a semiconductor substrate (or an insulating film), (2) is a signal line, (3) is a contact hole, and (4) is an insulating film.
次に第1,2,3,図によってこの発明の一実施例である半導
体装置の作用について説明を行う。この実施例の特徴
は、半導体装置内の信号線(2)の対を各々縦方向に分
離し、かつツイスト(Twist)することにある。Next, the operation of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. The feature of this embodiment resides in that each pair of signal lines (2) in the semiconductor device is vertically separated and twisted.
第2図にて、信号線(2)の対 は各々縦方向にL2の距離離れて配置されている。ここで
横方向の浮遊容量C1に対し、縦方向の浮遊容量C2が充分
小さくC1>C2なるようにL1,L2を設定してある。このた
め、例えば下層の信号線(2)のA1においては浮遊容量
C1を介してA0,A2から影響を受け、また上層の信号線
(2)の から主に影響を受ける。In Fig. 2, a pair of signal lines (2) Are arranged vertically at a distance of L 2 . Here, L 1 and L 2 are set so that the stray capacitance C 2 in the vertical direction is sufficiently small with respect to the stray capacitance C 1 in the horizontal direction and C 1 > C 2 . Therefore, for example, in A 1 of the lower signal line (2), stray capacitance is present.
It is affected by A 0 and A 2 via C 1 and also the signal line (2) of the upper layer Mainly affected by.
上記は逆に第3図のようにコンタクトホール(3)を経
て各信号線(2)をツイストする。下層信号線(2)の
A1に対しては から、また、上層信号線(2)の に対してはA0,A2から主に影響を受ける配置になってい
る。On the contrary, as shown in FIG. 3, each signal line (2) is twisted through the contact hole (3). Of lower layer signal line (2)
For A 1 From the upper signal line (2) For A, the arrangement is mainly influenced by A 0 and A 2 .
このため、コンタクトホール(3)を介して信号線
(2)をツイストすることにより信号線(2)の対 の各々に同一の影響(ノイズ)が加わるため半導体装置
内部の回路の誤動作を押えることができる。Therefore, by twisting the signal line (2) through the contact hole (3), the signal line (2) is paired. Since the same influence (noise) is applied to each of the above, malfunction of the circuit inside the semiconductor device can be suppressed.
また、上記実施例では、第1図に示したような方式で縦
方向のツイスト(Twist)を実施した場合について述べ
たが、信号線対を縦方向に分離して配置し、かつツイス
ト(Twist)を加えることにより、線間浮遊容量を介し
てのノイズ対策を施こすものであれば。いかなる種類の
ツイスト方式のものであっても適用することができる。Further, in the above embodiment, the case where the vertical twist (Twist) is carried out by the method as shown in FIG. 1 has been described. ) Is added, so long as noise countermeasures are taken for via stray capacitance between lines. Any type of twist system can be applied.
[発明の効果] 以上のようにこの発明によれば、配線の集積度を上げる
ことができると共に、信号線のノイズ対策が図ることが
でき、半導体装置の誤動作の発生を押えることが可能と
なる。[Effects of the Invention] As described above, according to the present invention, it is possible to increase the degree of integration of wirings, prevent signal line noise, and suppress malfunctions of a semiconductor device. .
第1図はこの発明の一実施例である半導体装置の内部信
号線配置を示す平面図、第2図、第3図は、各々第1図
中のX・Xにおける断面図、及びY・Yにおける断面図
である。第4図は従来の半導体装置の内部信号線配置を
示した平面図、第5図は第4図中のZ・Zにおける断面
図である。 図中、(1)は半導体基板(あるいは絶縁膜)、(2)
は信号線、(3)はコンタクトホール、(4)は絶縁膜
を示す。 なお、図中、同一符号は同一、又は相当部分を示す。1 is a plan view showing the arrangement of internal signal lines of a semiconductor device according to an embodiment of the present invention, FIGS. 2 and 3 are sectional views taken along line XX in FIG. 1, and Y.Y. FIG. FIG. 4 is a plan view showing the arrangement of internal signal lines of a conventional semiconductor device, and FIG. 5 is a sectional view taken along the line Z--Z in FIG. In the figure, (1) is a semiconductor substrate (or insulating film), (2)
Is a signal line, (3) is a contact hole, and (4) is an insulating film. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
置において、各信号線対を縦方向に分離して配置し、か
つツイスト(Twist)を施すことにより、上記信号線対
に同一のノイズが加わるようにし、半導体装置内部の回
路の誤動作を押えるよう図ったことを特徴とする半導体
装置。1. A semiconductor device having a pair of signal line pairs, wherein each signal line pair is arranged separately in the vertical direction, and twisted (Twist) to provide the same signal line pair. The semiconductor device is designed to suppress the malfunction of the circuit inside the semiconductor device by adding the noise of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16531588A JPH0783056B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16531588A JPH0783056B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0215655A JPH0215655A (en) | 1990-01-19 |
| JPH0783056B2 true JPH0783056B2 (en) | 1995-09-06 |
Family
ID=15809996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16531588A Expired - Lifetime JPH0783056B2 (en) | 1988-07-01 | 1988-07-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783056B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0430452A (en) * | 1990-05-25 | 1992-02-03 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1988
- 1988-07-01 JP JP16531588A patent/JPH0783056B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0215655A (en) | 1990-01-19 |
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