JPH0783216B2 - Half-wave rectifier - Google Patents
Half-wave rectifierInfo
- Publication number
- JPH0783216B2 JPH0783216B2 JP61299221A JP29922186A JPH0783216B2 JP H0783216 B2 JPH0783216 B2 JP H0783216B2 JP 61299221 A JP61299221 A JP 61299221A JP 29922186 A JP29922186 A JP 29922186A JP H0783216 B2 JPH0783216 B2 JP H0783216B2
- Authority
- JP
- Japan
- Prior art keywords
- wave rectifier
- transistors
- δvi
- present
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Rectifiers (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOS型集積回路に関し、特にMOS型集積回路にお
ける半波整流器に関する。The present invention relates to a MOS type integrated circuit, and more particularly to a half-wave rectifier in a MOS type integrated circuit.
従来、この種のMOS型集積回路上に半波整流器を構成す
るためには、例えばスイッチトキャパシタ回路で構成さ
れる半波整流器がある。(例えばP.E.Allen and E.Sanc
hex Sine−ncio:“Switched capacitor circu−its"Van
Nostrand Reinhold Co(1984))。Conventionally, in order to form a half-wave rectifier on this type of MOS integrated circuit, there is a half-wave rectifier composed of, for example, a switched capacitor circuit. (Eg PE Allen and E. Sanc
hex Sine−ncio: “Switched capacitor circu−its” Van
Nostrand Reinhold Co (1984)).
上述した従来の半波整流器は回路規模が大きくなるとい
う欠点がある。The above-mentioned conventional half-wave rectifier has a drawback that the circuit scale becomes large.
上述した従来の半波整流器回路に対し、本発明はMOS集
積回路においてバランスをくずした一対の差動対で構成
出来るという独創的内容を有する。In contrast to the conventional half-wave rectifier circuit described above, the present invention has an original content that it can be configured by a pair of differential pairs that are out of balance in a MOS integrated circuit.
本発明の半波整流器はトランジスタのゲート幅とゲート
長の比が互いに異なる2つのトランジスタから成る差動
対を有している。The half-wave rectifier of the present invention has a differential pair made up of two transistors having different gate width and gate length ratios.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の第一の実施例を示す回路図である。同
図においてM1,M2はNチャンネルトランジスタであり、I
SSは定電流源を示す。そしてトランジスタM1およびM2の
ゲート幅とゲート長の比をそれぞれW1/L1,W2/L2とし、 (W2/L2)/(W1/L1)=k(≠1) ……(1) とおく。ここでk>1として考えても一般性を失わな
い。FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the figure, M1 and M2 are N-channel transistors, and I
SS indicates a constant current source. Then, the ratios of the gate width and the gate length of the transistors M1 and M2 are set to W1 / L1 and W2 / L2, respectively, and (W2 / L2) / (W1 / L1) = k (≠ 1) (1). The generality is not lost even if k> 1 is considered here.
トランジスタM1およびM2のドレイン電流をそれぞれId1
およびId2、ゲート電圧をVgs1およびVgs2とすると Id1=α(Vgs1−Vt)2 (2) Id2=kα(Vgs2−Vt)2 (3) ただし、VtはトランジスタM1およびM2のスレッショルド
電圧であり、αはトランジスタのデバイスパラメータで
決まる定数である。Set the drain currents of the transistors M1 and M2 to I d1
And I d2 and the gate voltages are V gs1 and V gs2 , I d1 = α (V gs1 −V t ) 2 (2) I d2 = kα (V gs2 −V t ) 2 (3) where V t is a transistor It is the threshold voltage of M1 and M2, and α is a constant determined by the device parameter of the transistor.
また Id1+Id2=Iss (4) Vgs1−Vgs2=ΔVi (5) とおける。Also, I d1 + I d2 = I ss (4) V gs1 −V gs2 = ΔVi (5).
(1)〜(5)式より が求まる。(6)式において、第3項の は第2図に示すように、入力信号ΔViに対してΔVi=0
の点を点対称とする曲線になることが知られている。一
方、第1項の は第2図に示すように、入力信号ΔViに対して2次曲線
となる。第2項の は、第1項の2次曲線のy切片と考えて良い。From equations (1) to (5) Is required. In equation (6), the third term As shown in FIG. 2, ΔVi = 0 with respect to the input signal ΔVi.
It is known that the curve becomes a point symmetric with respect to the point. On the other hand, in the first term Shows a quadratic curve with respect to the input signal ΔVi, as shown in FIG. Of the second term Can be considered as the y-intercept of the quadratic curve of the first term.
従って、第2図に示すようにkを大きくしていった時の
Id1の特性は傾きが次第に小さくなるとともに負入力時
のId1の値も小さくなるので、半波整流特性を持つこと
がわかる。一方、Id2の特性はId1の差動出力となってい
るから同様に半波整流特性を持つ。Therefore, when k is increased as shown in FIG.
The characteristics of I d1 is also small values of I d1 in the negative input with inclination becomes progressively smaller, it can be seen that with a half-wave rectification characteristic. On the other hand, since the characteristic of I d2 is the differential output of I d1 , it also has a half-wave rectification characteristic.
すなわち第1図のようにトランジスタM3およびM4から成
るカレントミラー回路により、トランジスタM2のドレイ
ン電流をモニター出来る。ここで、カレントミラ回路出
力に抵抗R1を接続すれば電流出力が電圧に変換できる。That is, the drain current of the transistor M2 can be monitored by the current mirror circuit composed of the transistors M3 and M4 as shown in FIG. Here, if a resistor R1 is connected to the output of the current mirror circuit, the current output can be converted into a voltage.
第3図はk=10としてシミュレーションしたΔVi−Id1
特性をもとに入力信号ΔViが正弦波の場合のId1の特性
を時間軸tについて示してある。Figure 3 shows ΔVi-I d1 simulated with k = 10.
The characteristic of Id 1 when the input signal ΔVi is a sine wave based on the characteristic is shown with respect to the time axis t.
第4図は本発明の第二の実施例の回路図である。M1およ
びM2はトランジスタ、R1は抵抗、C1はコンデンサ、ISS
は定電流源、ΔViは入力信号であり交流信号VDDは電源
電圧である。このとき交流入力信号ΔViに対して直流出
力電圧V0は第5図に示すようになる。FIG. 4 is a circuit diagram of the second embodiment of the present invention. M1 and M2 are transistors, R1 is a resistor, C1 is a capacitor, I SS
Is a constant current source, ΔVi is an input signal, and AC signal V DD is a power supply voltage. At this time, the DC output voltage V 0 with respect to the AC input signal ΔVi becomes as shown in FIG.
以上説明したように本発明はトランジスタのゲート幅と
ゲート長の比が互いに異なる2つのトランジスタによっ
て差動対を構成することにより、半波整流器を実現出来
る効果がある。As described above, the present invention has an effect of realizing a half-wave rectifier by forming a differential pair with two transistors having different gate width and gate length ratios.
第1図は本発明の第1の実施例を示す回路図、第2図は
第1図の特性図、第3図は第1図においてk=10とした
場合のシミュレーション値、第4図は本発明の第2の実
施例を示す回路図、第5図は第4図の特性図である。 M1,M2,M3,M4……トランジスタ、R1……抵抗、C1……コ
ンデンサ、ISS……定電流源。FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a characteristic diagram of FIG. 1, FIG. 3 is a simulation value when k = 10 in FIG. 1, and FIG. FIG. 5 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is a characteristic diagram of FIG. M1, M2, M3, M4 …… Transistor, R1 …… Resistor, C1 …… Capacitor, I SS …… Constant current source.
Claims (1)
(W)とゲート長(L)の比(W/L)が互いに異なる2
つのトランジスタからなる差動対から構成され、前記差
動対を構成する2つのゲート間に信号が入力され、ドレ
イン電流を出力とすることを特徴とする半波整流器。1. A constant current drive, wherein the ratio (W / L) of the gate width (W) and the gate length (L) of the transistor is different from each other.
A half-wave rectifier comprising a differential pair composed of two transistors, wherein a signal is input between two gates constituting the differential pair and a drain current is output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299221A JPH0783216B2 (en) | 1986-12-15 | 1986-12-15 | Half-wave rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299221A JPH0783216B2 (en) | 1986-12-15 | 1986-12-15 | Half-wave rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63151109A JPS63151109A (en) | 1988-06-23 |
| JPH0783216B2 true JPH0783216B2 (en) | 1995-09-06 |
Family
ID=17869720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61299221A Expired - Fee Related JPH0783216B2 (en) | 1986-12-15 | 1986-12-15 | Half-wave rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783216B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107227A (en) * | 1988-02-08 | 1992-04-21 | Magellan Corporation (Australia) Pty. Ltd. | Integratable phase-locked loop |
| WO1999037019A1 (en) * | 1998-01-20 | 1999-07-22 | T.I.F. Co., Ltd. | Detector circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853205A (en) * | 1981-09-25 | 1983-03-29 | Fujitsu Ltd | RMS detection circuit |
| JPS60236190A (en) * | 1984-05-10 | 1985-11-22 | Nec Corp | Sensor amplifier |
| JPS61148906A (en) * | 1984-12-24 | 1986-07-07 | Hitachi Ltd | Mos amplification output circuit |
| JPH0677035B2 (en) * | 1985-03-29 | 1994-09-28 | クラリオン株式会社 | AC-DC conversion circuit |
-
1986
- 1986-12-15 JP JP61299221A patent/JPH0783216B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63151109A (en) | 1988-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |