JPH0783245B2 - Continuous pulse signal detector - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a continuous pulse signal detecting device which can be configured with a smaller number of elements than conventional ones, a reference signal can be easily set, and stable operation can be guaranteed.

2. Description of the Related Art A general continuous pulse detecting device sets a reference signal at a timing obtained by delaying a detected signal and is configured as shown in the circuit diagram of FIG.

That is, the conventional device has first, second, and third flip-flops (D side, hereinafter referred to as FF) 21, 22, and 23, and each clock input terminal (CK) is a reference signal terminal 12 Connected to the
The input terminal (D) of the first F / F21 is the detected signal terminal 11
The input terminals (D) of the second and third F · F22, 23 are connected to the non-inverted signal output terminals (Q) of the preceding stages, respectively, and the three-input coincidence gate (AND circuit) 9 is connected. The input terminal is connected, and the non-inverted signal output terminal of the third F / F23 is connected to the remaining input terminal of the 3-input matching gate 9,
The output signal terminal of the 3-input coincidence gate 9 is the fourth F · F2
4 is connected to an input terminal (D), and its clock input terminal (CK) is connected to a reference signal terminal 12 via an inverting gate (inverter) 10. The operation waveform is shown in FIG. In FIG. 4, 11 is a detected signal, 12 is a reference signal, and 24 (Q)
Is the detection result output signal, 21 (Q), 22 (Q), 23 (Q) are the
These are the output signals of the first, second and third F · F 21, 22, 23.

First, the reference signal is set at the timing when the detected signal is delayed. This reference signal does not become discontinuous and is used as a clock for sampling (latching) the detected signal. It is often easy for the system to generate this reference signal, and the timing can be easily set.

Now, when the detected signal is not input, the first F / F21
"0" of the input terminal (D) of is taken into the first F / F21 at each rising edge of the reference signal, and the second F / F22,
It is sent to the third F · F23, and the output of the continuous pulse detection gate 9 remains “0”. Next incorporated into the first F · F21 at the rising edge of the reference signal when one shot eyes of the detected signal arrives at time t _2, the time t _3, t ₄ and continuously when the detected signal arrives first "1" continues to be taken into F ・ F21 of. Also at time t ₃ in the second F · F22 first F · F21
Captured the output of "1", at time t ₄ to the third F · F 23 output of the second F · F22 "1" is fetched. Therefore, the output of the continuous pulse detection gate 9 at time t ₄ is shifted to "0" to "1", the result is taken into the fourth F · F 24 at the fall of the reference signal, also arrived 3 volley or The result does not change. On the other hand, if the detected signal does not arrive even one shot, the output of the continuous pulse detection gate 9 returns to "0" at that time (t ₆ ) and the latch output of the fourth F / F24 also falls of the reference signal. Return to “0” with. By operating as described above, an output signal can be generated at the time of the third occurrence when the detected signals arrive three or more times in succession.

However, in the continuous pulse signal detection device described above, when the number of pulses to be continuously detected increases, the number of F · F configuring the shift register is required by that number of pulses, and The number of input terminals of the pulse detection gate 9 and the number of decoding wirings are also increased, and the power consumption and the chip size both increase when used as an integrated circuit.

Means for Solving the Problem In order to solve the above problems, the present invention cancels the reset of the counter upon the arrival of the first first pulse of a continuous pulse signal (detected signal), and the counter is released. Thus, the second and subsequent detected signals are counted, and the counter is reset if even one signal does not arrive.

Action Even if the number of pulses for continuous detection increases by counting with the counter after the second generation of the detected signal, it is possible to double the number of detections by increasing the number of stages of the counter by one.
When integrated, it does not increase power consumption or chip size.

Embodiment An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit configuration diagram of the embodiment, and FIG. 2 is an operation timing chart thereof.

The clock input terminal (CK) of the first F · F1 (T type) is connected to the detected signal terminal 11, and the inverting output terminal is the second F · F1.
It is connected to the clock input terminal (CK) of F2 (T type)
The non-inverting output terminal (Q) of F / F2 is connected to the clock input terminal (CK) of the third F / F3, the input terminal D of the third F / F3 is fixed to the power supply potential, and the non-inverting The output terminal (Q) is connected to the detection result output signal terminal 13, the clock input terminal (CK) of the fourth F / F4 is connected to the reference signal terminal 12, and the reset input terminal () has a match gate (2). Input NAND
Circuit) 7 is connected to the output signal terminal, and the input terminal thereof is connected to the detected signal terminal 11 and the reference signal terminal 12, respectively.
The non-inverting output terminal (Q) of the fourth F · F4 is connected to the fifth F
-The fifth F / F5 clock input terminal (CK) is connected to the F5 input terminal (D) and the reference signal terminal 12 is connected through the inverting gate 8 to the fifth F / F5 inverted output. () Is the reset input terminal of the first, second, and third F · F1, 2, 3 ()
Is being applied to.

The configuration of this embodiment will be described with reference to the operation timing chart of FIG. 2. First, the reference signal is set at a timing wider than the detected signal. This reference signal does not become discontinuous and is used at a timing that covers the detected signal. It is often easy for the system to generate this reference signal, and the timing can be easily set.

By the way, when the detected signal is not input, the fourth F / F4 is not reset.
"1" is taken into and the 5th edge continues on the falling edge.
The output of the 4th F ・ F4 is taken into F ・ F5 of
Since the inverted output of F5 is "0", the 2-bit counter composed of the first F-F1 and the second F-F2 continues to be reset. Next, at time t ₂ , when the first signal of the detected signal arrives, the fourth F · F4 is reset, and the result is taken in to the fifth F · F5 at the fall of the reference signal, and the fifth F · F5 is fetched. The inverted output () of F5 becomes "1", the reset of the 2-bit counter is released, and the counter can count the second and subsequent occurrences of the detected signal. When three consecutive pulses, that is, two consecutive pulses after the second shot, are counted at time t ₄ , the third F · F latches and the detection is completed. Meanwhile the counter and latch circuit at the time if not arriving signal to be detected even one shot is at time t ₆ is reset, ready for the next continuous pulse arrival.

As described above, as described in the operation of the embodiment of the present invention, the detection of three consecutive pulses is exactly the same as the conventional one. However, even if the number of detected pulses increases, the number of elements may increase in proportion thereto. Absent.

As described above, in the continuous pulse signal detection device of the present invention, the number of elements does not increase even if the number of detection pulses increases,
Moreover, the number of detection pulses can be changed only by changing the wiring of the circuit, and as a result, the IC chip size and power consumption can be reduced, which is a great effect.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is an operation waveform diagram of each part thereof, and FIGS. 3 and 4 are circuit configuration diagrams and operation waveform diagrams of a conventional continuous pulse signal detecting device. Is. 1 to 5 ... First to fifth flip-flops, 7 ... coincidence gate, 8 ... inversion gate, 11 ... detected signal terminal, 12
…… Reference signal terminal, 13 …… Detection result output signal terminal.

Claims (1)

[Claims] 1. A clock input terminal (CK) of a first flip-flop (FF) is connected to a detected signal applying terminal,
The inverted output terminal () of the first F · F is the second F · F
Is connected to the clock input terminal (CK) of the
F and the second F · F constitute a counter for counting the arrival of the detected signal, and the non-inverting output terminal (Q) of the second F · F is the clock input terminal of the third F · F ( CK), the input terminal (D) of the third FF is fixed to the power supply potential, and the non-inverting output terminal (Q) of the third FF
Is connected to the detection result output signal output terminal, and the third F
・ Fourth F that holds the output of the counter by F and the reference signal application terminal is connected to the clock input terminal (CK)
The reset input terminal () of F is connected to the output terminal of the first coincidence gate to which the detected signal applying terminal and the reference signal applying terminal are connected, respectively, and the fourth F
The non-inverting output terminal (Q) of F is connected to the input terminal (D) of the fifth FF, and the clock input terminal (CK) of the fifth FF is through the first inverting gate. The discontinuity detection circuit is connected to the reference signal application terminal, and the fourth F · F and the fifth F · F form a discontinuity detection circuit, and the output signal thereof is the counter and a holding circuit for the counter output. First
A continuous pulse signal detecting device characterized in that the first, second and third F · F are reset.