JPH0783335B2 - System multiplexing method in PCM communication - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention multiplexes digital signals sent by four PCM6 speech path systems and converts them into an existing PCM24B system (Densha Corporation PCM24 speech path system). A system multiplexing scheme for adaptation.

[Conventional technology]

The 6-channel carrier telephone system using PCM is commonly referred to as the PCM6 system in Japan, and gradually spreads as a simple and economical communication method for short distance or medium distance used in areas with relatively low call volume. However, the method is not yet unified domestically. In addition, it may be desired to collectively transmit several lines of this system between relatively remote areas that employ the same PCM6 system. In this case, in order to effectively use the communication line, As shown in the figure, the multiplexer MUX-a (10
1) is used to further multiplex four systems of PCM6 systems, and a fixed distance is transmitted via the line 100. At the side of the PCM6 system that receives this, the division device MUX-b (10
According to 2), the system is divided into four PCM6 systems again. In this way, one path 100 can transmit PCM communication for 24 communication paths as one system, which is extremely economical. Hereinafter, this system is tentatively referred to as "PCM24 system equivalent".

[Problems to be solved by the invention]

In this way, in order to connect the high-order group side (the "PCM24 system charge" side) and the low-order group side (the "PCM6 system x 4" side), it is necessary to synchronize the two, and therefore the high-order group side has been used conventionally. For the frame synchronization, an extra pulse not directly related to the information content to be transmitted is added to the transmission format (1), which is generally called stuff synchronization.

However, in general, the PCM24 system, which is a main trunk line, for example, the PCM24B system specified by Denki Kogyo Co., Ltd., has no room for adding the above-mentioned frame synchronization pulse, and there is a problem that these cannot be directly connected.

This is because the conventional PCM6 system was developed only for application in the local area and did not initially assume connection to the existing trunk line. Now, as one point is being concentrated, it is becoming a serious drawback.

[Means and Actions for Solving Problems]

The present invention has been made in view of the above problems,
The following multiplexing means is used to multiplex the digital signals input as the four-system PCM6 system and to adapt this to the existing PCM24B system.

That is, the frame time length of the low-order group side (PCM6 system), the format of the multiframe, and the clock are set to the high-order group (PCM2 system).
4B) The transmission format and clock are the same as each other, and they are slave-synchronized, and 4 systems in series from the low-order group side 2
A digital signal input as a binary code string is temporarily stored in a buffer storage device in units of multiple frames, converted into a serial binary code string synchronized with the higher-order group side clock, and output. Therefore, the transmission format and clock of the PCM signal obtained by the multiplexing can be automatically matched with those of the existing PCM24B system.

Hereinafter, the system multiplexing method in the PCM communication of the present invention will be described in detail.

〔Example〕

FIGS. 1 (a), (b), (c), and (d) show one embodiment of the present invention as a whole, and (a) shows the low-order group (PC) in this embodiment.
M6 system) side frame and multi-frame configuration,
(B) is a circuit configuration used in the method of the present invention, (c)
(D) is a drawing showing details of the multiplexing / dividing circuit used in the circuit shown in (b). For ease of understanding, not only the system multiplexing method in the PCM communication of the present invention but also the same division method will be described in parallel below.

Table 1 shows the specifications of the low-order group side PCM6 system used in the present invention. First, the frame structure of the PCM6 system will be described based on Table 1 and the upper part of FIG. 1 (a). One frame, which is a basic unit of information transmission, is composed of a 49-bit serial binary code string. The first 1 bit (F bit in FIG. 1 (a)) is assigned as a frame synchronization bit, and the remaining 48 bits are assigned as information words for each channel (in this case, a total of 6 channels). In other words, the information word of each call path is 8 bits per call. As will be described later, 12 frames arranged in series form one multi-frame. Further, as for the voice signal in each speech path, 5 frames out of 6 frames (hence 10 frames out of 1 multi-frame) are transmitted by an 8-bit code, and 1 frame out of 6 frames (hence 2 frames out of 1 multi-frame). ) Voice signal first 7 bits (1st to 7th bits) are transmitted, and the last 1 bit (8th bit) is responsible for tire signal transmission (hereinafter abbreviated as signal transmission). The above is for PCM24B system
1/6 bit stealing syste
m) that complies with what is called
As is clear from the table, the clock frequency on the low-order side (PCM6 system side) is 329 kHz, so the pulse interval within each information word is 1/329 (kHz) = 2.55 (μs) Therefore, the time length of one frame (in other words, If so, the audio signal sampling interval) is 2.55 (μs) × 49 (bit) = 125 (μs) Therefore, the sampling frequency is the same as that of the existing PCM24B system, such as 1/125 (μs) = 8 (kHz). To configure.

Further, as shown in the lower part of FIG. 1 (a) and Table 2, one multi-frame is composed of 12 frames. The length of one multi-frame is 125 (μs) × 12 (Frame) = 15 (ms). As shown in the second column (F-bit column) of Table 2,
A fixed time pattern (1,0,0,0,1,1,1) is set for the frame synchronization bit (F bit) with one multiframe as a cycle.
0,1,1,1,0 game information) is attached, and this functions as information for frame synchronization. This F-bit pulse pattern is also the same as that of the PCM24B system.

Next, as described above, the 1 / 16-bit stealing method is used for signal transmission, and as shown in Table 2, the sixth and twelfth frames in one multiframe are used as signal frames. First on all internal channels
~ The 7th bit is used for audio signal transmission, and the 8th bit is used for signal transmission. Hereinafter, this frame is referred to as a signal frame. As mentioned above, the signal frame insertion position in the multi-frame is the same as that of the PCM24B system.

The operation of multiplexing four systems of the PCM-6 system and dividing the system again is performed by the circuit of FIGS. 1B, 1C and 1D in units of multiframe. The frame structure of the high-order group side multiplexed by this circuit is shown in FIG.
It is shown in comparison with that of 6). That is, the frame on the higher-order group side is a frame synchronization bit (F bit).
Information words for 24 channels starting with (8 bits / channel)
The number of bits per frame is 1 (b) + 8 (b / CH) × 24 (CH) = 193 (b) Also, the clock frequency on the higher-order side is set to 1.544MHz, and transmission per frame The time is 193 (b) × 1 / 1.544 (MHz) = 124 (μS), which is exactly the same as that on the low-order group side (supra).

The multi-frame structure on the high-order group side is completely the same as that of the existing PCM24B system, and is the same as that on the low-order group side except that the amount of information per frame is 193b (24 channels).

Furthermore, by performing multiplexing / division for each multi-frame, the multi-frame configuration (F-bit pulse pattern and signal frame insertion position) on the high-order group side also becomes as shown in Table 2, and this also applies to the existing PCM24B system. Exactly matches the multi-frame structure.

Next, the system synchronization format will be described. First, regarding the bit synchronization on the low-order group side (PCM6 side), in other words, on the clock synchronization of the low-order group and the high-order group, the transmission time (frame length) per frame on the low-order group side and the high-order group side is Since both have 125 μS and the amount of information contained in one frame is 193b and 49b, respectively, the following relationship must be established between the clock frequencies of both.

In order to prevent the slip phenomenon between the reference clocks between the high-order group and the low-order group (in other words, the phenomenon that the relative time positions at both ends of each frame are shifted), the low-order group side clock is fixed to the high-order group main station side clock. Need to be subordinately synchronized. FIG. 4 is a conceptual diagram for explaining the flow of the reproduction clock in this system, 103 is a clock signal (1.544 MHz continuous wave component in this case) from the received pulse train input from the main station (PCM24B terminal station device). In the clock recovery circuit to be extracted, the LC resonance circuit is used as in the usual case. Ten
Reference numeral 4 is a PLL circuit for converting the reproduced clock pulse into a clock pulse (392 kHz in this case) on the low-order side, and divides the original pulse into 1/139 (8 kHz) and multiplies this by 49. Thus, a pulse train having a desired frequency is obtained. Due to the nature of the circuit, the frequency (392kHz) and phase of the output pulse are completely slave-locked to the original clock pulse (1.544MHz). The low-order group side clock thus established functions as a transmission / reception clock for the multiplexing / division device 101, and also the low-order group side (PCM6 side) terminal stations 105a, 105b, 105c, 105d.
Are reproduced again and function as a transmission / reception clock for each of these terminal stations.

Next, regarding multi-frame synchronization, a case where four PCM6 system systems are multiplexed to obtain one PCM24B system will be described. As described above, the length of each frame between the high-order group and the low-order group is set to be completely equal to each other, but the number of pulses included in one frame and the interval between adjacent pulses are the same in the high-order group and the low-order group. Totally different. Further, since the distances between the multiplexer and each PCM6 terminal station are different, there is a possibility that the phase synchronization of the frames of the respective systems input to the multiplexer is incomplete. Furthermore, it is desirable to establish the synchronization of the high-order group and the low-order group in units of multiframes. Therefore, the serial binary code string synchronized with the clock of the low-order group side (PCM6 side) and the information word of each PCM6 system input was stored in a buffer memory in 1 multiframe unit as a parallel binary code sequence (B _UFFER M _EMORY), this was wipe the frame synchronization bit of a predetermined pattern, in series secondary code sequence synchronized with the high-order group clock A means for converting and outputting is adopted. 12 (Frame) × 6 (CH / Frame) × 8 (b) = 72 × 8 per PCM6 system of buffer memory
(B) Similar measures are taken when dividing one system of PCM24B into four systems of PCM6. On the receiving side, the F-bit pattern is decoded and the number of frames, the number of speech paths, and the inner bit of each communication channel is accurately grasped for each input pulse. Fifth
(A) and (b) are conceptual diagrams showing the flow of each communication path in the case of multiplexing and division, respectively.

A circuit constructed based on the above basic concept is shown in FIGS. 1 (b), (c) and (d). The upper part of Fig. 1 (b) is a multiplex of 4 PCM6 systems input from the left side.
Multiplexing unit that changes to PCM24B1 system and outputs it to the right, PCM24B1 system input from the right side is PCM
6 systems It is a division unit that divides into 4 systems and outputs,
In both cases, PCM6 (1) (channel number CH
Only 1,2,3 ... 6) are shown. First, in the case of system multiplexing, 1a is a BU conversion circuit that converts a received PCM signal input as a bipolar pulse train into a unipolar pulse train and outputs it, and 2a is an output of the BU conversion circuit 1a. A frame synchronization detection circuit that detects the same frame synchronization signal (F-bit pulse train) and outputs the content of the information word to a multiplexing circuit 4 described later. Reference numeral 3a cooperates with the frame synchronization detection circuit 2a to detect the input signal. Frame number, channel number,
A reception pulse generation circuit that detects the boundary time between frames and outputs the result as a control signal to the multiplexing circuit 4, the operation of which is performed by the low-order group side clock pulse extracted by the BU conversion circuit 1a. Regulated. 5a outputs the frame number of the higher-order group side (transmission side in this case) to the multiplexing circuit 4 and other control signals, and, if necessary, outputs the frame synchronization bit (F bit) to the output of the multiplexing circuit 4. )
Is a transmission pulse generation circuit for adding. Other lower group side 3
Similar outputs are obtained for the systems (PCM6 (2), (3), (4)), and the outputs of all four systems are combined by an OR circuit (not shown) and output to the line.

FIG. 1 (c) shows an internal configuration of the multiplexing circuit 4, and 4a is a serial / parallel conversion circuit (in the figure, a serial / parallel conversion circuit for converting a serial binary code string input from the frame synchronization detection circuit 2a into a parallel binary code string.
4b is a buffer memory that temporarily stores the output of the serial / parallel conversion circuit 4a, and 4c.
Is a parallel / serial conversion circuit (indicated as P / S in the figure) that reads the data stored in the buffer storage device 4b, converts it to a serial binary code string, and outputs it to the line. 4d is a multiplexing circuit. 4 is a microprocessor unit (MPU) that controls the operation of each unit of FIG.

In the above configuration, the received signal of the PCM6 (1) system (CH1,2 ... 6) input from the left side is converted into a unipolar pulse train by the BU conversion circuit 2a, and then the frame synchronization detection circuit 2a relates to the frame synchronization. Information is extracted, and the information word is input to the serial / parallel conversion circuit 4a in the multiplexing circuit 4 as a serial binary code string of the input side clock (392kHz),
It is converted into a parallel code string. On the other hand, the received pulse generation circuit 2a
Detects the frame number of the information data input to the multiplexing circuit 4 in cooperation with the frame synchronization detection circuit 3a, and sends the result as a control signal to the serial / parallel conversion circuit 4a. The MPU 4d stores the output data (parallel two-column code string) of the serial / parallel conversion circuit 4a in a predetermined address of the buffer storage device 4b according to the frame number according to a command from the serial / parallel conversion circuit 4a. When the storage of all information data for one multiframe is completed for the four input side systems, the parallel / serial conversion circuit 4c
Issues a transmission command to MPU4d. The MPU 4d adds an F bit to the start position of the multi-frame in accordance with a command from the transmission pulse generation circuit 5a, and further, the parallel / serial conversion circuit 4c converts the information data about the frame numbers sequentially instructed by the same circuit 5a.
And is converted into a serial binary code string synchronized with the transmission side clock (1.544 MHz), and further output to the line via the UB conversion circuit 6a. The above operation is for input side 4 system PCM6
The system of (1), (2), (3), and (4) is performed in series, and the output is synthesized by the OR circuit and PCM2
It is output to the line side as one 4B system system.

Next, the configuration and operation of the lower division unit in FIG. 1 (b) will be described. That is, PCM24B input from the right side
PCM for one system (channel number CH1,2,3, ... 23,24)
6 system A network that divides into 4 systems (PCM6 (1), (2), (3) and (4)). The names and functions of 1b, 2b, 3b, 5b and 6b in the figure are as follows. 1a, 2a, 3a, 5a, in the upper part of the figure, except that the number of channels of information to be processed is different.
Since they are the same as 6a, the description thereof will be omitted. 7 is a low-order group side clock 392kHz that is subordinately synchronized with the high-order group clock 1.544MHz.
Is a PLL circuit for generating the signal, and 8 is a dividing circuit. The operation of the reception pulse generating circuit 3b is regulated by the high-order group side clock (1.544MHz) extracted in the BU converter 1b, and the operation of the transmission pulse generating circuit 5b is controlled by the PLL circuit 7. It is regulated by the next group clock 392kHz. FIG. 1 (d) shows the internal circuit of the dividing circuit 8,
(S / P) is a serial / parallel conversion circuit, 8b is a buffer memory device, 8c
(P / S) is a parallel / serial conversion circuit, and 8d is an MPU. The above configuration is shown only for the single-system PCM6 (1) on the low-order group side.

With the above configuration, 1 system of PCM24B system (CH1,2,3,
...... 23, 24) is input from the right side, is converted into a unipolar pulse train by the BU conversion circuit 1b, and the frame synchronization detection circuit 2b
The frame synchronization information is extracted by and is input to the serial / parallel conversion circuit 8a in the division circuit 8 as information data synchronized with the higher-order group side clock (1.544 MHz). On the other hand, the reception pulse generation circuit 3b cooperates with the frame synchronization detection circuit 2b in series /
The frame number and the communication path number of the information data input to the parallel conversion circuit 8a are detected, and the information is sent in parallel to the conversion circuit 8a as a control signal. The serial / parallel conversion circuit 8a has a predetermined communication path (in this case, CH1,2,
6) Only the information data of 6) is converted into a parallel binary code string, and the MPU 8d receives the reception command signal from the conversion circuit 8a, and the parallel binary data is buffered according to the frame number of the buffer memory 8b. Stored in a predetermined address of. When the storage of all information data for one multi-frame is completed, the MPU8d adds an F bit to the start position of the low-order group side (PCM6 (1)) by the command signal of the transmission pulse generation circuit 5b, and then the transmission pulse The information data about the frame numbers sequentially instructed by the generation circuit 5d is transferred from the buffer storage device 8b to the parallel / serial conversion circuit 8c, where it is converted into a serial binary code string synchronized with the transmission side clock (392 kHz in this case). After being converted and converted into a bipolar pulse train by the UB conversion circuit 6B, it is output to the line as a PCM6 (1) system.

As mentioned above, the transmission format of the PCM6 system is PCM24B.
Since it is set according to that of the system, the configuration of the multiplexing / splitting system between both systems is extremely simple, and there is no special processing especially for the signal bits (dial signal) inserted every 6 frames. No longer need. In a system in which the transmission format on the high-order group side is different from that on the low-order group side, it is necessary to separate the signal bits from the voice bits in the multiplexing / dividing device, store them in the temporary buffer storage device, and then take them into the transmission code string. Becomes

Also, since the transmission format of the higher-order group side system obtained by multiplexing automatically matches that of the PCM24B system, it is possible to connect it directly to the PCM24B end pole and also to the higher-order group converter. Economical operation of the line network becomes possible.

Further, in the embodiment, the case of the multiplexing / division method between the PCM6 system and the PCM24B system has been described, but the application of the present invention is not limited to this case, and the higher-order group is, for example, the PCM30 speech path system (European standard Method) or when the low-order group is in a system other than the PCM6 system, it can be similarly applied.

〔The invention's effect〕

As described above, according to the multiplexing system of the PCM communication of the present invention, the frame time length of the low-order group side and the format of the multi-frame are made to match those of the high-order group side, and the clock of the low-order group side is set to that of the high-order group side. Information data to be subordinately synchronized and input in synchronization with the input side clock is temporarily stored in a buffer storage device in units of one multiframe, and a frame synchronization bit is added to the information data and then synchronized with the transmission side clock. Since the serial binary code string (single system in case of multiplexing, multiple system in case of division) is converted and outputted, the transmission format of the higher-order group side signal obtained by the multiplexing can be set in the desired existing system. It became possible to automatically match the transmission format and directly connect to the terminal station of the existing system.

[Brief description of drawings]

FIG. 1 ... Diagram showing an embodiment of the present invention, FIG. 1 (a) ... Diagram showing low order group (PCM6) frame and multi-frame.
The same (b) ... The figure which shows the structure of a multiplexing / division circuit network. (C) (d) ... Diagrams showing the internal configurations of the multiplexing and dividing circuits, respectively. FIG. 2 ... A diagram showing the state of multiplexing and division of four PCM6 systems, and FIG. 3 ... A diagram showing a comparison of the frame configurations of the high-order group (PCM24B) and the low-order group (PCM6). Fourth
Figure: A conceptual diagram showing the flow of the recovered clock. Fig. 5 (a)
(B) ... A conceptual diagram showing transition of each communication path in multiplexing / division. Code table 1a, 1b ... BU conversion circuit, 2a, 2b ... frame synchronization detection circuit, 3a, 3b ... received pulse generation circuit, 4 ... multiplex circuit, 5a, 5b ... transmission pulse generation circuit, 6a, 6b ... UB conversion circuit, 7 ... PLL circuit, 8 ... Dividing circuit, 100 ... Line, 101 ... Multiplexing device, 102 ... Dividing device, 103 ... Clock recovery circuit, 104 ... … PLL circuit, 105a, b, c, d …… PCM6
Terminal equipment.

Claims (2)

[Claims] 1. A single system serial 2 which synchronizes the information content of a plurality of systems of PCM communication systems input as a serial binary code string synchronized with a low order group side clock, in synchronization with a clock of a general purpose high order group side PCM communication system. PCM to convert to a binary code string and output
In the communication system multiplexing method, the frame time length of the low-order group side and the format of the multiframe are set equal to those of the high-order group side, and the pulse train obtained by dividing the clock of the high-order group side is used as the low-order group side clock. , The information contents of the PCM communication system on the low-order side are synchronized with that on the high-order side and temporarily stored in the buffer memory as a parallel binary code string for each multi-frame, and the frames are stored in the buffer memory. The parallel binary code string excluding the sync signal is taken out for each frame, serially connected in a predetermined order, and a frame synchronization bit having a predetermined temporal pattern is added to a predetermined position of each frame. After that, a system multiplexing method in PCM communication, which converts into a serial binary code string synchronized with the higher-order group side clock and outputs it in every one multi-frame. 2. The general-purpose high-order group side PCM communication system is PCM
It is a 24B system, and the low-order group side PCM communication system is 6
A carrier telephone system for a communication path, wherein the low-order group side PCM communication system transmits 6 bits of 8-bit information word per communication path.
One frame is composed of 49 bits by arranging 48 bits continuously for the communication path and adding a 1-bit frame synchronization signal to the beginning of the frame.
A multiplex system of a system in PCM communication according to claim 1, which is a PCM6 system configured by 12 frames.