JPH0783336B2 - System division method in PCM communication - Google Patents

Description

The present invention relates to a signal division method for adapting a digital signal sent by an existing PCM24B system to a PCM6 speech path system.

[Prior art]

The 6-channel carrier telephone system using PCM is commonly referred to as the PCM6 system in Japan, and is gradually becoming popular as a simple and economical communication system for short distances or medium distances in areas with relatively small call volumes. , The method has not yet been unified domestically. In addition, it may be desired to transmit several systems of this system collectively in a district that uses a relatively remote similar PCM6 system. In this case, in order to effectively use the communication line, As shown in the figure, using the multiplexer MUX-a (101)
The PCM6 system is further multiplexed and transmitted for a certain distance through the line 100, and in the PCM6 system for receiving this, the division device MUX-b (102) divides the PCM6 system into four systems again. In this way, one path 100 can transmit PCM communication for 24 communication paths as one system, which is extremely economical. Hereinafter, this system is tentatively referred to as "PCM24 system equivalent".

[Problems to be solved by the invention]

In this way, in order to connect the high-order group side (the "PCM24 system charge" side) and the low-order group side (the "PCM6 system x 4" side), it is necessary to synchronize the two, and therefore the high-order group side has been used conventionally. For the frame synchronization, an extra pulse not directly related to the information to be transmitted is added to the transmission format (1), which is generally called stuff synchronization.

However, in general, the PCM24 system, which is the main trunk line, for example, the PCM24B system specified by the Electric Power Corporation has no room for adding the above-mentioned frame synchronization pulse, and therefore the transmission formats of both cannot be matched, and these are directly connected. There was a problem that I could not do it.

This is because the conventional PCM6 system was developed for the purpose of application only in the local area and was not originally intended for connection to the existing backbone line. Nowadays, as one point of information is being concentrated, it is becoming a serious drawback.

[Means and Actions for Solving Problems]

The present invention has been made in view of the above-mentioned problems, and a signal sent via an existing PCM24 system is converted into a PCM.
In order to adapt to the communication system of 6 systems x 4 systems, the following dividing means is adopted.

That is, the frame time length of the low-order group side (“PCM6 system × 4”), the format of multi-frame and the clock are synchronized to the transmission format and clock of the higher-order group (“equivalent to the PCM24 system”) in the period and subordinately synchronized, A signal output as a serial binary code string of a high-order group is temporarily stored in a buffer storage device with a multiframe as one unit, and the data is divided into information contents of a predetermined fixed number of communication paths,
Each of them constitutes the information content of the low-order group side multiframe, and after adding a frame synchronization bit to this, each is converted into a serial binary code string synchronized with the low-order group side clock and output.

〔Example〕

Hereinafter, the present invention will be described in detail based on illustrated embodiments. To facilitate understanding, not only the PCM division method of the present invention but also the PCM multiplexing method will be described at the same time.

FIGS. 1 (a), (b), (c), and (d) show an embodiment of the present invention as a whole, and (a) is a configuration of a low-order group side frame and a multi-frame in this embodiment, (B) is a configuration of a circuit used in the method of the present invention (c), (d) is a multiplexing 1 division used in the circuit shown in (b), and is a drawing showing the details of the circuit, respectively.

Table 1 shows the specifications of the low-order group side PCM6 system used in the present invention. First, the frame structure of the PCM6 system will be described based on Table 1 and the upper part of FIG. 1 (a). One frame, which is a basic unit of information transmission, is composed of a 49-bit serial binary code string. The first 1 bit (F bit in FIG. 1 (a)) is assigned as a frame synchronization bit, and the remaining 48 bits are assigned as information words for each channel (in this case, a total of 6 channels). In other words, the information word of each call path is 8 bits per call. As will be described later, 1 in 12 frames arranged in series
Configure a multi-frame. Further, as for the voice signal in each communication path, 5 frames out of 6 frames (hence 10 frames out of 1 multi-frame) are transmitted by an 8-bit code, and 1 frame out of 6 frames (hence 2 frames out of 1 multi-frame) The signal is transmitted by the first 7 bits (1st to 7th bits), and the last 1 bit (8th bit) is responsible for tire signal transmission (hereinafter abbreviated as signal transmission).

The above is based on what is called the 1/6 bit stealing system in the PCM24B system, and as is clear from Table 1,
The clock frequency on the low-order group side (PCM6 system side) is 329 kH
z, therefore the pulse spacing within each information word is 1/329 (kH
z) = 2.55 (μs) Therefore, the time length of one frame (in other words, the audio signal sampling interval) is 2.55 (μs) × 49 (bit) = 125 (μs) Therefore, the sampling frequency is 1/125 (μs) = 8 ( Each of them is configured to be the same as that of the existing PCM24B system such as (kHz).

Further, as shown in the lower part of FIG. 1 (a) and Table 2, one multi-frame is composed of 12 frames. The length of one multi-frame is 125 (μs) × 12 (Frame) = 15 (ms). 1 as shown in the second column (F-bit column) of Table 2
Frame synchronization bit (F
Bit) has a fixed temporal pattern (1,0,0,0,1,1,0,1,
(1,1,0 game information) is attached, and this functions as information for frame synchronization. This F-bit pulse pattern is also the same as that of the PCM24B system.

Next, as mentioned above, the 1 / 6-bit stealing method was adopted for signal transmission, and the results are shown in Table 2. That is, the sixth and twelfth frames in one multi-frame are used as signal frames, and the first to seventh bits are used for voice signal transmission and the eighth bit is used for signal transmission in all speech paths in these frames. used. Hereinafter, this frame is referred to as a signal frame. As mentioned above, the signal frame insertion position in the multi-frame is the same as that of the PCM24B system.

The operation of multiplexing four systems of the PCM-6 system and dividing the system again is performed by the circuit of FIGS. 1B, 1C and 1D in units of multiframe. The frame structure on the high-order group side multiplexed by this circuit is shown in Fig. 3 on the low-order group side (PCM6).
It is shown in comparison with that of. That is, the frame on the high-order group side is composed of information words (8 bits / speech path) for 24 speech paths starting with a frame synchronization bit (F bit), and the number of bits per frame is 1 (b) +8 ( b / CH) × 24 (CH) = 193 (b) Also, the clock frequency on the high-order group side is set to 1.544MHz, and the transmission time per frame is 193 (b) × 1 / 1.544 (MHz) = 125 ( μs), which is completely in agreement with that of the low-order group side (supra).

The multi-frame structure on the high-order group side is completely the same as that of the existing PCM24B system, and is the same as that on the low-order group side except that the amount of information per frame is 193b (24 channels).

Furthermore, by performing multiplexing / division for each multi-frame, the multi-frame configuration (F-bit pulse pattern and signal frame insertion position) on the high-order group side also becomes as shown in Table 2, and this also applies to the existing PCM24B system. Exactly matches the multi-frame structure.

Next, the system synchronization format will be described. First, regarding the bit synchronization on the low-order group side (PCM6 side), in other words, on the clock synchronization of the low-order group and the high-order group, the transmission time (frame length) per frame on the low-order group side and the high-order group side is Both have 125 μs, and the amount of information contained in each frame is 193
Since they are b and 49b, it is necessary that the following relationship be established between the clock frequencies of both.

In order to prevent the slip phenomenon between the reference clocks between the high-order group and the low-order group (in other words, the phenomenon in which the relative time positions at both ends of each frame deviate) from occurring, the low-order group side kelock is fixed to the high-order group main station side clock. Need to be subordinately synchronized. FIG. 4 is a conceptual diagram for explaining the flow of the reproduction clock in this system, 103 is a clock signal (1.544 MHz continuous wave component in this case) from the received pulse train input from the main station (PCM24B terminal station device). In the clock recovery circuit to be extracted, the LC resonance circuit is used as in the usual case. Ten
Reference numeral 4 is a PLL circuit for converting the regenerated clock pulse into a clock pulse on the lower-order side (392 kHz in the case of this figure), which divides the original pulse into 1/139 (8 kHz), and further divides this by 4
A pulse train with a desired frequency is obtained by multiplying by 9. Frequency of output pulse (392kHz) due to circuit characteristics
And the phase is fully slaved to the original clock pulse (1.544MHz). The low-order group side clock thus established functions as a transmission / reception clock of the multiplexing / division device 101, and each low-order group side (PCM6 side) terminal station 105a, 105b, 105c, 105.
It is reproduced again at d and functions as a transmission / reception clock for each of these terminal stations.

Next, regarding multi-frame synchronization, a case where four PCM6 system systems are multiplexed to obtain one PCM24B system will be described. As described above, the length of each frame between the high-order group and the low-order group is set to be completely equal to each other, but the number of pulses included in one frame and the interval between adjacent pulses are the same in the high-order group and the low-order group. Totally different. Further, since the distance between the multiplexer and each PCM6 terminal station is different, there is a possibility that the phase synchronization of the frames of the respective systems input to the multiplexer may be incomplete. Furthermore, it is desirable to establish the synchronization of the high-order group and the low-order group in units of multiframes. Therefore, the serial binary code string synchronized with the clock of the low-order group side (PCM6 side) and the information word of each PCM6 system input Are stored in a buffer memory (BUFFER MEMORY) as a parallel binary code string in units of one multiframe, and a frame synchronization bit of a predetermined pattern is added to the buffer memory to convert it into a serial secondary code string synchronized with the higher-order group side clock. The means for outputting is adopted. 12 (Frame) × 6 (CH / Frame) × 8 (b) = 72 × 8 per PCM6 system of buffer memory
(B) Similar means can be taken when dividing one system of PCM24B into four systems of PCM6. On the receiving side, the F-bit pattern is decoded and each pulse to be input is accurately grasped as to what bit of what communication channel of what frame and what channel. 5 (a) and 5 (b) are conceptual diagrams showing the flow of each communication path in the case of multiplexing and division, respectively.

A circuit constructed based on the above basic concept is shown in FIGS. 1 (b), (c) and (d). The upper part of Fig. 1 (b) is a multiplex of 4 PCM6 systems input from the left side.
PCM24B1 system PCM6 that changes to PCM24B1 system and outputs it to the right, PCM24B1 system PCM6 that inputs from the right side
This is a division unit that divides into four systems and outputs, but in each case, PCM6 (1) (channel number CH1,
Only 2,3 ... 6) are shown. First, in the case of system multiplexing, 1a is a BU conversion circuit that converts a received PCM signal input as a bipolar pulse train into a unipolar pulse train and outputs it, and 2a is an output of the BU conversion circuit 1a. A frame synchronization detection circuit that detects the same frame synchronization signal (F-bit pulse train) and outputs the content of the information word to a multiplexing circuit 4 described later. Reference numeral 3a cooperates with the frame synchronization detection circuit 2a to detect the input signal. Frame number, channel number,
A reception pulse generation circuit that detects the boundary time between frames and outputs the result as a control signal to the multiplexing circuit 4, the operation of which is performed by the low-order group side clock pulse extracted by the BU conversion circuit 1a. Regulated. 5a outputs the frame number of the higher-order group side (transmission side in this case) to the multiplexing circuit 4 and other control signals, and, if necessary, outputs the frame synchronization bit (F bit) to the output of the multiplexing circuit 4. )
Is a transmission pulse generation circuit for adding. Other lower group side 3
Similar outputs are obtained for the systems (PCM6 (2), (3), (4)), and the outputs of all four systems are combined by an OR circuit (not shown) and output to the line.

FIG. 1 (c) shows an internal configuration of the multiplexing circuit 4, and 4a is a serial / parallel conversion circuit (in the figure, a serial / parallel conversion circuit for converting a serial binary code string input from the frame synchronization detection circuit 2a into a parallel binary code string.
4b is a buffer memory that temporarily stores the output of the serial / parallel conversion circuit 4a, and 4c.
Is a parallel / serial conversion circuit (indicated as P / S in the figure) that reads the data stored in the buffer storage device 4b, converts it to a serial binary code string, and outputs it to the line. 4d is a multiplexing circuit. 4 is a microprocessor unit (MPU) that controls the operation of each unit of FIG.

In the above configuration, the received signal of the PCM6 (1) system (CH1,2 ... 6) input from the left side is converted into a unipolar pulse train by the BU conversion circuit 2a, and then the frame synchronization detection circuit 2a relates to the frame synchronization. Information is extracted, and the information word is input to the serial / parallel conversion circuit 4a in the multiplexing circuit 4 as a serial binary code string of the input side clock (392kHz),
It is converted into a parallel code string. On the other hand, the received pulse generation circuit 2a
Cooperates with the frame synchronization detection circuit 3a to detect the frame number of the information data input to the multiplexing circuit 4,
The result is sent as a control signal to the serial / parallel conversion circuit 4a. The MPU 4d stores the output data (parallel two-column code string) of the serial / parallel conversion circuit 4a in a predetermined address of the buffer storage device 4b according to the frame number according to a command from the serial / parallel conversion circuit 4a. When the storage of all the information data for one multiframe is completed for the four input side systems, the parallel / serial conversion circuit 4c issues a transmission command to the MPU 4d. The MPU 4d adds an F bit to the start position of the multi-frame in response to a command from the transmission pulse generation circuit 5a, and further transfers information data about the frame numbers sequentially instructed by the circuit 5a to the parallel / serial conversion circuit 4c, where Converted to a serial binary code string synchronized with the transmitter clock (1.544MHz), and further a UB conversion circuit
It is output to the line via 6a. The above operation is 4 systems on the input side
The PCM6 (1), (2), (3), and (4) systems are serially performed, and the outputs are combined by an OR circuit and output to the line side as one PCM24B system system.

Next, the configuration and operation of the lower division unit in FIG. 1 (b) will be described. That is, PCM24B input from the right side
PCM for one system (channel number CH1,2,3, ... 23,24)
6 system A network that divides into 4 systems (PCM6 (1), (2), (3) and (4)). The names and functions of 1b, 2b, 3b, 5b and 6b in the figure are as follows. 1a, 2a, 3a, 5a, in the upper part of the figure, except that the number of channels of information to be processed is different.
Since they are the same as 6a, the description thereof will be omitted. 7 is a low-order group side clock 392kHz that is subordinately synchronized with the high-order group clock 1.544MHz.
The PLL circuit 8 for generating is a division circuit. The operation of the reception pulse generation circuit 3b is restricted by the high-order group side clock (1.544MHz) extracted in the BU converter 1b,
Further, the operation of the transmission pulse generation circuit 5b is restricted by the low-order group side clock 392 kHz output from the PLL circuit 7.
FIG. 1 (d) shows the internal circuit of the dividing circuit 8, which is 8a (S /
P) is a serial / parallel conversion circuit, 8b is a buffer memory device, and 8c (P / P
S) is a parallel / serial conversion circuit, and 8d is an MPU. The above configuration is shown only for the single-system PCM6 (1) on the low-order group side.

With the above configuration, 1 system of PCM24B system (CH1,2,3,
...... 23, 24) is input from the right side, is converted into a unipolar pulse train by the BU conversion circuit 1b, and the frame synchronization detection circuit 2b
The frame synchronization information is extracted by the division circuit 8 as information data synchronized with the higher-order group side clock (1.544 MHz).
It is input to the serial / parallel conversion circuit 8a therein. On the other hand, the reception pulse generation circuit 3b works in cooperation with the frame synchronization detection circuit 2b to detect the frame number and the communication channel number of the information data input to the serial / parallel conversion circuit 8a, and the information is used as a control signal in the conversion circuit. Send in parallel towards 8a. The serial / parallel conversion circuit 8a has a predetermined communication path (in this case, CH1,
2, ... 6) Only the information data is converted into a parallel binary code string,
Further, the MPU 8d receives the reception command signal from the conversion circuit 8a and stores the parallel binary data in a predetermined address of the buffer storage device 8b according to the frame number. When the storage of all information data for one multi-frame is completed, the MPU8d adds an F bit to the start position of the low-order group side (PCM6 (1)) by the command signal of the transmission pulse generation circuit 5b, and then the transmission pulse Information data about the frame numbers sequentially instructed by the generation circuit 5d is transferred from the buffer storage device 8b to the parallel / serial conversion circuit 8c, where the serial binary code string synchronized with the transmission side clock (392 kHz in this case) Is converted into a bipolar pulse train by the UB conversion circuit 6B, and then output to the line as a PCM6 (1) system.

As mentioned above, the transmission format of the PCM6 system is PCM24B.
Since it is set according to that of the system, the configuration of the multiplexing / splitting system between both systems is extremely simple, and there is no special processing especially for the signal bits (dial signal) inserted every 6 frames. No longer need. In a system in which the transmission format on the high-order group side is different from that on the low-order group side, it is necessary to separate the signal bits from the voice bits in the multiplexing / dividing device, store them in the temporary buffer storage device, and then take them into the transmission code string. Becomes

Also, since the transmission format of the higher-order group side system obtained by multiplexing automatically matches that of the PCM24B system, it is possible not only to directly connect this to the PCM24B terminal station but also to the higher-order group converter. It enables economical operation of the line network.

Further, in the embodiment, the case of the multiplexing / division method between the PCM6 system and the PCM24B system has been described, but the application of the present invention is not limited to this case, and the higher-order group is, for example, the PCM30 speech path system ( In the case of the European standard system), or when the low-order group is in a system other than the PCM6 system, it can be similarly applied.

〔The invention's effect〕

As described above, according to the division method of the PCM communication of the present invention, the frame time length and the multi-frame format of the low-order group side are matched with those of the high-order group side, and the clock of the low-order group side is dependent on that of the high-order group side. Information data to be synchronized and input in synchronization with the input side clock is temporarily stored in the buffer storage device in units of one multiframe, and a frame synchronization bit is added to this, and then synchronized with the transmission side clock. Since the serial binary code string (single system in case of multiplexing, multiple system in case of division) is converted and outputted, the transmission format of the higher-order group side signal obtained by the multiplexing can be set in the desired existing system. It became possible to automatically match the transmission format and directly connect to the terminal station of the existing system.

[Brief description of drawings]

1 (a), (b), (c), (d) ... The figure which shows one Example of this invention. The same (a) ... The figure which shows the frame and multi-frame of a low-order group (PCM6). Same (b) …… Multiplexing /
The figure which shows the structure of a division circuit network. (C) (d) ... Diagrams showing the internal configurations of the multiplexing and dividing circuits, respectively. Figure 2: PCM6
Figure 3 is a diagram showing the state of multiplexing and division of the four systems
Figure: Comparison of the frame configurations of the high-order group (PCM24B) and low-order group (PCM6). FIG. 4 ... A conceptual diagram showing the flow of the recovered clock. FIG. 5 (a), (b) ... Conceptual diagram showing transition of each communication path in multiplexing / division. Code table 1a, 1b ... BU conversion circuit, 2a, 2b ... frame synchronization detection circuit, 3a, 3b ... received pulse generation circuit, 4 ... multiplex circuit, 5a, 5b ... transmission pulse generation circuit, 6a, 6b ... UB conversion circuit, 7 ... PLL circuit, 8 ... Dividing circuit, 100 ... Line, 101 ... Multiplexing device, 102 ... Dividing device, 103 ... Clock recovery circuit, 104 ... … PLL circuit, 105a, b, c, d …… PCM6
Terminal equipment.

Claims (2)

[Claims] 1. A single PCM input as a serial binary code string synchronized with a clock of a general-purpose higher-order side PCM communication system.
PCM communication for dividing and outputting the information contents of the communication system to a plurality of low-order group side PCM communication systems by dividing the information contents into a plurality of series binary code strings synchronized with the low-order side clock In the system division method, the frame time length on the low-order group side and the multiframe format are set equal to those on the high-order group side, and the pulse train obtained by dividing the clock on the high-order group side is used for all low-order group PCM communication systems. As a clock of the higher order group, it is subordinately synchronized with it, and the information content input from the PCM communication system of the higher order group is 1
A parallel binary code string for each multiframe is temporarily stored in the buffer memory, and the parallel binary code string excluding the frame synchronization signal is taken out from the buffer memory for each frame, and these are predetermined. The information content of the low-order group side multi-frame is configured by dividing it into the information content of a fixed number of calls, and a frame synchronization bit having a predetermined time pattern is added to a predetermined position of each frame. A system division method in PCM communication that converts to a serial binary code string synchronized with the clock of the next group and outputs it for each multi-frame. 2. The general-purpose high-order group side PCM communication system is PCM
It is a 24B system, and the low-order group side PCM communication system is 6
A carrier telephone system for a communication path, wherein the low-order group side PCM communication system transmits 6 bits of 8-bit information word per communication path.
A PCM6 system is constructed in which 48 bits are continuously arranged for the communication path and 49 bits are added with a 1-bit frame synchronization signal at the beginning to compose 1 frame, and 1 multiframe is composed of 12 frames as in the PCM24B system. A system division method in PCM communication according to claim 1.