JPH0785026B2 - Measurement condition information generator in physical quantity measuring instrument - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a measurement condition information generator in a physical quantity measuring instrument, and more specifically, a physical quantity that receives an output of a sensor that converts a physical quantity into an electric quantity and performs measurement processing on the output. The present invention relates to a measurement condition information generator in a measuring instrument.

(B) Conventional Technology There have been remarkable technological advances in recent years, and the field of measurement is becoming more and more complicated, and there is a demand for measuring instruments to have higher performance and multiple functions. For example, in the case of multipoint measurement, generally, a plurality of types of sensors, a plurality of types of physical quantity measuring devices provided corresponding to these sensors, a data recording device or a data processing device, etc. are assembled to form a system. When performing such a measurement, if various measurement conditions are not recorded in advance in any form, when data is reproduced by a multi-channel magnetic recording / reproducing device, a so-called multi-channel data recorder or the like as the data recording device, It becomes impossible to specify the content of the reproduced data.
Therefore, conventionally, prior to the measurement, the measurement conditions such as the measurement range of each physical quantity measuring instrument, the calibration value, the cutoff frequency of the low-pass filter and the like had to be recorded by means such as writing or voice memo. In other words, since the conventional recording means has gone through a person, there is a drawback that human error such as misunderstanding, erroneous entry, forgetting to record, etc. occurs and the reliability of the measurement data is reduced. Even if no mistakes occur, the recording means requires a considerable amount of time for the recording work, which is a factor that prevents labor saving and speedup of the measurement.

On the other hand, in the above recording means, when the measurement data recorded in the data recorder is reproduced to analyze the phenomenon, the measurement condition is manually input every time even if a large computer is used as the data processing device. Must be
The input work has been a factor that impedes the high speed of the computer.

By the way, when recording the calibration value waveform in the waveform recording device, the present applicant generates a pulse waveform corresponding to the set calibration value out of the number of pulse waveforms determined in advance corresponding to various calibration values. Calibration method and its calibration in a waveform recording device, wherein a calibration value waveform having an amplitude corresponding to the calibration value is continuously generated before or after the pulse waveform, and the calibration value used can be determined by the pulse waveform. A value generator was previously proposed (see Japanese Patent Laid-Open No. Sho 60-3558). According to this, the calibration value used at the time of recording can be easily and accurately determined without recording the calibration value by human hands or voice each time, which is very convenient.

However, the output signal having the identification function of the conventional device is an analog signal to the last, and can be applied only to an analog device such as the multi-channel data recorder or a so-called pen recorder, such as the data processing device by a computer or the like. It cannot be applied to digital devices.

(C) Purpose The present invention has been made in view of the above-mentioned circumstances, and the purpose thereof is to always obtain accurately the measurement condition information corresponding to the set measurement conditions, and to introduce misunderstandings, erroneous recording, forgetting to record, etc. It is an object of the present invention to provide a measurement condition information generating device in a physical quantity measuring instrument that has no room, and therefore can significantly improve the reliability of measurement data, and can significantly reduce and speed up measurement and measurement data processing.

(D) Configuration In order to achieve the above object, the present invention relates to a physical quantity measuring instrument that receives an output of a sensor for converting a physical quantity into an electric quantity and processes the measurement, by switching circuit elements in the physical quantity measuring instrument. , A measurement condition setting circuit that can manually set measurement conditions such as calibration values and measurement condition information corresponding to the measurement condition set in this measurement condition setting circuit is output as a digital signal consisting of multiple bits A condition information output circuit, a first common signal line composed of a plurality of bits to which a plurality of the measurement condition information output circuits can be connected in parallel, and a signal line output circuit provided at one end of the first common signal line A first control circuit for controlling the measurement condition information output circuit and the measurement condition setting circuit, a second common signal line composed of a plurality of bits, and a command signal from the outside. A second control circuit is provided for controlling the signal line output circuit to connect and disconnect the second common signal line and the first common signal line and control the first control circuit. So that the measurement condition information of the physical quantity measuring device can be automatically output from the second common signal line in a time-sharing manner in a one-to-one correspondence with the measurement data signal output from the physical quantity measuring device. It is characterized by being configured in.

Hereinafter, the gist of the present invention will be described in detail based on examples.

FIG. 1 is a block diagram showing an overall configuration of a measurement condition information generating device in a physical quantity measuring unit configured by assembling a plurality of physical quantity measuring instruments according to the present invention in a mother body.

In FIG. 1, reference numeral 1 denotes a measuring bridge 1a, which is a Wheatstone bridge including a strain gauge on each side in this example.
Is a physical quantity-electric quantity converter (hereinafter referred to as a sensor), and 2 is a power supply circuit for supplying a carrier power to the measurement bridge 1a. An input amplifier circuit 3 receives the output of the sensor, and has an input impedance sufficiently higher than the output resistance of the measuring bridge 1a so as not to give a disturbance to the measuring bridge 1a. Reference numeral 4 is a calibration value generation circuit for receiving a reference voltage from the power supply circuit 2 and generating a predetermined calibration value voltage by a control means described later. Reference numeral 5 is for receiving the output of the input amplifier circuit 3 at the time of measurement and generating calibration value at the time of calibration. A carrier amplification circuit including a variable gain amplifier or the like which receives the output of the circuit 4 and is set to a predetermined gain by a control means described later, 6 is a detection circuit which detects the output of the carrier amplification circuit 5 and removes the carrier component, and 7 is Calibration value generation circuit 4 which receives the output of the detection circuit 6
And a filter circuit which is set to a predetermined cutoff frequency by a control means similar to the carrier amplifier circuit 5 and removes harmful frequency components from the detected measurement signal.
Is an output circuit including a DC amplifier (not shown) whose signal level of the measurement signal detected as described above is adjustable, and 9 is an analog output terminal connected to the output terminal of the output circuit 8. Incidentally, the portion 10 surrounded by a broken line constitutes an analog circuit system. Reference numeral 11a is a calibration value setting circuit, and 11b and 11c are a range setting circuit and a frequency setting circuit, respectively.The calibration value setting circuit 11a, the range setting circuit 11b, and the frequency setting circuit 11c have measurement condition setting circuits.
Make up 11. Also, (a-1), (a-2), (a
-3) represents an analog circuit system control signal output from each of the setting circuits 11a to 11c. 12a, 12b and 12c
Is a manual setting unit including push button switches for manually setting the calibration value setting circuit 11a, the range setting circuit 11b, and the frequency setting circuit 11c.

Reference numerals 13a, 13b and 13c are display circuits for confirming the set values of the calibration value setting circuit 11a, the range setting circuit 11b and the frequency setting circuit 11c, respectively. Reference numeral 14a is a type signal setting circuit including a digital switch for identifying the type of the sensor 1 which is an input of the analog circuit system 10, and 14b is a rotor for manually inputting a set value to the outer type signal setting circuit 14b. In FIG. 1, (b) shows the type signal output from the type signal setting circuit. Reference numerals 15a to 15c are BCD encoders for receiving the analog circuit system control signals (a-1) to (a-3) and converting them into a binary coded decimal code (BCD), and this BCD encoder.
A setting information output circuit as a measurement condition information output circuit configured by a buffer gate for switching the output of the encoder between valid and invalid, (c-1) to (c-3)
Represents a set value signal output from each of the setting information output circuits. The calibration value generating circuit 4, the carrier wave amplifying circuit 5, and the filter circuit 7 are the analog circuit system control signals (a-1) to (a-1) generated by the calibration value setting circuit 11a, the range setting circuit 11b, and the frequency setting circuit 11c, respectively. a-3) and receives the analog circuit control signals (a-1) to (a-).
The configuration is such that the operating state according to 3), that is, the measurement condition is set.

Reference numeral 16 is a type signal output circuit for switching the type signal (b) consisting of a plurality of bits from the type signal setting circuit 14a to valid or invalid, and (b ') is a type signal output from the type signal output circuit 16. is there. Reference numeral 17a is a monitor request signal circuit for generating a monitor request signal (d), and 17b is a monitor switch for supplying an input to the monitor request signal circuit 17a.

Reference numeral 18 denotes a card bus line composed of 4 bits as a first common signal line connected in parallel to the output terminals of the setting information output circuits 15a to 15c and the type signal output circuit 16.
Is a signal line output circuit including a buffer gate having one end of the card bus line 18 connected to the input end.

Reference numeral 20 is for remotely setting the calibration value setting circuit 11a, range setting circuit 11b, and frequency circuit 11c, or for enabling or disabling respective outputs to the setting information output circuits 15a to 15c and the type signal output circuit 16. It is an output control circuit as a first control circuit for switching. In Figure 1,
(E) is a setting pulse signal output to each circuit of the measurement condition setting circuit 11, and (f) is each setting information output circuit 15a to 1
Output ON-OFF signal output to 5c. 21a is an input bus line to which the output ends of the signal line output circuit 19 are connected in parallel, 21b is an output bus line to which the input ends of the output control circuit 20 are connected in parallel, and the input bus line 21a and the output bus line 21b constitutes a second common signal line. Reference numeral 22 is a channel control circuit which connects one end of the input bus line 21a and one end of the output bus line 21b and controls the signal line output circuit 19 and the output control circuit 20, and (g) shows the signal line output circuit 19 and the output. A channel ON-OFF signal given to the control circuit 20, 23 is a bidirectional data bus line connected to the channel control circuit 22 for exchanging data with the outside, and (h) is an input or output from the data bus line 23. Data signal, 24 is also a channel control circuit
22 is an address bus line for transmitting a control signal from the outside, (i) is this address bus line 24
To the channel control circuit 22, (j) is a gate signal externally applied to the gate terminal 25, 26a is a unit signal setting circuit including a one-digit digital switch, 26b is the set value (unit number) in this unit signal setting circuit 26a
A rotor for inputting the signal, 27 is a unit signal setting circuit 26
A unit signal output circuit that receives the output of a and switches this output between valid and invalid, 28 is a unit control input terminal connected to the unit signal output circuit, and (k) is an enable that is externally applied to this unit control input terminal. It is a signal. The output terminal of the unit signal output circuit 27 is connected in parallel to the data bus line 23.

Note that (l) is the unit signal output from the unit signal setting circuit 26a, and (l ') has the same content as the unit signal (l), but since it is the output signal from the unit signal output circuit 27, it has the same name. The call signal symbol will have a ‘(dash). Further, the data signal (k), the address signal (i), the gate signal (j) and the enable signal (k) constitute a command signal given from the outside,
On the other hand, the command signals (h) to (k) are composed of a read command signal and a remote setting command signal, and the read command signal further includes a measurement condition read command signal including the reading of the type signal (b ') and a unit signal ( l ') for reading a unit read command signal.

On the other hand, 29 is a measurement value output switching circuit that receives the output of the monitor request signal circuit 17a and selects one of the outputs of the plurality of analog circuit systems 10, and 30 receives the output of the measurement value switching circuit 29 and outputs the measurement value. It is a measured value display unit composed of a digital display equipped with an A / D converter for displaying. In FIG. 1, a portion 31 surrounded by a one-dot chain line constitutes a monitor portion as a mother body, and the monitor portion 31 and other portions excluding the sensor 1 constitute a card 32 as a physical quantity measuring instrument. . A unit 33 is composed of one or a plurality of cards 32 and one monitor unit 31. In this embodiment,
Unit 33 with 16 cards 32 and 1 monitor 31
Are configured. Therefore, the measured value output switching circuit 29 is
The output of the analog circuit system 10 is received, and the output of the 16 monitor request signal circuits 17a is received.

FIG. 2 shows a plurality of units 33 (up to 10 in this embodiment).
It is a conceptual diagram in the case of being configured by using each piece) and applied to a multipoint measurement system.

In the figure, 34 is a first unit, 35 is a second unit, and in the drawing, an intermediate unit is omitted and 36 is a final tenth unit, and 37 is each of the first to tenth units.
A core data bus line in which each data bus line 23 of 34 to 36 is connected in parallel, a reference numeral 38 is a core address bus line in which the address bus line 24 of each unit 34 to 36 is connected in parallel, and a reference numeral 39 is similarly in each unit 34. 36 is a basic control signal line representatively represented by one control signal line connected to the gate terminals 25 and unit control input terminals 28 (see FIG. 1). In FIG. 2, (m) is a backbone data bus line
A basic data signal input or output to 37, (n) is a basic address signal given to a basic address bus line 38, and (p) is a basic control signal given to a basic control signal line 39.

Reference numerals 40 and 41 denote the monitor portions of the first unit 34 and the second unit 35, respectively.
Is the monitor unit of the tenth unit 36, which is the last unit, and the contents thereof are substantially the same as the monitor unit 31 shown in the first illustration. 43 to 45 are 16 sensors of the first unit 34, 46
˜48 are 16 cards of the first unit 34, 49˜51 are analog output terminals of each of the above cards 46˜48, and are sensors 43˜45, cards 46˜48, analog output terminals 49˜51.
Are substantially the same as the sensor 1, the card 32, and the analog output terminal 9 shown in FIG. And the sensor
The first channel 52, which is the first conceptual channel having 43, the card 46, and the analog output terminal 49.
Are configured. Similarly, the sensor 44, the card 47, and the analog output terminal 50 constitute the second channel 53, and the sensor 45, the card 48, and the analog output terminal 51 constitute the final channel, that is, the 16th channel 54. . The channel concept of the first channel 52, the second channel 53, and the final 16th channel 54 is that each unit 34
~ 36 are common. Therefore, in the same way, 55
~ 57 are sensors, 58-60 are cards, 61-63 are analog output terminals, and the sensors 55-57, cards 58-60, analog output terminals 61-63 have the first channel of the second unit 35.
52 to 16th channel 54 is configured. In addition, 64-66
Is a sensor, 67 to 69 are cards, and 70 to 72 are analog output terminals. The sensors 64 to 65, the cards 67 to 69, and the analog output terminals 70 to 72 have the first channel 52 to the 16th channel of the tenth unit 36. It constitutes channel 54.

FIG. 3 is a circuit diagram showing a specific circuit example of the measurement condition setting circuit 11. However, although the measurement condition setting circuit 11 is composed of the calibration value setting circuit 11a, the range setting circuit 11b, and the frequency setting circuit 11c as described above, all of the above three circuits have substantially the same configuration, and the analog circuit system Control signal (a-
Since only 1) to (a-3) differ in the number of bits, the calibration value setting circuit 11a having the largest number of bits is shown as a representative thereof. Note that FIG. 3 also includes the display circuit 13a as a representative of the display circuits 13a to 13c and a part of the setting information output circuit 15a as a representative of part of the setting information output circuits 15a to 15c.

In FIG. 3, 73 is a manual input terminal to which a pulse signal for manual setting is input, 74 is a remote input terminal to which the setting pulse signal (e) for remote operation is input, and 75 is a reset signal described later. This is a reset terminal to be input. 76
Is a positive logic OR gate having two inputs, the first input terminal of which is connected to the manual input terminal 73 and the second input terminal of which is connected to the remote input terminal 74. Reference numerals 77 to 83 are first to seventh D-type flip-flops (hereinafter, this D-type flip-flop is abbreviated as “D-FF”), and each clock input terminal T is an output terminal of the OR gate 76. Connected to the preset input terminal of the first D-FF77 and the second
The reset input terminals of the D-FF78 to the seventh D-FF83 are all connected in parallel to the reset terminal 75, and the non-inverting output terminal Q of the first D-FF77 is connected to the data input terminal D of the second D-FF78. Similarly, if n is an integer of 2 to 6 and the nth D-FF is expressed as D-FF (n), the non-inverting output terminal Q of D-FF (n) is D-FF (n + 1). Data input terminal D
It is connected to the.

Reference numeral 84 is a positive logic NOR gate having 7 inputs. The first to seventh input terminals are connected to the non-inverting output terminals Q of the first D-FF77 to the seventh D-FF83, respectively, and the NOR gate 84 has The output terminal is connected to the data input terminal D of the first D-FF77.

Reference numeral 85 denotes a display, which is a concrete circuitization of the display circuit 13a shown in FIG. 86a to 86g are fixed resistors having substantially the same resistance value, and 87a to 87g are light emitting diodes for display, and the set values are 50με, 100με, 200με and 500μ, respectively.
One of ε, 1000 με, 2000 με, and 5000 με is displayed by lighting. 88a to 88g are inverters for driving the light emitting diodes 87a to 87g. One ends of the fixed resistors 86a to 86g are all connected in parallel and are connected to a power source of + 5V, and the other ends are respectively connected to the anode side of the display light emitting diodes 87a to 87g in a one-to-one manner. Inverter 88a on the cathode side
~ 88g output terminal and one-to-one connection, inverter 88a ~
88g input terminals are 1st D-FF77 to 7th D-F
It is connected to the non-inverting output terminal Q of F83 in a one-to-one relationship. 89
˜95 are analog circuit control output terminals (hereinafter, simply referred to as output terminals), which are the first D-FF77 to the seventh D, respectively.
-One-to-one connection with the non-inverting output terminal Q of FF83.
In the following a first output signal of the D-FF77~ seventh D-FF 83 simply with symbols T ₁ through T ₇ are denoted. Therefore, the analog circuit system control signal (a-1) is composed of T _{1 to} T ₇ . 96 is a positive logic BCD encoder for both input and output that converts decimal input to BCD, I _{0 to} I ₁₅ are decimal input terminals,
A to D are BCD output terminals consisting of 4 bits and BCD output terminal A
Corresponds to the least significant bit (LSB), and the BCD output terminal D corresponds to the most significant bit (MSB). The decimal input terminals I _{1 to} I ₇ are the first
Of the D-FF77 to the seventh D-FF83 are connected to the non-inverting output terminal Q in a one-to-one manner, and the decimal input terminals I ₀ and I _{8 to} I ₁₅ are both grounded. The BCD encoder 96 is a part of the setting information output circuit 15a which is a measurement condition information output circuit.

FIG. 4 is a circuit diagram showing the configurations of the card bus line 18, the input / output bus lines 21a and 21b, and their peripheral circuits. In FIG. 4, 97, 98 and 99 are respectively calibration value blocks corresponding to the calibration value setting circuit 11a, the range setting circuit 11b and the frequency setting circuit 11c shown in FIG.
A range block and a frequency block. However,
The reset terminal 7 of the measurement condition setting circuit 11 shown in FIG.
5, the manual input terminal 73, the display 85, the output terminal, etc. are omitted. In these blocks 97 to 99, PI is a set pulse input terminal connected to the remote input terminal 74 (third shown), and A to D are the same as the BCD output terminals A to D of the BCD encoder 96. Reference numerals 100 to 119 are so-called 3-state buffer gates having a high impedance state at the output, and are configured so that their control inputs are in an operating state at H level and are in a high impedance state at L level. The input terminals of the buffer gates 100 to 103, 104 to 107, 108 to 111 are respectively the calibration value block 97 and the range block 9
8. Connected to the BCD output terminals A to D of the frequency block 99 on a one-to-one basis. BCD encoder 96 in calibration value block 97
And the buffer gates 100 to 103 configure the setting information output circuit 15a of the calibration value, the BCD encoder 96 in the range block 98 and the buffer gates 104 to 107 configure the range setting information output circuit 15b, and the frequency block 99 in the frequency block 99. The BCD encoder 96 and the buffer gates 108 to 111 constitute a frequency setting information output circuit 15c. The buffer gates 112 to 115 form a type signal output circuit 16, and the buffer gates 116 to 119 form a signal line output circuit 19. 120 to 123 are bit signal lines corresponding to each bit forming the card bus line 18, and the bit signal line 120 is LSB,
Bit signal line 123 corresponds to MSB. Buffer gate
The input terminals of 116 to 119 are respectively connected to the bit signal lines 120 to 123 on a one-to-one basis, and the bit signal lines 120 to 123 are respectively buffer gates 100 to 103, 104 to 107, 108 to 111, 112 to 11.
5 output terminals are connected in parallel one by one.
The output signals of the buffer gates 100 to 103 are set value signals (c-1) of the calibration value, and the output signals of the buffer gates 104 to 107 are set value signals (c-2) of the range, and the buffer gates 108 to 111. The output signals of (3) and (3) respectively constitute the frequency setting value signal (c-3).

124-127, 128-131 are input bus lines 21a,
Of the bit signal lines forming the output bus line 21b, the bit signal lines 124 and 128 correspond to LSB, and the bit signal lines 127 and 131 correspond to MSB. 132 is a channel ON-OFF signal input terminal, 13
3-136 are AND gates of positive logic having two inputs, 137 is a binary-octal decoder having positive logic for both input and output. In this decoder 137, A to D are input terminals, and input terminal A is LS.
B, input terminal D corresponds to MSB, and Y ₀ to Y ₇ are first to first
Eighth output terminal. The decoder 137 and the AND gate 13
The output control circuit 20 is composed of 3-136. The output terminals of the buffer gates 116 to 119 are connected to the bit signal lines 124 to 127 of the input bus line 21a in a one-to-one relationship, and all the control input terminals of the buffer gates 116 to 119 and the first gates of the AND gates 133 to 136 are connected. All of the 2 input terminals are connected in parallel and connected to the channel ON-OFF signal input terminal 132,
The first input terminals of the AND gates 133 to 136 are respectively connected to the bit signal lines 128 to 131 in a one-to-one relationship, and the output terminals of the AND gates 133 to 136 are input terminals A to D of the decoder 137.
And one-to-one connection with. In the decoder 137, when all the input terminals are at the L level, that is, when the code signal of 0H in hexadecimal notation is given, only the signal of the first output terminal Y ₀ becomes the H level, and the same applies to the input 1H and the second output. Terminal Y ₁ , input 7H
However, only the signal of the eighth output terminal Y ₇ is set to the H level, but nothing is connected to the first output terminal Y ₀ . The second output terminal Y ₁ is connected in parallel with the control input terminals of the buffer gates 100 to 103, the third output terminal Y ₂ is connected in parallel with the control input terminals of the buffer gates 104 to 107, and the fourth Output terminal Y ₃ is buffer gate 108-111
Is connected the control input terminals of the parallel, the output terminal Y ₄ of the 5 are connected in parallel with the control input terminal of the buffer gate 112-115. The sixth to eighth output terminals Y _{5 to} Y ₇ are respectively provided with a calibration value block 97, a range block 98, and a frequency block.
99 setting Pulse input terminal Connected to PI. And
The signals output from the output terminals Y _{1 to} Y _{4 of the} decoder 137 form an output ON-OFF signal (f), and the output terminals Y _{5 to} Y ₇
The setting pulse signal (e) is constituted by the output signal of. 138 is a digital switch as the type signal setting circuit 14a, 139 is a dial as the rotor 14b for inputting a set value (6H to FH or 0H to FH in hexadecimal notation), 140 is a set value visually It is a scale for doing. In the digital switch 138, b _{0 to} b ₃ are output terminals that output a binary code signal as a type signal, P is a power supply terminal, COM is a common terminal, output terminal b ₀ is LSB, and output terminal b ₃ is
Corresponding to MSB, power supply terminal P is connected to + 5V, common terminal C
OM is grounded, and the output terminals b _{0 to} b ₃ are connected to the input terminals of the buffer gates 112 to 115, respectively. The output signals from the output terminals b _{0 to} b _{3 of} the digital switch 138 constitute the type signal (b).

The output signals of the buffer gates 112 to 115 are represented by the same name as the type signal (b ').

FIG. 5 is a circuit diagram showing a specific circuit example of the monitor unit 31 excluding the measured value output switching circuit 29 and the measured value display unit 30.

In FIG. 5, reference numeral 141 denotes binary −1, which is a positive logic for both input and output.
In this hexadecimal decoder 141, A to D are input terminals and Y _{0 to} Y ₁₅ are output terminals. Input terminal A
Corresponds to the LSB, and the input terminal D corresponds to the MSB. Further, in the decoder 141, when a signal whose input terminals are all L levels, that is, a code signal of 0H in hexadecimal notation is given, only the signal of the output terminal Y ₀ becomes H level, and 1H as an input.
When the code signal of is given, only the signal of the output terminal Y ₁ becomes H
It becomes a level, and in the same manner, when FH is applied as an input, only the signal at the output terminal Y ₁₅ becomes an H level. Then, the output terminals Y _{0 to} Y _{15 of the} decoder 141
The channel ON-OFF signal (g) is composed of the output signal of. 142 and 143 are 4-bit data latches. D _{0 to} D ₃ are input terminals, Q _{0 to} Q ₃ are output terminals,
LT is a latch input terminal. Input terminal D ₀ , output terminal
Both Q ₀ correspond to the LSB, the input terminal D ₃ and the output terminal Q ₃ correspond to the MSB, and the input data is latched by the rising edge of the latch input terminal becoming H level.
144 is an inverter, 145 is an AND gate with two inputs, 146
Numerals 153 to 153 are so-called 3-state buffer gates having an output in a high impedance state, and are configured to be in an operating state when the control input terminal thereof becomes H level and to be in a high impedance state at L level. still,
(Q) is an output signal of the inverter 144 and is called a write signal. 154 is a digital switch as the unit signal setting circuit 26a, 155 is a dial as the setting input rotor 26b, and 156 is a scale for confirming the set value. The digital switch 154 has substantially the same configuration as the digital switch 138 described above, except that the setting input is limited to 0-9. Therefore, the output signals of the output terminals b _{0 to} b ₃ are limited to 0H to 9H in hexadecimal notation. The output signals from the output terminals b _{0 to} b _{3 of} the digital switch 154 form the unit signal (1), and the output signals of the buffer gates 150 to 153 form the unit signal (1 ′). 157-161
Are channel ON-OFF signal output terminals, which are connected to the output terminals Y _{0 to} Y ₁₅ of the decoder 141 in a one-to-one relationship. 16
Numerals 2 to 165 are address input terminals, which are connected to the input terminals A to D of the decoder 141 in a one-to-one relationship via the signal lines forming the address bus line 24 (FIG. 1). The address input terminal 162 corresponds to the LSB and the address input terminal 165 corresponds to the MSB. Also, address input terminal
Address signals (i) with signals applied to 162 to 165
Are configured. Reference numerals 166 to 169 are bit signal lines corresponding to the respective bits forming the data bus line 23, and 170 is a data bus terminal connected to one ends of these bit signal lines 166 to 169 in a one-to-one relationship. The data bus terminal 170 and the address input terminals 162 to 165 are connected to an external device. The bit signal line 166 is LSB and the bit signal line 169 is M.
It corresponds to SB. The signal input to or output from the bit signal lines 166 to 169 is the data signal (h). The output terminals Q _{0 to} Q ₃ of the data latch 142 are connected to the bit signal lines 128 to 131 (shown in FIG. 4) of the output bus line 21b and 1 respectively.
Input terminal D of address latch 143 connected to pair 1 in the same way
_{0 to} D ₃ are bit signal lines 124 to 127 of the input bus line 21a.
(4th illustration) and 1: 1 connection. On the other hand, the input terminals D _{0 to} D _{3 of} the data latch 142 and the buffer gates 146 to 149.
And the output terminals of the buffer gates 150 to 153 are the bit signal lines 166 to 169 and 1 of the data bus line 23, respectively.
It is connected in parallel to pair 1. The output terminals Q _{0 to} Q ₃ of the data latch 143 are connected to the input terminals of the buffer gates 146 to 149 on a one-to-one basis. Output terminal b of digital switch 154
_{0 to} b ₃ are connected to the input terminals of the buffer gates 150 to 153, respectively. 25 and 28 are the gate terminal and the unit control input terminal already described, respectively, and the gate terminal 25 is the latch input terminal LT of the data latch 143 and all the control input terminals of the buffer gates 146 to 149 and the inverter.
The unit control input terminal 28 is connected to the first input terminal of the AND gate 145. The output terminals of the AND gate 145 are buffer gates 150 to 153.
It is connected in parallel with all of the control input terminals. The output terminal of the inverter 144 is connected to the second input terminal of the AND gate 145 and the latch input terminal LT of the data latch 142, respectively. Channel ON-OFF signal output terminals 157-16
1 is the first channel 52 to the 16th channel 54 (Fig. 2)
The channel 32 is connected to the channel ON-OFF input terminal 132 (shown in FIG. 4) of FIG.
Is shown as a representative of each channel, the channel ON-OFF input terminal 132 (shown in the same figure 4)
The ON-OFF output terminal 157 is connected. Also, a binary-hexadecimal decoder 141, data latches 142 and 143, an inverter 14
4. The channel control circuit 22 is composed of the buffer gates 146 to 149, and the AND gate 145 and the buffer gates 150 to 153.
And constitutes a unit signal output circuit 27.

FIG. 6 is a circuit diagram showing a specific configuration example of the calibration value generation circuit 4. In FIG. 6, 171 is a transformer for generating a calibration value voltage, 172 and 172 'are primary side input terminals of this transformer 171, respectively, which are connected to the power supply circuit 2 shown in FIG. Has become. 173 to 179 are analog switches, 180 to 187 are divided output terminals obtained by dividing the output of the secondary winding of the transformer 171 through a buffer 187 ′ with this output terminal divided by resistors having a predetermined resistance value,
188 is an output terminal of the calibration value generating circuit 4, and 189 to 195 are analog circuit system control input terminals. Analog switch 173-1
The signal input terminals of 79 are connected to the split output terminals 181-187, and the signal output terminals of the analog switches 173-179 are all connected in parallel and the output terminal 18
Connected to 8. In addition, analog switches 173--17
9 control input terminals are analog circuit control input terminals 189-
It is connected one-to-one with 195.

The tap 180 is grounded. Further, the analog switches 173 to 179 are configured to be in a conductive state when the control input terminal thereof becomes H level and to be in an OFF state when they become L level. The analog circuit system control input terminals 189 to 195 are connected to the output terminals 89 to 95 shown in FIG.
They are connected to each other. Also, the split output terminals 181-187 are respectively 50 με, 200 με, 500 με, 1000 με, 2000 με, 500
It is provided to generate a calibration value voltage corresponding to 0 με.

FIG. 7 is a circuit diagram showing a specific configuration example of a variable gain amplifier forming a part of a carrier wave amplifying circuit. In FIG. 7, 196 is a measurement value input terminal, 197 is a calibration value input terminal, and these measurement value input terminal 196 and calibration value input terminal 197 are the output terminal of the input amplifier circuit and the output terminal 188 of the calibration value generating circuit 4. Respectively connected to. 198 is a changeover switch for switching between measurement and calibration.
Reference numeral 98a is a calibration side contact connected to the calibration input terminal 197, 198b is a measurement side contact connected to the measurement input terminal 196, and 198c is a common contact. Reference numerals 199 to 204 denote analog switches, which have substantially the same configuration as the above analog switches 173 to 179.
205 to 210 are R / 100, R / 200, R / 500, R / 1000, R / 2000,
Reference numeral 211 is an input resistance having a resistance value of R, 211 is a feedback resistance having a resistance value of R, 212 is an operational amplifier, and 213 is an output terminal of the variable gain amplifier. The signal input terminals of the analog switches 199 to 203 are all connected in parallel and the common contact 19
8c, the signal output terminals of the analog switches 199 to 204 are connected to the one ends of the input resistors 205 to 210 in a one-to-one manner, and the other ends of the input resistors 205 to 210 are all connected in parallel and the operational amplifier 212 is connected. The feedback resistor 211 is connected between the output terminal of the operational amplifier 212 and the inverting input terminal, and the output terminal of the operational amplifier 212 is connected to the output terminal 213 of the variable gain amplifier. The non-inverting input terminal of the operational amplifier 212 and the signal input terminal of the analog switch 204 are grounded. Reference numerals 214 to 219 denote analog circuit system control input terminals, which are connected to the control input terminals of the analog switches 199 to 204, respectively. Input resistance 205 to 21
0, the feedback resistor 211, and the operational amplifier 212 constitute a variable gain amplifier which is an inverting amplifier. The analog circuit control input terminals 214 to 219 are connected to the range setting circuit 11b (first
(Not shown) is connected to the analog circuit system control output terminals (that is, corresponding to the output terminals 89 to 95 shown in FIG. 3) in FIG. 3), but the circuit shown in FIG. Similarly, the output terminal 95, in other words, the seventh D
Only the circuit portion related to the output signal T ₇ of -FF83 has a configuration in which have been removed are different.

FIG. 8 shows the manual setting section of the measurement condition setting circuit 11 (FIG. 1).
It is a concrete circuit diagram of 12a-12c. In FIG. 8, 22
0 is a pull-up resistor, 221 is a delay circuit consisting of a resistor and a capacitor, 222 is a push button switch, 223 is an inverter, and 224 is an output terminal. One end of the pull-up resistor is
It is connected to a + 5V power supply, and the other end is connected to one end of a push button switch 222 and an input terminal of an inverter 223 via a delay circuit 221. Push button switch 222
The other end is grounded, and the output terminal 224 is connected to the output terminal of the inverter 223. The above circuit is generally called a chattering prevention circuit, and is configured to output a positive pulse from the output terminal 224 from which chattering generated from the push button switch 222 which is a mechanical contact is removed. . However, the pulse width of the positive pulse is approximately equal to the time during which the push button switch 222 is pressed. The output terminal 224 is the manual input terminal 7 shown in FIG.
Connected to 3.

FIG. 9 shows a reset signal generating circuit. In FIG. 9, 225 is a + 5V power source, 226 is a power switch, 227 is a time constant circuit, 228 is a discharge circuit, and 229 is an output terminal. Power supply 22
The negative side of 5 is grounded, the positive side is connected to one end of the power switch 226, and the other end of this power switch 226 is connected to the time constant circuit 2
It is connected to the output terminal 229 via 27 and the discharge circuit 228. This circuit is a so-called power-on reset circuit. Even after the power switch 226 is turned on, the output terminal 229 holds the zero potential for about 200 μs, for example. The reset pulse is output. And the output terminal 22
9 is connected to the reset terminal 75 shown in FIG.
(Note that the explanation of the operation of the circuits shown in FIGS. 8 and 9 is omitted).

Next, the operation of this embodiment configured as described above will be described.

First, the overall schematic operation will be described with reference to FIG.
By operating the manual setting units 12a to 12c, the measurement condition setting circuit 11, that is, each of the calibration value setting circuit 11a, the range setting circuit 11b, and the frequency setting circuit 11c is confirmed while being confirmed by the display of each display circuit 13a to 13c. Set to the state (measurement conditions).
The analog circuit system control signals (a-1) to (a-3) output from the measurement condition setting circuit 11 are input to the calibration value generating circuit 4, the carrier wave amplifying circuit 5, and the filter circuit 7, respectively. Analog circuit system by switching the circuit elements of the analog circuit according to the above measurement conditions.
Setting 10 measurement conditions, that is, operating states, and setting information output circuits 15a to 1 as measurement condition information output circuits
5c, and the set value signals (c-1) to (c-1) as the measurement condition information are input to the respective setting information output circuits 15a to 15c.
Is converted into (c-3). The type signal (b) is output from the type signal setting circuit 14a by the operation of the rotor 14b and input to the type signal output circuit 16. Here, when the monitor switch 17b is turned on, the monitor request signal (d) from the monitor request signal circuit 17a is input to the measurement value output switching circuit 29, and the analog circuit of the channel (the first channel in the case of the first illustration). The output signal of the system 10 is selected and displayed on the measured value display section 30.

On the other hand, in the monitor unit 31, when the unit signal setting circuit 26a is set by operating the rotor 26b, the unit signal (1) is output from the unit signal setting circuit 26a and is input to the unit signal output circuit 27.

Now, next, the above-mentioned command signal is transmitted to the address bus line 24,
The measurement condition information including the type signal (b ') by being applied to the gate terminal 25 and the unit control input terminal 28,
Alternatively, the unit signal (l ') can be read and the measurement condition of the analog circuit system can be set from the outside.

First, when a unit read command signal is applied as the command signal, the unit signal output circuit 27 operates to send the unit signal (l ') onto the data bus line 23, and the unit signal (l') is transferred to the data. It can be read from the outside as a signal (h).

Next, when the measurement condition read command signal is applied, the channel control circuit 22 is activated by the address signal (i) and the gate signal (j), and the output control circuit 20 of the channel is activated by the channel ON-OFF signal (g). And the signal line output circuit 19 operates. By the data signal (h) transmitted through the output bus line 21b, the output control circuit 20 causes the setting information output circuits 15a to 15c corresponding to the data signal (h).
, Or an output ON-OFF signal (f) is output to any one of the type signal output circuits 16. Then, for example, when the setting information output circuit 15a is designated by the output ON-OFF signal (f), the setting value signal (c-1) of the calibration value is sent to the card bus line 18. Card bus line 18
The set value signal (c-1) transmitted to the channel control circuit 22 is transferred to the channel control circuit 22 via the signal line output circuit 19 and the input bus line 21a, and the gate signal (j) is switched to the H level here. The channel controller 22 sends the set value signal (c-1) as a data signal (h) onto the data bus line 23. After that, the data signal (h), which is a component of the command signal, is updated, and the same operation as above is repeated to set value signals (c-2), (c).
-3) or the type signal (b ') can be read.
Then, next, when the remote setting command signal is given,
The channel control circuit 22 operates by the gate signal (j) and the address signal (i) to output the channel ON-OFF signal (g) to the channel corresponding to the address signal (i), and the channel ON- Upon receiving the OFF signal (g), the signal line output circuit 19 and the output control circuit 20 of the channel are activated, while the gate signal (j) causes the data signal (h) to be output via the channel control circuit 22 to the output bus line 21b. Dispatched on. Upon receiving the data signal (h) on the output bus line 21b, the output control circuit 20 responds to the data signal (h) by the calibration value setting circuit 11a and the range setting circuit 1
The setting pulse signal (e) is output to any one of 1b and the frequency setting circuit 11c. This setting pulse signal (e)
The measurement condition setting circuit 11 that has received the information updates one measurement condition (setting state). That is, for example, if the setting condition before the measurement condition setting circuit 11 is the calibration value setting circuit 11a and the setting pulse signal (e) is 50 με, the setting condition is set when the setting pulse signal (e) is received. Is 1
Is updated to 100 με. After that, the above operation may be repeated until the desired state is reached. The operation according to the remote setting command signal is referred to as a remote setting operation, and hereinafter, the operations according to the measurement condition reading command signal and the unit reading command signal are also referred to as a measurement condition reading operation and a unit reading operation, respectively. The above is the description of the operation in the unit 33.

Now, in the multipoint measurement system shown in FIG. 2, the backbone data bus 37, backbone address bus 38, backbone control signal line 39
Predetermined operations are performed by applying a basic data signal (m), a basic address signal (n), and a basic control signal (p) to each of them. That is, the basic control signal (p)
Any one of the first unit 34 to the tenth unit 36 is designated (selected) by, and thereafter, the operation in the unit 33 (FIG. 1) described above is performed.

Incidentally, the basic data signal (m) and the basic address signal (n) given from the outside are conceptual, and the data signal (h) and the address signal (i) in the unit 33 are referred to respectively.
The contents of the data signal (h) as an output are also the same as those of the basic data signal (m) as an output.

As described above, the first to tenth units 34 to 36, the first channel to the sixteenth channel 52 to each of these units are
For 54, any unit, any channel, any measurement condition setting information can be obtained, and the setting condition can be set (changed) from the outside. That is, the analog output terminals 49 to 51, 61 to 6 of the above units and channels
Analog output (measurement value signal) output to 3,70 to 72 and 1
The measurement condition setting information corresponding to the pair 1 is obtained.

Next, detailed operation will be described with reference to the circuit diagrams of FIG. In FIG. 3, since the reset signal from the reset signal generation circuit (shown in FIG. 9) is applied to the reset terminal 75 when the power is turned on, the output signal T _{1 of} the first D-FF 77 is
Is at the H level, and the output signals T _{2 to} T ₇ of the second D-FF 78 to the seventh D-FF 83 are at the L level. Therefore, an H-level signal is applied to the data input terminal D of the second D-FF78, and the third D-FF79 to the seventh D-FF83 are applied.
An L level signal is applied to the data input terminal D of. Further, since the NOR gate 84 receives the H level signal T ₁ , the L level signal is input to the data input terminal D of the first D-FF 77. Then, since the output of the inverter 88a becomes L level by T ₁ , the display light emitting diode 87a is turned on, and it can be confirmed that the initial state is set to 50 με. Also, T ₁ is the BCD encoder 9
6 is input to the input terminal I ₁ , and the input terminals I _{2 to} I ₉ and I ₀ of the BCD encoder 96 are at L level, so that the output terminal A to
The signal of D is a signal of each level of H, L, L, L. That is, the signals from the output terminals A to D are expressed in hexadecimal notation.
It is 1H. Therefore, when the positive pulse signal is applied again to the manual input terminal 73 or the remote input terminal 74, this positive pulse signal is applied to the T terminal of D-FF77 to 83 through the OR gate 76, and the D-FF77 to 83 are positive. The signal applied to each data input terminal D at this time is taken in using the pulse signal as a clock signal, and the signal is output to each non-inverting output terminal Q and held. As a result, T ₁ becomes L, T ₂ becomes H, and T _{3 to} T ₇ become L level. Since the H level signal of T ₂ is inputted to the NOR gate 84 as though T ₁ is changed to T ₂ , its output holds the L level. Then, the output of the inverter 88b is set to L by the above T ₂ .
Since it becomes the level, it can be confirmed that the light emitting diode 87b is turned on, the light emitting diode 87a is turned off by T ₁ , and is set to 100 με.

Further, the above T ₂ is applied to the input terminal I ₂ of the BCD encoder, and the signals applied to the other input terminals I _{3 to} I ₁₅ , I ₀ and i ₁ are at L level, so that the output terminals A to D thereof are L, H,
L, L, level signals, that is, 2H in hexadecimal notation are output. After that, in the same way, from T ₃ that the positive pulse signal is applied to the manual input terminal 73 or the remote input terminal 74.
The H-level signal advances toward T ₇ , and T ₇ or the seventh D
The output of -FF83 becomes H level, With additional said positive pulse signal is applied to the manual input terminal 73 or the remote input terminal 74, T ₇ is changed from H level to L level T ₁ through T ₇ Are all at the L level, the output of the NOR gate 84 becomes the H level, and this H level signal is sent to the first D-FF77.
Is taken in from the data input terminal D, and as a result, T ₁ becomes H level, which means that the H level signal that has proceeded from T ₁ to T ₇ has completed a cycle. Then, in the display 85, the light emitting diode 87a lights up to indicate that the set value is 50 με, and the output signal of the BCD encoder 96 becomes 1H. Further, as far as manual setting is concerned, the positive pulse signal is inputted to the manual input terminal 73 every time the push button switch 222 shown in FIG. 8 is pressed once, and the output states of the first to seventh D-FF 77 to 83 are outputted. Goes one step.

Next, the operation of the calibration value generating circuit shown in FIG. 6 and the variable gain amplifier shown in FIG. 7 will be described.

In FIG. 6, analog circuit system control input terminals 189 to 195
The signals T _{1 to} T ₇ are input to the respective switches, the corresponding analog switches 173 to 179 are turned on, and the calibration value voltages corresponding to the respective switches are output from the output terminal 188. For example, when T ₁ goes high, analog switch 173 turns on and 50μ
A calibration value voltage corresponding to ε is output. The same applies to T _{2 to} T ₇ .

Next, referring to FIG. 7, the analog circuit control input terminal 214
When the output signals T _{1 to} T ₆ are input to ~ 219, the corresponding analog switches 199 to 204 are turned on. For example, when T ₁ is at the H level, the analog switch 199 is turned on and the analog switches 199 to 204 are turned on. Input resistor 205 connected to 199
Has a resistance value of R / 100, while the feedback resistance 211 has a resistance value of R, the amplification degree or gain at this time is R ÷ (R / 10
0) = 100, that is, 100 times, and the variable gain amplifier is 1
The lens is set to 00x. Hereinafter, the same applies to T _{2 to} T ₅ , and the ranges are set to 200 times, 500 times, 1000 times, and 2000 times, respectively. When the output signal T ₆ becomes H level, the analog switch 204 is turned on and the output signal of the output terminal 213 is held at 0V regardless of the signal applied to the common contact 198c.

The changeover switch 198 is appropriately changed over by setting and calibration. The set value signal from the input amplifier circuit 3 shown in FIG. 1 is applied to the measured value input terminal 196, and the calibration value signal from the output terminal 188 shown in FIG. 6 is applied to the calibration value input terminal 197. Therefore, the analog signal amplified by the magnification of each range set as described above is output from the output terminal 213. Then, this analog output signal is finally output as an output signal of the carrier wave amplifying circuit 5 via another circuit in the carrier wave amplifying circuit 5 not shown. Although a specific circuit configuration of the filter circuit 7 is not shown,
The cutoff frequency can be set by a circuit configuration similar to the calibration value generation circuit shown and the variable gain amplifier shown in FIG.

Next, the measurement condition reading operation, unit reading operation, and remote setting operation described above will be described based on FIGS. 4 and 5, but the setting conditions will be clarified before that.

In FIG. 4, dial 139 of digital switch 138 is turned to be included in FH. Then, the output terminals b _{0 to} b ₃ of the digital switch 138 all output H level signals and are input to the buffer gates 112 to 115. Further, the calibration value setting circuit 11a shown in FIG. 1 is set to 50 με, and the range setting circuit 11b is set to 0 V.
It is assumed that the range is set. Therefore, the output terminals A to D of the calibration value block 97 shown in FIG.
The signals of the respective levels of L are output, and the signals of the respective levels of L, H, H, L are output to the output terminals A to D of the range block 98, respectively. And the output terminal A of the frequency block 99
It is assumed that signals of H, L, L, and H levels are output to D, respectively. Further, in FIG. 5, the dial 155 of the digital switch 154 is included in "0". Then, L level signals are all output to the output terminals b _{0 to} b ₃ of the digital switch 154 and input to the buffer gates 150 to 153. The digital switch 154 or the previous digital switch 138 (shown in the fourth diagram) is set to "0 to 0", respectively.
9 "or" 6H ~ FH "can be set arbitrarily,
Since the digital switch 154 is a signal for identifying a unit when a plurality of units 33 are used as shown in the second illustration, normally, the set values “0 to 9” are set to the first unit 34 to the tenth, respectively. Set according to unit 36.
Therefore, in the case of the present embodiment, since the illustrated unit 33 is the first unit 34, it is set to "0" as described above.
Further, since the above digital switch 138 is for identifying the type of the sensor 1 connected to the channel or the location (measurement number) of the measurement point, etc., the operator defines the corresponding relationship in advance. You can leave it. In the case of this embodiment, the load converter is defined as FH as the sensor 1.

Now, when the measurement conditions are satisfied, the unit reading operation will be described first.

In FIG. 5, an L level signal is applied as a gate signal (j) to the gate terminal 25, and the unit control input terminal 28
An H level signal is applied as an enable signal (k). The L level gate signal (j) is supplied to the buffer gate 14
Buffer gate 146 applied to control input terminals 6-149.
The outputs of ~ 149 are in a high impedance state and are electrically separated from the bit signal lines 166-169. Then, the gate signal (j) is input to the inverter 144 and output as the H level write signal (q), and the second signal of the AND gate 145 is output.
Applied to the input. On the other hand, the enable signal (k) of H level is applied to the first input terminal of the AND gate 145. As a result, the output of the AND gate 145 becomes the H level, the buffer gates 150 to 153 become the operating state, and the unit signal (l) of all bits L level which is the output signal of the digital switch 154 becomes the unit signal (l ′). ) Is output to each bit signal line 166 to 169 of the data bus line 23 and is output to the data bus terminal 170.

Next, the measurement condition reading operation will be described. Similarly, in FIG. 5, H, L, L, and L level signals are input to the address input terminals 162 to 165 as address signals (i). Decoder 14 receiving this address signal (i)
In the case of 1, only the signal at its output terminal Y ₀ becomes H level and is output as the channel ON-OFF signal (g) of the first channel. On the other hand, the data bus terminal 170 inputs signals of H, L, L, and L levels corresponding to the bit signal lines 166 to 169, and the unit control signal input terminal 28 receives an L level enable signal ( k) and an L level gate signal (j) are input to the gate terminal 25. The L level enable signal (k) is input to the first input terminal of the AND gate 145, the output of which holds the L level regardless of the signal level of the second input terminal, and the outputs of the buffer gates 150 to 153 have high impedance. The data bus line 23 is separated from the data bus line 23. Then, it becomes an H level read / write signal (q) through the L level gate signal (j) inverter 144, and is input to the latch input terminal LT of the data latch 142,
At this time, the signals input to the data input terminals D _{0 to} D ₃ are taken in, output to the output terminals Q _{0 to} Q ₃ , and held. In addition, the buffer gate 146 is driven by the gate signal (j).
The output of ~ 149 has a high impedance and is separated from the bus line 23. Therefore, the signals at the respective levels of H, L, L, and L are output and held at the output terminals Q _{0 to} Q ₃ of the data latch 142.

Next, turning to FIG. 4, the channel ON-OFF signal (g) of the first channel at the H level is input to the channel ON-OFF signal input terminal 132 of the first channel, and as a result, the buffer gates 116 to 119. The H-level channel ON-OFF signal (g) is input to the control input terminal of the buffer gates 116 to 119, and the buffer gates 116 to 119 are brought into the operating state. Further, the above-mentioned H level channel ON-OFF signal (g) is applied to AND gates 133 to 136.
Is applied to the second input terminal of. On the other hand, the output signals output from the output terminals Q _{0 to} Q ₃ of the data latch 142 shown in FIG. 5 are sent to the bit signal lines 128 to 131 of the output bus line 21b and are decoded via the AND gates 133 to 136, respectively. 1
Signals of H, L, L, and L levels are input to 37 input terminals A to D, respectively. As a result, the output terminal Y _{1 of the} decoder 137
Only the signal of H level is input to the control input terminal of the buffer gates 100 to 103 as the output ON-OFF signal (f), the buffer gates 100 to 103 are in the operating state, and the card bus Each bit signal line of line 18
Signals of H, L, L, and L levels are sent to 120 to 123 as calibration value signals (c-1). Since the output terminals Y _{2 to} Y ₇ and Y ₀ of the decoder 137 are all at the L level, the outputs of the buffer gates 104 to 107, 108 to 111, 112 to 115 are all in the high impedance state and separated from the card bus line 18. There is. The set value signal (c-1) of the above calibration value on the card bus line 18 is sent to the input bus line 21a via the buffer gates 116 to 119, and the input terminal D _{0 of the} data latch 143 shown in FIG. Input to ~ D ₃ . here,
The L level gate signal (j) is switched to the H level. By the gate signal (j) which has become the H level, the data latch 143 has the set value signal (c-1) of each level of H, L, L and L applied to the input terminals D _{0 to} D ₃ at that time. Capture and output to output terminals Q _{0 to} Q ₃ and hold. And
At the same time, the gate signal (j) which has become the H level activates the buffer gates 146 to 149 and sends the output signal of the data latch 143 to the data bus line 23 (however, the external device which gives a command signal from the outside also has a data bus). Line 23
Input and output switching control shall be performed so as not to conflict with). As a result, the set value signals (c-1) of the above calibration values at the respective levels of H, L, L, L are sent to the bit signal lines 166 to 169 of the data bus line 23 and output from the data bus terminal 170. To be done.

Next, a 2H signal in hexadecimal notation is input to the data bus terminal 170 as the data signal (h), and the gate signal (j) is returned to the L level again (another input signal, that is, an enable signal (k), an address signal). (I) keeps the previous state). The 2H data signal (h) is latched by the data latch 142 at the time when the gate signal (j) becomes L level, the output bus 21b, and AND gates 133 to 136 shown in FIG.
Is input to the decoder 137 via. In the decoder 137 which has received the 2H data signal (h), only the signal at its output terminal Y ₂ becomes H level, and the buffer gates 104 to 107 are in the operating state. As a result, the range set value signal (c-2)
The L, H, H, and L level signals are sent to the card bus line 18
Sent to the buffer gates 116-119, input bus line
Input terminals D ₀ ~ of the data latch 143 shown in FIG.
Applied to D ₃ . Then, similarly to the above, the gate signal (j), which was at the L level, is switched to the H level, and the data latched by the data latch 143 is sent to the data bus line. As a result, the set value signal (c-2) of each level range of L, H, H, L is output to the data bus terminal. Similarly, by updating the data input to the data bus terminal 170 to 3H and then 4H, H, L, and L already set as the frequency setting value signal (c-3) on the data bus line 23. , H level signals are then sequentially output to the data bus terminal 170 as all bit H level signals which have already been set as the type signal (b ').

Next, the remote setting operation will be described. The address signal (i) is the same as in the measurement condition reading operation.
Therefore, the subsequent operation is the same, and the AND gate 133 of FIG.
~ 136 is open. The enable signal (k) is the same,
Hold at H level. A 5H signal in hexadecimal notation is input to the data bus terminal 170 to set the gate signal (j) to the H level. The data signal (h) of 5H is latched by the data latch 142 by the gate signal (j) which becomes H level, and its output is output to the output bus line 21b and the AND gate 133.
It is input to the decoder 137 via ~ 136. The decoder 137 which receives this 5H data signal (h) outputs its output terminal Y ₅
Becomes H level and is input to the setting pulse input terminal PI of the calibration value block 97 as the setting pulse signal (e) (that is, input to the remote input terminal 74 shown in FIG. 3). Then, 0H is input to the data bus terminal 170 as the data signal (h), and the gate signal (j) that has been at the L level is once brought to the H level and then returned to the L level again. The gate signal (j) that has become L level again is the inverter
The data signal (h) of 0H is latched by the data latch 142 by the write signal (q) of H level inverted by 144, and its output signal is the same as the above.
b, input to the decoder 137 via the AND gates 133 to 136. Decoder 13 which has received the data signal (h) of 0H
In the case of 7, only the signal of its output terminal Y ₀ becomes H level, and the signal of the output terminal Y ₅ that was H level becomes L level. Since nothing is connected to the output terminal Y ₀ of the decoder 137, one positive pulse signal is eventually applied to the setting pulse input terminal PI of the calibration value block 97 by the above operation, 3 illustrated first to seventh D-FF77 to 83
The output state of is advanced by one. That is, 50μ as the setting condition
Since it has been set to ε, the set value is updated to 100 με by the one positive pulse signal {set pulse signal (e)}. By repeating the above operation a required number of times, it is possible to set an arbitrary calibration value.

Similarly, 6H and 0H are alternately input to the data bus terminal 170 as the data signal (h) and the range is set remotely by performing the above operation, and as the data signal (h).
The frequency can be set remotely by alternately inputting 7H and 0H to the data bus pin and performing the above operation.

The above description of the operation was for only the first channel, but 1H is used as the address signal (i) for the address input terminal.
162 to 165, the decoder 141 outputs its output terminal Y ₁
Only the signal of is set to H level, and the channel ON-OFF signal (g) of the second channel is the channel ON-OFF signal output terminal.
Output from 158, AND gate 133-136 of the second channel
Is opened, and the buffer gates 116 to 119 are activated. Then, after that, the output bus line 21 common to multiple channels
b, data is transmitted and received via the input bus line 21b, and this operation is the same as each operation described above. Similarly, by giving 2H to FH as the address signal (i), the third to third
Data can be exchanged with 16 channels, that is, all channels. Further, when a plurality of units are used as shown in FIG. 2, the backbone control signal (p) is unique to each unit, and the backbone data bus line 37 and the backbone address bus line 38 common to each unit are used. Through this, data can be exchanged with any unit by performing the same operation as described above in each unit 33.

As described above, according to the present embodiment, various measurement conditions in the physical quantity measuring device that receives the output of the sensor that converts the physical quantity into the electric quantity and processes this, that is, the analog circuit system 10
The calibration value, measurement range, setting state of filter cutoff frequency, sensor type or connection (correspondence) relationship with the analog circuit system 10, unit identification, etc. are for each channel and each of the three types described above for each unit. By an external command signal, it can be read as digital data in a one-to-one correspondence with the output signal of the analog circuit system 10 of each channel and each unit. Therefore, it becomes possible to omit the conventional measurement condition recording means, that is, the work unrelated to the original measurement work such as writing or voice memo on the magnetic tape. It is possible to significantly reduce the recording amount and the recording work time associated therewith, realize simplification and speeding up to virtually nothing, and achieve the efficiency of the above-mentioned measurement work. In addition, since it is a recording means that does not involve humans, important measurement data is not wasted by forgetting to record it, and there is very little room for human error such as misunderstanding or erroneous entry, and the reliability of measurement data is high. There are many areas that contribute to improvement.

Furthermore, when various data signals (h) as the above-mentioned measurement conditions obtained by this embodiment are recorded in a multi-channel data recorder, it is not necessary to refer to the measurement conditions from the recording paper at the time of reproduction, and a computer is used. When you analyze the measurement data using the existing data analysis device, you can automatically input the measurement conditions, not only improving the efficiency of the measurement work on site, but also improving the efficiency and reliability of the data in various subsequent work. It is possible to improve the sex.

It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

For example, the card bus line 18, the input bus line 21a, the output bus line 21b, the data bus line 23, and the address bus line 24 are not limited to 4 bits, and the number of bits can be increased or decreased depending on the size of the unit 33. The measurement condition setting circuit 11 is not limited to three types, and a setting circuit such as the output circuit 8 may be provided.

It is also possible to separate the analog circuit system 10 from the digital system circuit such as the measurement condition setting circuit 11 by an optical coupling element, a so-called photo coupler.

Furthermore, it is possible to provide an identification signal generating circuit for discriminating the individual function of each card 32 and add it as one of the measurement condition setting circuits 11, and the digital switches 138 and 154 are limited to the one-digit configuration. It is possible to increase the number of digits as appropriate without needing to do so, and in the case of such a configuration, it is possible to generate more detailed type signal (b) and unit signal (l), and to realize even higher efficiency. can do.

(E) Effects As described in detail above, according to the present invention, the measurement condition set in the physical quantity measuring device is made into a one-to-one correspondence with the measurement data output signal of the physical quantity measuring device as a digital signal composed of a plurality of bits. Since it is configured to output automatically correspondingly,
There is no need to record the measurement conditions one by one as in the conventional method, so there is no human error, labor saving and speeding up of the measurement work and improvement of the reliability of the measurement data can be realized, and the measurement data after the measurement work is completed. It is possible to provide a measurement condition information generation device in a physical quantity measuring instrument that can realize labor saving, speedup, and improvement in reliability of measurement data even in processing operations such as sorting and analysis.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 9 relate to the present invention,
Of these, FIG. 1 is a block diagram showing an embodiment of the overall configuration of the present invention, FIG. 2 is a conceptual diagram when the present invention is applied to a multipoint measuring system, and FIG. FIG. 4 is a circuit diagram showing an example of a measurement condition setting circuit which constitutes a part,
FIG. 5 is a circuit diagram showing an example of card bus lines, input / output bus lines and their peripheral circuits, FIG. 5 is a circuit diagram excluding analog circuits in a monitor section, and FIG. 6 is a specific example of a calibration value generation circuit. 7 is a concrete circuit diagram of a variable gain amplifier in a carrier amplifier circuit, FIG. 8 is a concrete circuit diagram of a manual setting unit, and FIG. 9 is a reset signal. It is a concrete circuit diagram of a generation circuit. 1 ... Sensor, 1a ... Measuring bridge, 2 ... Power supply circuit, 3 ... Input amplification circuit, 4 ... Calibration value generation circuit, 5 ... Carrier amplification circuit, 6 ... Detection circuit, 7 ... Filter circuit , 8 ... Output circuit, 9 ... Analog output terminal, 10 ... Analog circuit system, 11 ... Measurement condition setting circuit, 11a ... Calibration value setting circuit, 11b ... Range setting circuit, 11c ... Frequency setting circuit , 12a to 12c ... manual setting section, 13a to 13c ... display circuit, 14a ... type signal setting circuit, 14b ... rotor, 15a to 15c ... setting information output circuit, 16 ... type signal output circuit, 17a …… monitor request signal circuit, 17b …… monitor switch, 18 …… card bus line, 19 …… signal line output circuit, 20 …… output control circuit, 21a …… input bus line, 21b …… output bus line, 22 …… Channel control circuit, 23 …… Data bus line, 24 …… Address Bus line, 25 ... Gate terminal, 26a ... Unit signal setting circuit, 26b ... Rotor, 27 ... Unit signal output circuit, 28 ... Unit control input terminal, 29 ... Measured value output switching circuit, 30 ... … Measured value display part, 31 …… monitor part, 32 …… card, 33 …… unit.

Claims (4)

[Claims] 1. A physical quantity measuring instrument which receives an output of a sensor for converting a physical quantity into an electric quantity and measures and processes this output, by manually switching a circuit element in the physical quantity measuring instrument to set measurement conditions such as a measurement range and a calibration value. Settable measurement condition setting circuit, measurement condition information output circuit that outputs measurement condition information corresponding to the measurement condition set in this measurement condition setting circuit as a digital signal composed of multiple bits, and this measurement condition information output A first common signal line including a plurality of bits in which a plurality of circuits can be connected in parallel, a signal line output circuit provided at one end of the first common signal line, the measurement condition information output circuit, and the measurement condition First to control the setting circuit
Control circuit, a second common signal line composed of a plurality of bits, and a signal line output circuit for connecting / disconnecting the second common signal line and the first common signal line by an external command signal. And a second control circuit for controlling the first control circuit and controlling the first control circuit.
It is configured such that the measurement condition information of the physical quantity measuring instrument can be automatically output from the second common signal line in a time division manner in one-to-one correspondence with the measurement data signal output from the physical quantity measuring instrument. Measuring condition information generator in the characteristic physical quantity measuring instrument. 2. A physical quantity measuring instrument has a variable gain amplifier which receives an output of a sensor and amplifies it with an appropriate gain, and a calibration value generating circuit which generates a plurality of calibration values, and a measurement condition for setting the gain. The output of the setting circuit adjusts the variable gain amplifier to have the set gain, and the output of the measurement condition setting circuit for setting the calibration value causes the calibration value generating circuit to generate the set calibration value. The measurement condition information generating device in the physical quantity measuring instrument according to claim 1, which is adjusted to 3. The physical quantity according to claim 1, wherein the sensor comprises a load transducer, a pressure transducer, an acceleration transducer, a displacement transducer or the like using a strain gauge as a physical quantity-electric quantity conversion element. Measuring condition information generator in measuring instrument. 4. The sensor according to claim 1, wherein the sensor is a temperature sensitive element that senses temperature and outputs an electric signal corresponding to the temperature.
A measurement condition information generator in the physical quantity measuring instrument described in the paragraph.