JPH0785092B2 - AC effective value-DC conversion circuit - Google Patents
AC effective value-DC conversion circuitInfo
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- JPH0785092B2 JPH0785092B2 JP24232585A JP24232585A JPH0785092B2 JP H0785092 B2 JPH0785092 B2 JP H0785092B2 JP 24232585 A JP24232585 A JP 24232585A JP 24232585 A JP24232585 A JP 24232585A JP H0785092 B2 JPH0785092 B2 JP H0785092B2
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- voltage
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- input terminal
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- current
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Description
【発明の詳細な説明】 (発明の分野) 本発明は、交流実効値−直流変換回路に関する。Description: FIELD OF THE INVENTION The present invention relates to an AC effective value-DC conversion circuit.
(従来技術とその問題点) 交流実効値−直流変換回路とは、交流の実効値を求め、
この実効値に基づいて直流に変換する回路である。この
ような変換回路には、入力信号を二乗する二乗回路と、
この二乗回路出力を積分することにより平均化する平均
化回路と、その平均化回路出力を開平する開平回路とか
らなるものがあり、従来ではこれらの各回路をモノリシ
ックICに組み込んだものが知られている(実用電子ハン
ドブック(4)昭和58年11月1日第5版CQ出版株式会社
発行の第421および422ページ参照)。(Prior art and its problems) With the AC effective value-DC conversion circuit, the effective value of AC is obtained,
It is a circuit that converts to DC based on this effective value. Such a conversion circuit includes a squaring circuit that squares an input signal,
There is an averaging circuit that averages the squared circuit output by integrating it, and a square rooting circuit that squares the output of the averaging circuit. Conventionally, it is known that each of these circuits is incorporated in a monolithic IC. (See Practical Electronic Handbook (4), pages 421 and 422, published by CQ Publishing Co., Ltd., 5th edition, November 1, 1983).
しかしながら、交流実効値−直流変換回路をモノリシッ
クICに組み込んだものでは、開平回路が必要であったた
めに回路構成が非常に複雑であるのみならず、それのコ
ストも高くつくものであるという問題点があった。そし
て、このようなコストが高いという問題点がある割に
は、今1つ信頼性に乏しいというという問題点もあっ
た。However, in the case where the AC RMS value-DC conversion circuit is incorporated in the monolithic IC, the circuit configuration is very complicated because the square root circuit is required, and the cost thereof is high. was there. And, although there is a problem that the cost is high, there is another problem that the reliability is not good.
また、整流器と、コンデンサおよび抵抗で構成された時
定数回路とを組み合わせ、その時定数回路の特定数を特
定値に設定して疑似的に実効値変換する方式のものも提
案されている。この提案の回路では回路構成が簡単にな
る反面、実効値変換の精度に劣るという問題点があり、
精度の高い実効値変換を行いたい場合は採用することが
できないものであった。Also proposed is a system in which a rectifier and a time constant circuit composed of a capacitor and a resistor are combined, a specific number of the time constant circuit is set to a specific value, and pseudo effective value conversion is performed. Although the circuit of this proposal has a simple circuit configuration, it has a problem that the accuracy of effective value conversion is poor.
It could not be adopted when it is desired to perform highly accurate RMS conversion.
(発明の目的) 本発明は、前記各問題点を解消することを目的とする。(Object of the Invention) The present invention aims to solve the above problems.
(発明の構成と効果) 本発明は、前記目的を達成するために、二乗化電流が現
れる出力部と負帰還電圧が与えられる負帰還入力部とを
有する二乗回路と、 演算増幅器を備え、この演算増幅器の、一方の入力端子
が前記二乗回路の出力部に接続され、また他方の入力端
子には、実効値変換されるべき整流電圧が与えられるも
のであって、前記二乗回路の出力部の電圧と前記整流電
圧との差を平均化して出力する平均化回路と、 前記平均化回路から出力される平均化出力電圧と前記二
乗回路の出力部の電圧とに基づいて、前記整流電圧の実
効値を出力するとともに、この出力を前記二乗回路の負
帰還入力部に負帰還電圧として負帰還する差動増幅回路
とを具備し、 前記二乗回路は、前記一方の入力端子と接地部との間に
主路を、また前記一方の入力端子に現れる整流電圧と前
記負帰還入力部に現れる前記差動増幅回路からの負帰還
電圧との差電圧とを分圧する分圧点と前記接地部との間
に副路を有し、前記主路には前記演算増幅器の両入力端
子におけるイマジナリショートによって一方の入力端子
に現れる整流電圧と前記接地部の電位との間の電圧差と
核主路内のインピーダンス値とに応じた主電流が流れ、
前記副路には前記分圧電圧と前記接地部の電位との間の
電圧差と該副路内のインピーダンス値とに応じた副電流
が流れるものであり、さらに前記副路内には前記分圧電
圧が前記接地部電位よりも高い第1の状態のときまたは
低い第2の状態のときに導通して副電流が流れる向きに
方向性素子が設けられており、前記一方の入力端子には
前記主電流と副電流とが加算された加算電流が前記第1
の状態のときには前記平均化回路の一方の入力端子から
流れ込み前記第2の状態のときには該一方の入力端子へ
流れ込むとともに、この加算電流が整流電圧波形を近似
した二乗化電流となるように前記主路と副路内それぞれ
のインピーダンス値が設定されている。(Structure and Effect of the Invention) In order to achieve the above object, the present invention includes a squaring circuit having an output section in which a squared current appears and a negative feedback input section to which a negative feedback voltage is applied, and an operational amplifier, One of the input terminals of the operational amplifier is connected to the output section of the squaring circuit, and the other input terminal is supplied with a rectified voltage to be converted into an effective value. An averaging circuit that averages and outputs the difference between the voltage and the rectified voltage; and based on the averaged output voltage output from the averaging circuit and the voltage of the output section of the squaring circuit, the effective rectified voltage. A differential amplifier circuit that outputs a value and negatively feeds back this output to the negative feedback input section of the square circuit as a negative feedback voltage, wherein the square circuit is between the one input terminal and the ground section. To the main road A sub path between the voltage dividing point for dividing the difference voltage between the rectified voltage appearing at the input terminal and the negative feedback voltage appearing at the negative feedback input section and the ground section, and In the main path, there is a main current corresponding to the voltage difference between the rectified voltage appearing at one input terminal due to an imaginary short circuit at both input terminals of the operational amplifier and the potential of the ground section and the impedance value in the nuclear main path. flow,
A subcurrent according to a voltage difference between the divided voltage and the potential of the ground portion and an impedance value in the subpath flows in the subpath, and the subcurrent flows in the subpath. A directional element is provided in a direction in which a sub-current flows when the piezo voltage is in a first state in which the voltage is higher than the ground potential or in a second state in which the voltage is low, and the one input terminal is provided in the one input terminal. The added current obtained by adding the main current and the sub current is the first
In the above state, the current flows from one input terminal of the averaging circuit into the one input terminal in the second state, and the main current is adjusted so that the added current becomes a squared current that approximates the rectified voltage waveform. The impedance value of each of the road and the sub road is set.
あるいは、本発明は、二乗化電流が現れる出力部と負帰
還電圧が与えられる負帰還入力部とを有する二乗回路
と、 演算増幅器を備え、この演算増幅器の、一方の入力端子
が前記二乗回路の出力部に接続され、また他方の入力端
子には、実効値変換されるべき整流電圧が与えられるも
のであって、前記二乗回路の出力部の電圧と前記整流電
圧との差を平均化して出力する平均化回路と、 前記平均化回路から出力される平均化出力電圧と前記二
乗回路の出力部の電圧とに基づいて、前記整流電圧の実
効値を出力するとともに、この出力を前記二乗回路の負
帰還入力部に負帰還電圧として負帰還する差動増幅回路
とを具備し、 前記二乗回路が、前記一方の入力端子と前記負帰還入力
部との間に主路を、また前記一方の入力端子に現れる整
流電圧と前記接地部の電位との差電圧を分圧する分圧点
と前記負帰還入力部との間に副路を有し、前記主路には
前記演算増幅器の両入力端子におけるイマジナリショー
トによって一方の入力端子に現れる整流電圧と前記負帰
還電圧との間の電圧差と該主路内のインピーダンス値と
に応じた主電流が流れ、前記副路には前記分圧電圧と前
記負帰還電圧の電位との間の電圧差と該副路内のインピ
ーダンス値とに応じた副電流が流れるものであり、さら
に前記副路内には前記分圧電圧が前記負帰還電圧よりも
高い第1の状態のときまたは低い第2の状態のときに導
通して副電流が流れる向きに方向性素子が設けられてお
り、前記一方の入力端子には前記主電流と副電流とが加
算された加算電流が前記第1の状態のときには前記平均
化回路の一方の入力端子から流れ込み前記第2の状態の
ときには該一方の入力端子へ流れ込むとともに、この加
算電流が整流電圧波形を近似した二乗化電流となるよう
に前記主路と副路内それぞれのインピーダンス値が設定
されている。Alternatively, the present invention comprises a squaring circuit having an output section in which a squared current appears and a negative feedback input section to which a negative feedback voltage is applied, and an operational amplifier, wherein one input terminal of the operational amplifier is the squaring circuit. A rectified voltage to be converted to an effective value is applied to the other input terminal of the output circuit, and the difference between the output voltage of the squaring circuit and the rectified voltage is averaged and output. Based on the averaged output voltage output from the averaging circuit and the voltage of the output section of the squaring circuit, and outputs the effective value of the rectified voltage, and this output of the squaring circuit. A differential amplifier circuit that negatively feeds back as a negative feedback voltage to a negative feedback input portion, wherein the square circuit forms a main path between the one input terminal and the negative feedback input portion, and the one input Rectified voltage appearing at the terminal There is a sub path between the voltage dividing point for dividing the voltage difference from the potential of the ground section and the negative feedback input section, and the main path has one input due to an imaginary short circuit at both input terminals of the operational amplifier. A main current according to the voltage difference between the rectified voltage appearing at the terminal and the negative feedback voltage and the impedance value in the main path flows, and the divided voltage and the potential of the negative feedback voltage flow in the sub path. A sub-current according to the voltage difference between the sub-path and the impedance value in the sub-path, and when the divided voltage is in the first state higher than the negative feedback voltage in the sub-path. Alternatively, a directional element is provided in a direction in which the sub-current flows in a conductive state when the second state is low, and an addition current obtained by adding the main current and the sub-current is provided to the one input terminal. In the state of 1, it is one of the input terminals of the averaging circuit Inflow In the second state, while flowing into the one input terminal, impedance values in the main path and the sub path are set such that the added current becomes a squared current that approximates the rectified voltage waveform. .
この構成によれば、平均化回路の演算増幅器の両入力端
子はイマジナリショートであるから、一方の入力端子側
に与えられる整流電圧は、他方の入力端子の電圧であ
る。したがって、二乗回路の出力部側と接地部との間の
電圧差または該整流電圧と負帰還電圧との電圧差とそれ
の主路内の抵抗値とに対応した電流(主電流)が該主路
内に流れる。また、それの副路内においては方向性素子
が設けられているから、分圧電圧が接地電位よりも大き
いかまたは小さいか、あるいは分圧電圧が負帰還電圧よ
りも大きいかまたは小さくなると、その副路内には前記
電圧差とその副路内での抵抗値とに対応した副電流が流
れる。このような主電流と副電流とが該二乗回路内で加
算されるから、この二乗回路の出力部には二乗化電流が
現れる。この二乗化電流は、結局、整流電圧の二乗に比
例し、かつ差動増幅回路の出力に反比例していることに
なるから、この二乗化電流が平均化回路に入力されて平
均化され、更に差動増幅回路で差動された電圧は、実効
値の理論式に対応した電圧となる。According to this configuration, since both input terminals of the operational amplifier of the averaging circuit are imaginary short-circuited, the rectified voltage applied to one input terminal side is the voltage of the other input terminal. Therefore, a current (main current) corresponding to the voltage difference between the output side of the squaring circuit and the grounding section or the voltage difference between the rectified voltage and the negative feedback voltage and the resistance value in the main path thereof is the main current. Flowing in the street. Further, since the directional element is provided in the sub path thereof, when the divided voltage is larger or smaller than the ground potential or the divided voltage is larger or smaller than the negative feedback voltage, An auxiliary current corresponding to the voltage difference and the resistance value in the auxiliary path flows in the auxiliary path. Since the main current and the auxiliary current are added in the squaring circuit, a squaring current appears at the output of the squaring circuit. Since this squared current is, after all, proportional to the square of the rectified voltage and inversely proportional to the output of the differential amplifier circuit, this squared current is input to the averaging circuit and averaged, and The voltage differentiated by the differential amplifier circuit becomes a voltage corresponding to the theoretical formula of the effective value.
したがって、本発明によれば、開平回路を使用すること
なく、単に二乗回路と平均化回路と差動増幅回路との組
み合わせだけという簡単な回路構成であるから、モノリ
シックICで構成されたものよりもコスト的に安価な回路
を得ることができる。また、理論式に従った実効値変換
を行うから、前記疑似実効値変換方式のものに比較して
これより信頼性に優れた交流実効値−直流変換を行うこ
とができるのみならず、モノリシックICで構成したもの
と比較してもそれのコストの点を考慮すると信頼性に優
れたものとなる。Therefore, according to the present invention, since the circuit configuration is simple, that is, only the square circuit, the averaging circuit, and the differential amplifier circuit are combined, without using a square root circuit, it is more preferable than that configured by a monolithic IC. An inexpensive circuit can be obtained. Further, since the RMS value conversion is performed according to the theoretical formula, not only the AC RMS value-DC conversion that is more reliable than the pseudo RMS value conversion method can be performed, but also the monolithic IC. Even if it is configured as described above, it will be excellent in reliability in consideration of its cost.
また、本発明によれば、平均化回路の出力が二乗回路に
直接、負帰還されるということはないから、平均化回路
は二乗回路のインピーダンスの影響を考慮することなく
その回路設計が可能となり、したがってその回路設計が
極めて容易になるという効果もある。Further, according to the present invention, since the output of the averaging circuit is not directly negatively fed back to the squaring circuit, the averaging circuit can be designed without considering the influence of the impedance of the squaring circuit. Therefore, there is also an effect that the circuit design becomes extremely easy.
(実施例の説明) 第1図は、本発明の交流実効値−直流変換回路の実施例
1の回路図である。第1図において、INは交流電圧
(e0)の入力端子、OUTは実効値電圧(V0)の出力端子
である。1は、入力端子INからの交流電圧(e0)を全波
整流し、それを実効値変換されるべきプラスの整流電圧
(e1)として出力する全波整流回路である。(Description of Embodiments) FIG. 1 is a circuit diagram of Embodiment 1 of an AC effective value-DC conversion circuit of the present invention. In FIG. 1, IN is an input terminal for an AC voltage (e 0 ), and OUT is an output terminal for an effective value voltage (V 0 ). Reference numeral 1 is a full-wave rectifier circuit that full-wave rectifies the AC voltage (e 0 ) from the input terminal IN and outputs it as a positive rectified voltage (e 1 ) that should be converted into an effective value.
2は、抵抗R1ないしR6と、ダイオードD1,D2とからなる
二乗回路である。この二乗回路2は、二乗化電流(i)
を引き込む出力部21と、負帰還電圧(V0)が与えられる
負帰還入力部22とを有している。二乗回路2はまた、そ
れの出力部21と接地部23との間に主電流(i1)が流れる
主路A(抵抗R4を含む)と、前記整流電圧(e1)より低
い電圧点24,25と接地部23との間に、それぞれ副電流(i
2,i3)が流れる2つの副路B,Cとを備えている。各低電
圧点24,25は、それぞれ抵抗R1と抵抗R2との接続点と、
抵抗R2と抵抗R3との接続点である。各副路B,Cにはそれ
ぞれ、抵抗R5とダイオードD1、抵抗R6とダイオードD2と
が設けられている。ダイオードD1,D2は方向性素子とし
て機能するものであるから、この機能がある素子であれ
ば、例えばトランジスタ等であってもよい。Reference numeral 2 is a square circuit composed of resistors R1 to R6 and diodes D1 and D2. This squaring circuit 2 has a squaring current (i)
Has a negative feedback input section 22 to which a negative feedback voltage (V 0 ) is applied. The squaring circuit 2 also includes a main path A (including a resistor R4) through which a main current (i 1 ) flows between its output section 21 and a ground section 23, and a voltage point 24 lower than the rectified voltage (e 1 ). , 25 and the grounding portion 23, respectively, a subcurrent (i
2 and i 3 ) have two sub paths B and C. The low voltage points 24 and 25 are the connection points of the resistors R1 and R2,
It is a connection point between the resistor R2 and the resistor R3. A resistor R5 and a diode D1, and a resistor R6 and a diode D2 are provided in each of the sub paths B and C. Since the diodes D1 and D2 function as directional elements, any elements having this function may be transistors or the like.
3は、二乗回路2の出力部22に対して二乗化電流(i)
を与える入力部31と、全波整流回路1から整流電圧
(e1)が与えられる入力部32と、平均化出力電圧
(V00)を出力する出力部33と、その入力部31における
イマジナリショートの整流電圧(e1)を出力する出力部
34とを有する平均化回路である。この平均化回路3は、
演算増幅器AMPと、その演算増幅器AMPの、反転入力端子
(−)と出力端子との間において互いに並列に接続され
た平滑用コンデンサCと増幅度決定用抵抗R7とを備えて
いる。3 is a squared current (i) with respect to the output section 22 of the squaring circuit 2.
An input section 31 that gives a rectified voltage (e 1 ) from the full-wave rectifier circuit 1, an output section 33 that outputs an averaged output voltage (V 00 ), and an imaginary short circuit in the input section 31. Output unit that outputs the rectified voltage (e 1 ) of
34 is an averaging circuit having. This averaging circuit 3
The operational amplifier AMP includes a smoothing capacitor C and an amplification degree determining resistor R7 that are connected in parallel between the inverting input terminal (-) and the output terminal of the operational amplifier AMP.
4は平均化回路3の出力部33に一方の入力端子(−)41
が接続され、同じく平均化回路3の出力部34に他方の入
力端子(+)42が接続された差動増幅回路である。4 is one input terminal (-) 41 to the output section 33 of the averaging circuit 3.
Is also connected, and the other input terminal (+) 42 is also connected to the output section 34 of the averaging circuit 3.
次に、実施例1の動作および作用を第2図の波形図に従
って説明する。第2図(a1)は全波整流回路1から平均
化回路2の演算増幅器AMPの正転入力端子(+)に与え
られる整流電圧(e1)の波形を示し、第2図(a2)は二
乗回路2の主路A内の抵抗R4を流れる主電流(i1)の波
形を示し、第2図(b1)は接続点24に現われる電圧
(e2)の波形を示し、第2図(b2)は副路B内の抵抗R5
を流れる副電流(i2)の波形を示し、第2図(c1)は接
続点25に現われる電圧(e3)の波形を示し、第2図(c
2)は副路C内の抵抗R6を流れる副電流(i3)の波形を
示し、第2図(d)は接続点21に現れる二乗化電流
(i)の波形を示している。各図中、0は接地部23の接
地電位を示している。Next, the operation and action of the first embodiment will be described with reference to the waveform chart of FIG. 2 (a1) shows the waveform of the rectified voltage (e 1 ) given from the full-wave rectifier circuit 1 to the non-inverted input terminal (+) of the operational amplifier AMP of the averaging circuit 2, and FIG. 2 (a2) shows The waveform of the main current (i 1 ) flowing through the resistor R4 in the main path A of the squaring circuit 2 is shown, FIG. 2 (b1) shows the waveform of the voltage (e 2 ) appearing at the connection point 24, and FIG. b2) is resistance R5 in secondary path B
2 (c 1) shows the waveform of the sub-current (i 2 ) flowing through the circuit, and FIG. 2 (c 1) shows the waveform of the voltage (e 3 ) appearing at the connection point 25.
2) shows the waveform of the sub-current (i 3 ) flowing through the resistor R6 in the sub path C, and FIG. 2 (d) shows the waveform of the squared current (i) appearing at the connection point 21. In each figure, 0 indicates the ground potential of the ground section 23.
第2図(a1)に示すような波形の整流電圧(e1)が演算
増幅器AMPの正転入力端子(+)に与えられる。演算増
幅器AMPの正転・反転の各入力端子(+)(−)はイマ
ジナリショートになっているから、二乗回路2の抵抗R4
を流れる主電流(i1)は整流電圧(e0)と接地部23の電
位0との電圧差に対応した値となる。この値を式で表せ
ばi1=e1/R4になる。ここで、i1は主電流(i1)の電流
値、e1は整流電圧(e1)の電圧値、R4は抵抗R4の抵抗値
である。また、「/」の記号は徐算記号(÷)である
(以下、同じ)。主電流(i1)の波形は第2図(a2)に
示すようになる。A rectified voltage (e 1 ) having a waveform as shown in FIG. 2 (a1) is applied to the non-inverting input terminal (+) of the operational amplifier AMP. The input / output terminals (+) and (-) of the operational amplifier AMP for inverting and inverting are imaginary short circuit, so the resistance R4 of the squaring circuit 2
The main current (i 1 ) flowing through the circuit has a value corresponding to the voltage difference between the rectified voltage (e 0 ) and the potential 0 of the ground portion 23. If this value is expressed by a formula, i 1 = e 1 / R 4 is obtained. Here, i 1 is the current value of the main current (i 1 ), e 1 is the voltage value of the rectified voltage (e 1 ), and R 4 is the resistance value of the resistor R 4 . The symbol "/" is a division symbol (÷) (hereinafter the same). The waveform of the main current (i 1 ) is as shown in Fig. 2 (a2).
一方、二乗回路2の出力部21に現れる整流電圧(e1)
は、負帰還入力部22に加わる差動増幅回路4の出力
(V0)との関係で接続点24,25においては抵抗R1,R2,R3
とで分圧されるから、その接続点24における電圧(e2)
は、第2図(b1)に示すようになる。即ち、この電圧
(e2)は、ハッチングで示されるようにマイナス電位が
生じる。したがって、抵抗R5に流れる副電流(i2)は、
電圧(e2)が0よりも高いときにダイオードD1が導通す
ることにより第2図(b2)に示すようになる。同様に接
続点25における電圧(e3)は、第2図(c1)に示すよう
になり、したがって抵抗R6に流れる副電流(i3)はダイ
オードD2により第2図(c2)に示すようになる。On the other hand, the rectified voltage (e 1 ) that appears at the output 21 of the squaring circuit 2
Is the resistance R1, R2, R3 at the connection points 24, 25 in relation to the output (V 0 ) of the differential amplifier circuit 4 applied to the negative feedback input section 22.
Since it is divided by and, the voltage at its connection point 24 (e 2 )
Becomes as shown in FIG. 2 (b1). That is, this voltage (e 2 ) has a negative potential as indicated by hatching. Therefore, the auxiliary current (i 2 ) flowing through the resistor R5 is
When the voltage (e 2 ) is higher than 0, the diode D1 becomes conductive, as shown in FIG. 2 (b2). Similarly, the voltage (e 3 ) at the connection point 25 becomes as shown in FIG. 2 (c1), and therefore the auxiliary current (i 3 ) flowing through the resistor R6 is as shown in FIG. 2 (c2) by the diode D2. Become.
これら各電流(i1,i2,i3)の加算は出力部21に現れる二
乗化電流(i)であるから、その加算電流(二乗化電
流)(i)は第2図(d)に示すようになる。なお、二
乗化電流(i)の波形において、a−a間は副電流
(i2)に、b−b間は副電流(i3)にそれぞれ対応して
いる。Since the addition of these respective currents (i 1 , i 2 , i 3 ) is the squared current (i) appearing in the output section 21, the added current (squared current) (i) is shown in FIG. 2 (d). As shown. In the waveform of the squared current (i), the sub-current (i 2 ) corresponds to aa and the sub-current (i 3 ) corresponds to bb.
各電流(i1,i2,i3)の大きさは、各抵抗R4,R5,R6の抵抗
値により決定されるが、その各抵抗値を適宜選定すれば
二乗化電流(i)の波形は、整流電圧(V0)の二乗に、
より近似させることが可能である。また、第2図(d)
の二乗化電流(i)の波形は、2点折れ線であったが、
接続点23,24等を増加させれば、その折れ線を二乗カー
ブに、より近付けることができることは勿論である。The magnitude of each current (i 1 , i 2 , i 3 ) is determined by the resistance value of each resistor R4, R5, R6, but if each resistance value is appropriately selected, the squared current (i) waveform Is the square of the rectified voltage (V 0 ),
It is possible to make it more approximate. Also, FIG. 2 (d)
The waveform of the squared current (i) of was a two-point broken line,
Of course, if the number of connection points 23, 24, etc. is increased, the polygonal line can be brought closer to the square curve.
したがって、全波整流回路1に与えられる交流電圧
(e0)の二乗は整流電圧(e1)の二乗であるから、二乗
化電流(i)は交流電圧(e0)の二乗に比例しかつ差動
増幅出力(V0)に反比例した値、つまり次式(1)で与
えられる。Therefore, since the square of the AC voltage (e 0 ) given to the full-wave rectifier circuit 1 is the square of the rectified voltage (e 1 ), the squared current (i) is proportional to the square of the AC voltage (e 0 ), and The value is inversely proportional to the differential amplification output (V 0 ), that is, given by the following equation (1).
i=(k1・e0 2)/V0 ………(1) ただし、iは二乗化電流(i)の電流値、k1は定数、e0
は整流電圧(e0)の電圧値、V0は差動増幅回路4の出力
値となる。i = (k 1 · e 0 2 ) / V 0 (1) where i is the current value of the squared current (i), k 1 is a constant, and e 0
Is the voltage value of the rectified voltage (e 0 ), and V 0 is the output value of the differential amplifier circuit 4.
この二乗化電流(i)は、平均化回路3で平均化されて
第2図(d)に示すような平均化電流(I ave)とな
る。平均化回路3においては、その抵抗R7に、この平均
化電流(I ave)が流れるから、平均化電圧(V00)は次
式(2)で示される値となる。This squared current (i) is averaged by the averaging circuit 3 to become an averaged current (I ave) as shown in FIG. 2 (d). In the averaging circuit 3, this averaging current (I ave) flows through the resistor R7, so that the averaging voltage (V 00 ) has a value represented by the following equation (2).
V00=e1+R7・I ave=e1+(k1・R7)・{1/(T・
V0)}・∫e0 2dt ………(2) ここで、R7は抵抗R7の抵抗値、I aveは平均化電流(I a
ve)の電流値、e0交流電圧(e0)の電圧値、V0は爺高値
電圧(V0)の電圧値、Tは交流電圧(e0)の半周期であ
る。 V 00 = e 1 + R 7 · I ave = e 1 + (k 1 · R 7) · {1 / (T ·
V 0 )} · ∫e 0 2 dt ……… (2) where R 7 is the resistance value of resistor R 7 and I ave is the averaged current (I a
current value of ve), the voltage value of e 0 AC voltage (e 0), V 0 is the voltage value of the grandfather high voltage (V 0), T is the half cycle of the AC voltage (e 0).
そして、差動増幅回路4は、整流電圧(e1)と平均化出
力(V00)との差動をとるから、k2を定数とすれば、実
効値電圧(V0)は、次式(3)で示されることになる。Since the differential amplifier circuit 4 takes the differential between the rectified voltage (e 1 ) and the averaged output (V 00 ), if k 2 is a constant, the effective value voltage (V 0 ) is It will be indicated by (3).
V0=k2(e1−V00)={−(k1・k2・R7)/(T・
V0)}・∫e12dt ………(3) したがって、V0を右辺におく次式(4)で表すと この式(4)は、実効値の理論式に合致しているから、
平均化回路3の出力である実効致電圧(V0)は実効値で
あることが分かる。V 0 = k 2 (e 1 −V 00 ) = {− (k 1 · k 2 · R 7 ) / (T ·
V 0 )} · ∫e 12 dt (3) Therefore, if V 0 is placed on the right side, Since this formula (4) matches the theoretical formula of the effective value,
It can be seen that the effective voltage (V 0 ) output from the averaging circuit 3 is an effective value.
この実施例では、周波数特性を制限する回路や素子を使
用していないから、周波数特性が良好である。また、平
均化回路3のコンデンサCの容量値と抵抗R7の抵抗値と
でその時定数が決定されるが、交流電圧(e0)のリップ
ル分がその時定数の影響を受けない程度までその時定数
を短くすることができることから、それの応答性は速く
なる。更に、実効値の理論式に従った実効値変換を行っ
ているから、歪波の影響は、疑似実効値変換方式に比較
して非常に小さくなり、信頼性に優れた実効値変換を行
うことができる。In this embodiment, since the circuit and the element for limiting the frequency characteristic are not used, the frequency characteristic is good. The time constant is determined by the capacitance value of the capacitor C of the averaging circuit 3 and the resistance value of the resistor R7. However, the time constant is set to such an extent that the ripple component of the AC voltage (e 0 ) is not affected by the time constant. Since it can be shortened, it is more responsive. Furthermore, since the RMS value conversion is performed according to the RMS theoretical formula, the effect of distorted waves is much smaller than that of the pseudo RMS value conversion method, and RMS value conversion with excellent reliability must be performed. You can
また、実施例の二乗回路2は、ダイオード近似であった
が、これに何等限定されるものではなく、例えば、トラ
ンジスタによる二乗回路であってもよい。Further, although the squaring circuit 2 of the embodiment is a diode approximation, the squaring circuit 2 is not limited to this and may be, for example, a squaring circuit using transistors.
更に、実施例では整流電圧(e1)はプラス電圧であった
が、マイナス電圧であってもよく、この場合はダイオー
ドD1,D2の極性向きを逆にするなどすればよい。Further, although the rectified voltage (e 1 ) is a positive voltage in the embodiment, it may be a negative voltage. In this case, the polar directions of the diodes D1 and D2 may be reversed.
第3図は本発明の実施例2の回路図であり、第1図と対
応する部分には同一の符号を付している。実施例2で特
徴とするところは、負帰還入力部22が抵抗R4とダイオー
ドD1,D2の各カソード側に接続されていることと、抵抗R
4が接地部23に接地されていることである。そして、そ
の動作は第4図の波形図にも示すように、基本的には第
3図のそれと同様であり、異なるところは、低電圧点2
4,25の電圧が、整流電圧(e1)と接地部23の接地電位0
との電圧差で決定され、また主路A、副路B,C内の主電
流(i)1と副電流(i2,i3)とがその低電圧点24,25で
の電圧(e2,e3)と負帰還電圧(V0)との電圧差で決定
されることである。それ以外は実施例1と同様であるか
ら、その詳細な説明は省略する。FIG. 3 is a circuit diagram of the second embodiment of the present invention, and the portions corresponding to those in FIG. 1 are designated by the same reference numerals. The feature of the second embodiment is that the negative feedback input section 22 is connected to the resistor R4 and each cathode side of the diodes D1 and D2.
4 is grounded to the grounding part 23. The operation is basically the same as that of FIG. 3 as shown in the waveform diagram of FIG. 4, except that the low voltage point 2
The voltage of 4,25 is the rectified voltage (e 1 ) and the ground potential of the ground part 23 is 0.
And the main current (i) 1 and the sub-currents (i 2 , i 3 ) in the main path A and the sub paths B, C are determined by the voltage difference (e) between the low voltage points 24, 25. 2 , e 3 ) and the negative feedback voltage (V 0 ). Since the other points are the same as those in the first embodiment, detailed description thereof will be omitted.
図面は本発明の実施例に係り、第1図は実施例1の回路
図、第2図は第1図の回路の動作説明に供する電流−電
圧の波形図、第3図は実施例2の回路図、第4図は第3
図の回路の動作説明に供する電流−電圧の波形図であ
る。 1は全波整流回路、2は二乗回路、3は平均化回路、4
は差動増幅回路。1 is a circuit diagram of the first embodiment, FIG. 2 is a current-voltage waveform diagram for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a circuit diagram of the second embodiment. Circuit diagram, Figure 4 is the third
FIG. 7 is a current-voltage waveform diagram for explaining the operation of the circuit in the figure. 1 is a full-wave rectifier circuit, 2 is a square circuit, 3 is an averaging circuit, 4
Is a differential amplifier circuit.
Claims (2)
与えられる負帰還入力部とを有する二乗回路と、 演算増幅器を備え、この演算増幅器の、一方の入力端子
が前記二乗回路の出力部に接続され、また他方の入力端
子には、実効値変換されるべき整流電圧が与えられるも
のであって、前記二乗回路の出力部の電圧と前記整流電
圧との差を平均化して出力する平均化回路と、 前記平均化回路から出力される平均化出力電圧と前記二
乗回路の出力部の電圧とに基づいて、前記整流電圧の実
効値を出力するとともに、この出力を前記二乗回路の負
帰還入力部に負帰還電圧として負帰還する差動増幅回路
とを具備し、 前記二乗回路は、前記一方の入力端子と接地部との間に
主路を、また前記一方の入力端子に現れる整流電圧と前
記負帰還入力部に現れる前記差動増幅回路からの負帰還
電圧との差電圧とを分圧する分圧点と前記接地部との間
に副路を有し、前記主路には前記演算増幅器の両入力端
子におけるイマジナリショートによって一方の入力端子
に現れる整流電圧と前記接地部の電位との間の電圧差と
該主路内のインピーダンス値とに応じた主電流が流れ、
前記副路には前記分圧電圧と前記接地部の電位との間の
電圧差と該副路内のインピーダンス値とに応じた副電流
が流れるものであり、さらに前記副路内には前記分圧電
圧が前記接地部電位よりも高い第1の状態のときまたは
低い第2の状態のときに導通して副電流が流れる向きに
方向性素子が設けられており、前記一方の入力端子には
前記主電流と副電流とが加算された加算電流が前記第1
の状態のときには前記平均化回路の一方の入力端子から
流れ込み前記第2の状態のときには該一方の入力端子へ
流れ込むとともに、この加算電流が整流電圧波形を近似
した二乗化電流となるように前記主路と副路内それぞれ
のインピーダンス値が設定されていることを特徴とする
交流実効値−直流変換回路。1. A squaring circuit having an output section where a squared current appears and a negative feedback input section to which a negative feedback voltage is applied, and an operational amplifier, one input terminal of which is the output of the squaring circuit. A rectified voltage to be converted into an effective value is applied to the other input terminal, and the difference between the voltage at the output of the squaring circuit and the rectified voltage is averaged and output. An averaging circuit, based on the averaged output voltage output from the averaging circuit and the voltage of the output section of the squaring circuit, outputs the effective value of the rectified voltage, and outputs this output to the negative of the squaring circuit. The feedback input section includes a differential amplifier circuit that negatively feeds back as a negative feedback voltage, wherein the squaring circuit forms a main path between the one input terminal and a ground section, and a rectification that appears at the one input terminal. Voltage and the negative feedback input There is a sub path between the voltage dividing point for dividing a voltage difference between the negative feedback voltage from the differential amplifier circuit and the grounding section, and the main path has an imaginary voltage at both input terminals of the operational amplifier. A main current flows according to the voltage difference between the rectified voltage appearing at one input terminal due to a short circuit and the potential of the ground portion and the impedance value in the main path,
A subcurrent according to a voltage difference between the divided voltage and the potential of the ground portion and an impedance value in the subpath flows through the subpath, and the subcurrent flows through the subpath. A directional element is provided in a direction in which a sub-current flows when the piezo voltage is in a first state in which the voltage is higher than the ground potential or in a second state in which the voltage is low, and the one input terminal is provided in the one input terminal. The added current obtained by adding the main current and the sub current is the first
In this state, the current flows from one input terminal of the averaging circuit to the one input terminal in the second state, and the main current is adjusted so that the added current becomes a squared current that approximates the rectified voltage waveform. An AC effective value-DC conversion circuit, characterized in that impedance values are set for each of the road and the sub road.
与えられる負帰還入力部とを有する二乗回路と、 演算増幅器を備え、この演算増幅器の、一方の入力端子
が前記二乗回路の出力部に接続され、また他方の入力端
子には、実効値変換されるべき整流電圧が与えられるも
のであって、前記二乗回路の出力部の電圧と前記整流電
圧との差を平均化して出力する平均化回路と、 前記平均化回路から出力される平均化出力電圧と前記二
乗回路の出力部の電圧とに基づいて、前記整流電圧の実
効値を出力するとともに、この出力を前記二乗回路の負
帰還入力部に負帰還電圧として負帰還する差動増幅回路
とを具備し、 前記二乗回路が、前記一方の入力端子と前記負帰還入力
部との間に主路を、また前記一方の入力端子に現れる整
流電圧と前記接地部の電位との差電圧を分圧する分圧点
と前記負帰還入力部との間に副路を有し、前記主路には
前記演算増幅器の両入力端子におけるイマジナリショー
トによって一方の入力端子に現れる整流電圧と前記負帰
還電圧との間の電圧差と該主路内のインピーダンス値と
に応じた主電流が流れ、前記副路には前記分圧電圧と前
記負帰還電圧の電位との間の電圧差と該副路内のインピ
ーダンス値とに応じた副電流が流れるものであり、さら
に前記副路内には前記分圧電圧が前記負帰還電圧よりも
高い第1の状態のときまたは低い第2の状態のときに導
通して副電流が流れる向きに方向性素子が設けられてお
り、前記一方の入力端子には前記主電流と副電流とが加
算された加算電流が前記第1の状態のときには前記平均
化回路の一方の入力端子から流れ込み前記第2の状態の
ときには該一方の入力端子へ流れ込むとともに、この加
算電流が整流電圧波形を近似した二乗化電流となるよう
に前記主路と副路内それぞれのインピーダンス値が設定
されていることを特徴とする交流実効値−直流変換回
路。2. A squaring circuit having an output section where a squared current appears and a negative feedback input section to which a negative feedback voltage is applied, and an operational amplifier, one input terminal of which is an output of the squaring circuit. A rectified voltage to be converted into an effective value is applied to the other input terminal, and the difference between the voltage at the output of the squaring circuit and the rectified voltage is averaged and output. An averaging circuit, based on the averaged output voltage output from the averaging circuit and the voltage of the output section of the squaring circuit, outputs the effective value of the rectified voltage, and outputs this output to the negative of the squaring circuit. A differential amplifier circuit that negatively feeds back as a negative feedback voltage to a feedback input section, wherein the square circuit forms a main path between the one input terminal and the negative feedback input section, and the one input terminal. Rectified voltage appearing on the ground and the ground There is a sub path between the voltage dividing point for dividing the voltage difference from the potential of the operational amplifier and the negative feedback input section, and the main path appears at one input terminal due to an imaginary short circuit at both input terminals of the operational amplifier. A main current corresponding to the voltage difference between the rectified voltage and the negative feedback voltage and the impedance value in the main path flows, and the auxiliary path has a voltage between the divided voltage and the potential of the negative feedback voltage. A sub-current flows according to the voltage difference and the impedance value in the sub-path, and the sub-voltage is in the first state higher or lower than the negative feedback voltage in the sub-path. In the state 2, the directional element is provided in a direction in which it conducts and a subcurrent flows, and an added current obtained by adding the main current and the subcurrent to the one input terminal is the first state. In case of, it flows from one input terminal of the averaging circuit. In the second state, the impedance values in the main path and the sub path are set such that the added current flows into the one input terminal and the added current becomes a squared current that approximates the rectified voltage waveform. An AC effective value-DC conversion circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24232585A JPH0785092B2 (en) | 1985-10-29 | 1985-10-29 | AC effective value-DC conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24232585A JPH0785092B2 (en) | 1985-10-29 | 1985-10-29 | AC effective value-DC conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62102164A JPS62102164A (en) | 1987-05-12 |
| JPH0785092B2 true JPH0785092B2 (en) | 1995-09-13 |
Family
ID=17087523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24232585A Expired - Fee Related JPH0785092B2 (en) | 1985-10-29 | 1985-10-29 | AC effective value-DC conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0785092B2 (en) |
-
1985
- 1985-10-29 JP JP24232585A patent/JPH0785092B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62102164A (en) | 1987-05-12 |
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