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JPH0785093B2 - AC effective value-DC conversion circuit - Google Patents
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JPH0785093B2 - AC effective value-DC conversion circuit - Google Patents

AC effective value-DC conversion circuit

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Publication number
JPH0785093B2
JPH0785093B2 JP24350285A JP24350285A JPH0785093B2 JP H0785093 B2 JPH0785093 B2 JP H0785093B2 JP 24350285 A JP24350285 A JP 24350285A JP 24350285 A JP24350285 A JP 24350285A JP H0785093 B2 JPH0785093 B2 JP H0785093B2
Authority
JP
Japan
Prior art keywords
voltage
circuit
output
current
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24350285A
Other languages
Japanese (ja)
Other versions
JPS62104476A (en
Inventor
伸一 村重
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Corp
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Filing date
Publication date
Application filed by Omron Corp filed Critical Omron Corp
Priority to JP24350285A priority Critical patent/JPH0785093B2/en
Publication of JPS62104476A publication Critical patent/JPS62104476A/en
Publication of JPH0785093B2 publication Critical patent/JPH0785093B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Power Conversion In General (AREA)

Description

【発明の詳細な説明】 (発明の分野) 本発明は、交流実効値−直流変換回路に関する。Description: FIELD OF THE INVENTION The present invention relates to an AC effective value-DC conversion circuit.

(従来技術とその問題点) 交流実効値−直流変換回路とは、交流の実効値を求め、
この実効値に基づいて直流に変換する回路である。この
ような変換回路には、入力信号を二乗する二乗回路と、
その二乗回路出力を積分することにより平均化する平均
化回路と、その平均化回路出力を開平する開平回路とか
らなるものがあり、従来ではこれら各回路をモノリシッ
クICに組み込んだものが知られている(実用電子ハンド
ブック(4)昭和58年11月1日第5版CQ出版株式会社発
行の第421および422ページ参照)。
(Prior art and its problems) With the AC effective value-DC conversion circuit, the effective value of AC is obtained,
It is a circuit that converts to DC based on this effective value. Such a conversion circuit includes a squaring circuit that squares an input signal,
There is one that consists of an averaging circuit that averages the squared circuit output by integrating it, and a square root circuit that squares the output of the averaging circuit. Conventionally, it is known that these circuits are incorporated into a monolithic IC. (See Practical Electronic Handbook (4), pages 421 and 422, published by CQ Publishing Co., Ltd., 5th edition, November 1, 1983).

しかしながら、交流実効値−直流変換回路をモノリシッ
クICに組み込んだものでは、開平回路が必要であったた
めに回路構成が非常に複雑であるのみならず、それのコ
ストも高くつくものであるという問題点があった。そし
て、このようなコストが高いという問題点がある割に
は、今1つ信頼性に乏しいというという問題点もあっ
た。
However, in the case where the AC RMS value-DC conversion circuit is incorporated in the monolithic IC, the circuit configuration is very complicated because the square root circuit is required, and the cost thereof is high. was there. And, although there is a problem that the cost is high, there is another problem that the reliability is not good.

また、整流器と、コンデンサおよび抵抗で構成された時
定数回路とを組み合わせ、その時定数回路の時定数を特
定値に設定して疑似的に実効値変換する方式のものも提
案されている。この提案の回路では回路構成が簡単にな
る反面、実効値変換の精度に劣るという問題点があり、
精度の高い実効値変換を行いたい場合は採用することが
できないものであった。
Also proposed is a system in which a rectifier and a time constant circuit composed of a capacitor and a resistor are combined, the time constant of the time constant circuit is set to a specific value, and pseudo effective value conversion is performed. Although the circuit of this proposal has a simple circuit configuration, it has a problem that the accuracy of effective value conversion is poor.
It could not be adopted when it is desired to perform highly accurate RMS conversion.

(発明の目的) 本発明は、前記各問題点を解消することを目的とする。(Object of the Invention) The present invention aims to solve the above problems.

(発明の構成と効果) 本発明は、前記目的を達成するために。実効値変換され
るべき整流電圧が与えられる入力部と二乗化電流が現れ
る出力部とを有する二乗回路と、 演算増幅器を備え、この演算増幅器の一方の入力端子が
前記二乗回路の出力部に接続され、また他方の入力端子
には、この演算増幅器の出力を反転増幅した出力が与え
られ、前記二乗回路の出力部からの二乗化電流に基づい
て、前記整流電圧を平均化して実効値電圧として出力す
る平均化回路と、 前記平均化回路から出力される実効値電圧を反転増幅し
て前記演算増幅器の他方の入力端子に与える反転増幅回
路とを具備し、 前記二乗回路は、それの入力部と出力部との間に主路
を、また前記入力部に与えられる前記整流電圧と接地部
の電位との電圧差を分圧する分圧点と前記出力部との間
に副路をそれぞれ備え、かつ、前記主路には前記整流電
圧と前記演算増幅器の両入力端子におけるイマジナリシ
ョートによって当該出力部に現れる前記反転増幅回路出
力との電圧差と該主路内のインピーダンス値とに応じた
主電流が流れ、また、前記副路には前記分圧点の分圧電
圧と前記反転増幅回路出力との電圧差と該副路内のイン
ピーダンス値とに応じた副電流が流れるものであり、 さらに前記副路内には前記分圧電圧が前記反転増幅回路
出力よりも低いときに導通して前記副電流が流れるよう
にする向きに方向性素子が設けられるとともに、前記二
乗回路の出力部には前記主電流と副電流との加算電流が
前記整流電圧波形を二乗近似した二乗化電流波形となる
ように前記両インピーダンス値が設定されている。
(Structure and Effect of the Invention) The present invention is intended to achieve the above object. A square circuit having an input section to which a rectified voltage to be converted into an effective value is applied and an output section in which a squared current appears, and an operational amplifier, and one input terminal of the operational amplifier is connected to the output section of the squaring circuit. An output obtained by inverting and amplifying the output of the operational amplifier is applied to the other input terminal, and the rectified voltage is averaged as an effective value voltage based on the squared current from the output section of the squaring circuit. An averaging circuit for outputting, and an inverting amplifier circuit for inverting and amplifying the effective value voltage output from the averaging circuit and supplying the inverted value to the other input terminal of the operational amplifier, wherein the squaring circuit has an input section thereof. A main path between the output section and the output section, and a sub path between the output section and the voltage dividing point for dividing the voltage difference between the rectified voltage applied to the input section and the potential of the ground section. And in front of the main road A main current according to the voltage difference between the rectified voltage and the output of the inverting amplifier circuit appearing in the output section due to an imaginary short circuit at both input terminals of the operational amplifier and the impedance value in the main path flows, and the sub path Means that a sub-current corresponding to the voltage difference between the divided voltage at the voltage dividing point and the output of the inverting amplifier circuit and the impedance value in the sub-path flows. A directional element is provided so as to conduct when the voltage is lower than the output of the inverting amplifier circuit to allow the sub-current to flow, and the output portion of the squaring circuit adds the main current and the sub-current. Both impedance values are set so that the current has a squared current waveform obtained by approximating the rectified voltage waveform with a square.

この構成によれば、平均化回路の演算増幅器の両入力端
子はイマジナリショートであるから、一方の入力端子の
電圧は、他方の入力端子の電圧、即ち反転増幅回路の反
転増幅出力である。したがって、二乗回路の入力部に与
えられた整流電圧とその演算増幅器の一方の入力端子の
電圧との差と、それの主路内の抵抗値とに対応した電流
(主電流)が該主路内に流れる。また、それの副路内に
おいては方向性素子が設けられているから、出力部の電
圧が低電圧点の電圧よりも大きいかまたは小さくなる
と、その副路内には演算増幅器の一方の入力端子の電圧
と低電圧点での電圧との差とその抵抗値とに対応した副
電流が流れる。このような主電流と副電流とが該二乗回
路内で加算されるから、この二乗回路の出力部には二乗
化電流が現れる。この二乗化電流は、結局、整流電圧の
二乗に比例し、かつ反転増幅出力に反比例していること
になるから、この二乗化電流が平均化回路に入力される
と、二乗回路の出力部の電圧は、実効値の理論式に対応
した電圧となる。
According to this configuration, since both input terminals of the operational amplifier of the averaging circuit are imaginary short-circuited, the voltage of one input terminal is the voltage of the other input terminal, that is, the inverted amplified output of the inverting amplifier circuit. Therefore, a current (main current) corresponding to the difference between the rectified voltage applied to the input part of the squaring circuit and the voltage at one input terminal of the operational amplifier and the resistance value in the main path is the main path. Flows in. In addition, since the directional element is provided in the sub-path, if the voltage of the output section is higher or lower than the voltage at the low voltage point, one input terminal of the operational amplifier is in the sub-path. A sub-current corresponding to the difference between the voltage at the low voltage and the voltage at the low voltage point and its resistance value flows. Since the main current and the auxiliary current are added in the squaring circuit, a squaring current appears at the output of the squaring circuit. This squared current is, after all, proportional to the square of the rectified voltage and inversely proportional to the inverted amplified output. Therefore, when this squared current is input to the averaging circuit, the output of the squaring circuit is changed. The voltage is a voltage corresponding to the theoretical formula of the effective value.

したがって、本発明によれば、開平回路を使用すること
なく、単に二乗回路と平均化回路との組み合わせだけと
いう簡単な回路構成であるから、モノリシックICで構成
されたものよりもコスト的に安価な回路を得ることがで
きる。また、理論式に従った実効値変換を行うから、前
記疑似実効値変換方式のものに比較してこれより信頼性
に優れた交流実効値−直流変換を行うことができるのみ
ならず、モノリシックICで構成したものと比較してもそ
れのコストの点を考慮すると信頼性に優れたものとな
る。
Therefore, according to the present invention, since the simple circuit configuration is simply a combination of a square circuit and an averaging circuit without using a square root circuit, the cost is lower than that of a monolithic IC. The circuit can be obtained. Further, since the RMS value conversion is performed according to the theoretical formula, not only the AC RMS value-DC conversion that is more reliable than the pseudo RMS value conversion method can be performed, but also the monolithic IC. Even if it is configured as described above, it will be excellent in reliability in consideration of its cost.

また、本発明によれば、平均化回路の出力が二乗回路に
負帰環されていないから、平均化回路は二乗回路のイン
ピーダンスの影響を考慮することなくその回路設計が可
能となり、したがってその回路設計が極めて容易になる
という効果もある。
Further, according to the present invention, since the output of the averaging circuit is not negatively returned to the squaring circuit, the averaging circuit can be designed without considering the influence of the impedance of the squaring circuit. There is also an effect that the design becomes extremely easy.

(実施例の説明) 第1図は、本発明の交流実効値−直流変換回路の回路図
である。第1図において、INは交流電圧(e0)の入力端
子、OUTは実効値電圧(V0)の出力端子である。1は、
入力端子INからの交流電圧(e0)を全波整流し、それを
実効値変換されるべき負の整流電圧(e1)として出力す
る全波整流回路である。
(Description of Embodiments) FIG. 1 is a circuit diagram of an AC effective value-DC conversion circuit of the present invention. In FIG. 1, IN is an input terminal for an AC voltage (e 0 ), and OUT is an output terminal for an effective value voltage (V 0 ). 1 is
It is a full-wave rectifier circuit that full-wave rectifies the AC voltage (e 0 ) from the input terminal IN and outputs it as a negative rectified voltage (e 1 ) that should be converted into an effective value.

2は、抵抗R1ないしR6と、ダイオードD1,D2とからなる
二乗回路である。この二乗回路2は、全波整流回路1か
らの整流電圧(e1)が与えられる入力部21と、二乗化電
流(i)を出力する出力部22とを有している。二乗回路
2はまた、それの入力部21と出力部22との間に主電流
(i1)が流れる主路A(抵抗R4を含む)と、前記整流電
圧(e1)より低い電圧点23,24と出力部22との間に、そ
れぞれ副電流(i2,i3)が流れる2つの副路B,Cとを備え
ている。各低電圧点23,24は、それぞれ抵抗R1と抵抗R2
との接続点と、抵抗R2と抵抗R3との接続点である。各副
路B,Cにはそれぞれ、抵抗R5とダイオードD1、抵抗R6と
ダイオードD2とが設けられている。ダイオードD1,D2は
方向性素子として機能するものであるから、この機能が
ある素子であれば、例えばトランジスタ等であってもよ
い。
Reference numeral 2 is a square circuit composed of resistors R1 to R6 and diodes D1 and D2. The squaring circuit 2 has an input unit 21 to which the rectified voltage (e 1 ) from the full-wave rectifying circuit 1 is applied and an output unit 22 that outputs a squaring current (i). The squaring circuit 2 also includes a main path A (including a resistor R4) through which a main current (i 1 ) flows between its input 21 and output 22 and a voltage point 23 lower than the rectified voltage (e 1 ). , 24 and the output section 22 are provided with two auxiliary paths B and C through which the auxiliary currents (i 2 , i 3 ) respectively flow. The low voltage points 23 and 24 are connected to the resistors R1 and R2, respectively.
And a connection point between the resistors R2 and R3. A resistor R5 and a diode D1, and a resistor R6 and a diode D2 are provided in each of the sub paths B and C. Since the diodes D1 and D2 function as directional elements, any elements having this function may be transistors or the like.

3は、二乗回路2の出力部22に対して二乗化電流(i)
を与える入力部31と、前記整流電圧(e1)の実効値電圧
(V0)を出力する出力部32,33と、反転増幅出力(−
V00)が与えられる入力部34とを有する平均化回路であ
る。この平均化回路3は、演算増幅器AMP1と、その演算
増幅器AMP1の、反転入力端子(−)と出力端子との間に
おいて互いに並列に接続された平滑用コンデンサCと増
幅度決定用抵抗R7とを備えている。この平均化回路3
は、前記二乗化電流(i)に基づいて前記整流電圧
(e1)を平均化して実効値電圧(V0)として出力するよ
うになっている。
3 is a squared current (i) with respect to the output section 22 of the squaring circuit 2.
And an output section 32, 33 for outputting the effective value voltage (V 0 ) of the rectified voltage (e 1 ), and an inverting amplification output (−
V 00 ) and an input section 34 to which the averaging circuit is provided. This averaging circuit 3 includes an operational amplifier AMP1, a smoothing capacitor C and an amplification degree determining resistor R7 connected in parallel with each other between the inverting input terminal (−) and the output terminal of the operational amplifier AMP1. I have it. This averaging circuit 3
Is configured to average the rectified voltage (e 1 ) based on the squared current (i) and output it as an effective value voltage (V 0 ).

4は平均化回路3の出力部33に接続された入力部41と、
同じく平均化回路3の入力部34に接続された出力部42と
を有する反転増幅回路であって、この反転増幅回路4
は、それの入力部41に一端が接続された抵抗R8と、その
抵抗R8の他端が反転入力端子(−)に接続された演算増
幅器AMP2と、この演算増幅器AMP2の反転入力端子(−)
と出力端子との間に接続された抵抗R9とを備えている。
この演算増幅器AMP2の出力端子は、それの出力端子42に
接続されている。
4 is an input unit 41 connected to the output unit 33 of the averaging circuit 3,
Similarly, an inverting amplifier circuit having an output section 42 connected to the input section 34 of the averaging circuit 3,
Is a resistor R8 whose one end is connected to its input section 41, an operational amplifier AMP2 whose other end is connected to an inverting input terminal (-), and an inverting input terminal (-) of this operational amplifier AMP2.
And a resistor R9 connected between the output terminal and the output terminal.
The output terminal of this operational amplifier AMP2 is connected to its output terminal 42.

次に、動作および作用を第2図の波形図に従って説明す
る。第2図(a1)は全波整流回路1から二乗回路2の入
力部21に与えられる整流電圧(e1)の波形を示し、第2
図(a2)は二乗回路2の主路A内の抵抗R4を流れる主電
流(i1)の波形を示し、第2図(b1)は接続点23に現わ
れる電圧(e2)の波形を示し、第2図(b2)は副路B内
の抵抗R5を流れる副電流(i2)の波形を示し、第2図
(c1)は接続点24に現われる電圧(e3)の波形を示し、
第2図(c2)は副路C内の抵抗R6を流れる副電流(i3
の波形を示し、第2図(d)は接続点22に現われる二乗
化電流(i)の波形を示している。各図中、−V00は反
転増幅回路4の出力を示している。
Next, the operation and action will be described with reference to the waveform chart of FIG. FIG. 2 (a1) shows the waveform of the rectified voltage (e 1 ) given from the full-wave rectifier circuit 1 to the input section 21 of the squaring circuit 2.
Figure (a2) shows the waveform of the main current (i 1 ) flowing through the resistor R4 in the main path A of the squaring circuit 2, and Figure 2 (b1) shows the waveform of the voltage (e 2 ) appearing at the connection point 23. 2 (b2) shows the waveform of the sub-current (i 2 ) flowing through the resistor R5 in the sub path B, and FIG. 2 (c1) shows the waveform of the voltage (e 3 ) appearing at the connection point 24.
Figure 2 (c2) shows the auxiliary current (i 3 ) flowing through the resistor R6 in the auxiliary path C.
2 (d) shows the waveform of the squared current (i) appearing at the connection point 22. In each figure, −V 00 indicates the output of the inverting amplifier circuit 4.

第2図(a1)に示すような波形の整流電圧(e1)が二乗
回路2の入力部21に与えられる。平均化回路3の入力部
31はイマジナリショートになっているから、二乗回路2
の抵抗R4を流れる主電流(i1)は整流電圧(e0)と反転
増幅出力(−V00)との電圧差に対応した値となる。こ
の値を式で表せばi1=(e1−V00)/R4になる。ここで、
i1は主電流(i1)の電流値、e1は整流電圧(e1)の電圧
値、R4は抵抗R4の抵抗値である。また、「/」の記号は
徐算記号(÷)である(以下、同じ)。主電流(i1)の
波形は第2図(a2)に示すようになる。
A rectified voltage (e 1 ) having a waveform as shown in FIG. 2 (a1) is applied to the input section 21 of the squaring circuit 2. Input part of averaging circuit 3
31 is an imaginary short, so the squaring circuit 2
The main current (i 1 ) flowing through the resistor R4 has a value corresponding to the voltage difference between the rectified voltage (e 0 ) and the inverted amplified output (−V 00 ). If this value is expressed by an equation, i 1 = (e 1 −V 00 ) / R 4 . here,
i 1 is the current value of the main current (i 1 ), e 1 is the voltage value of the rectified voltage (e 1 ), and R 4 is the resistance value of the resistor R 4 . The symbol "/" is a division symbol (÷) (hereinafter the same). The waveform of the main current (i 1 ) is as shown in Fig. 2 (a2).

一方、二乗回路2の入力部21に与えられている整流電圧
(e1)は、接続点23,24においては抵抗R1,R2,R3とで分
圧されているから、その接続点23における電圧(e2
は、第2図(b1)に示すようになる。即ち、この電圧
(e2)は、ハッチングで示されるようにプラス電位が生
じる。したがって、抵抗R5に流れる副電流(i2)は、マ
イナスの電圧(e2)が反転増幅出力(−V00)よりも低
いときにダイオードD1が導通することにより第2図(b
2)に示すようになる。同様に接続点24における電圧(e
3)は、第2図(c1)に示すようになり、したがって抵
抗R6に流れる副電流(i3)はダイオードD2により第2図
(c2)に示すようになる。
On the other hand, the rectified voltage (e 1 ) applied to the input section 21 of the squaring circuit 2 is divided by the resistors R1, R2, and R3 at the connection points 23 and 24, so the voltage at the connection point 23. (E 2 )
Becomes as shown in FIG. 2 (b1). That is, this voltage (e 2 ) has a positive potential as indicated by hatching. Therefore, the auxiliary current (i 2 ) flowing through the resistor R5 is caused by the diode D1 conducting when the negative voltage (e 2 ) is lower than the inverting amplification output (−V 00 ).
As shown in 2). Similarly, the voltage at node 24 (e
3 ) becomes as shown in FIG. 2 (c1), so that the subcurrent (i 3 ) flowing through the resistor R6 becomes as shown in FIG. 2 (c2) by the diode D2.

これら各電流(i1,i2,i3)は接続点22で加算されるか
ら、その加算電流(二乗化電流)(i)は第2図(d)
に示すようになる。二乗化電流(i)の波形において、
a−a間は副電流(i2)に、b−b間は副電流(i3)に
それぞれ対応している。
Since these respective currents (i 1 , i 2 , i 3 ) are added at the connection point 22, the added current (squared current) (i) is shown in FIG.
As shown in. In the waveform of the squared current (i),
The sub-current (i 2 ) corresponds to aa and the sub-current (i 3 ) corresponds to bb.

各電流(i1,i2,i3)の大きさは、各抵抗R4,R5,R6の抵抗
値により決定されるが、その各抵抗値を適宜選定すれば
二乗化電流(i)の波形は、整流電圧(V0)の二乗に、
より近似させることが可能である。また、第2図(d)
の二乗化電流(i)の波形は、2点折れ線であったが、
接続点23,24等を増加させれば、その折れ線を二乗カー
ブに、より近付けることができることは勿論である。
The magnitude of each current (i 1 , i 2 , i 3 ) is determined by the resistance value of each resistor R4, R5, R6, but if each resistance value is appropriately selected, the squared current (i) waveform Is the square of the rectified voltage (V 0 ),
It is possible to make it more approximate. Also, FIG. 2 (d)
The waveform of the squared current (i) of was a two-point broken line,
Of course, if the number of connection points 23, 24, etc. is increased, the polygonal line can be brought closer to the square curve.

したがって、全波整流回路1に与えられる交流電圧
(e0)の二乗は整流電圧(e1)の二乗であるから、二乗
化電流(i)は交流電圧(e0)の二乗に比例しかつ反転
増幅出力(−V00)に反比例した値、つまり次式(1)
で与えられる。
Therefore, since the square of the AC voltage (e 0 ) given to the full-wave rectifier circuit 1 is the square of the rectified voltage (e 1 ), the squared current (i) is proportional to the square of the AC voltage (e 0 ), and A value that is inversely proportional to the inverted amplification output (-V 00 ), that is, the following equation (1)
Given in.

i=(k1・e0 2)/V00 =(k1・e0 2)/(k2・V0) ………(1) ただし、V00=k2・V0、iは二乗化電流(i)の電流
値、k1,k2は定数、e0は整流電圧(e0)の電圧値、V0
平均化回路2の出力値、−V00は反転増幅出力値とな
る。
i = (k 1 · e 0 2 ) / V 00 = (k 1 · e 0 2 ) / (k 2 · V 0 ) ... (1) where V 00 = k 2 · V 0 , i is the square Current value of the digitized current (i), k 1 and k 2 are constants, e 0 is the voltage value of the rectified voltage (e 0 ), V 0 is the output value of the averaging circuit 2, and −V 00 is the inverted amplification output value. Become.

この二乗化電流(i)は、平均化回路3で平均化されて
第2図(d)に示すような平均化電流(I ave)とな
る。平均化回路3においては、その抵抗R7にこの平均化
電流(I ave)が流れるから、実効値電圧(V0)は次式
(2)で示される値となる。
This squared current (i) is averaged by the averaging circuit 3 to become an averaged current (I ave) as shown in FIG. 2 (d). In the averaging circuit 3, the averaging current (I ave) flows through the resistor R7, so that the effective value voltage (V 0 ) becomes a value represented by the following equation (2).

V0=−V00+R7・I ave=−k2・V0 +R7・(1/T)・∫{(k1・e0 2)/(k2・V0)}dt……
…(2) ここで、R7は抵抗R7の抵抗値、I aveは平均化電流(I a
ve)の電流値、e0は交流電圧(e0)の電圧値、V0は実効
値電圧(V0)の電圧値、Tは交流電圧(e0)の半周期で
ある。
V 0 = -V 00 + R 7 · I ave = -k 2 · V 0 + R 7 · (1 / T) · ∫ {(k 1 · e 0 2) / (k 2 · V 0)} dt ......
(2) Here, R 7 is the resistance value of the resistor R 7 , and I ave is the averaged current (I a
ve) current value, e 0 is the voltage value of the AC voltage (e 0 ), V 0 is the voltage value of the effective value voltage (V 0 ), and T is the half cycle of the AC voltage (e 0 ).

したがって、実効値電圧(V0)は、次式(3)で示され
ることになる。
Therefore, the effective voltage (V 0 ) is expressed by the following equation (3).

この式は、実効値の理論式に合致しているから、平均化
回路3の出力である実効値電圧(V0)は実効値であるこ
とが分かる。
Since this formula matches the theoretical formula of the effective value, it can be seen that the effective voltage (V 0 ) which is the output of the averaging circuit 3 is the effective value.

この実施例では、周波数特性を制限する回路や素子を使
用していないから、周波数特性が良好である。また、平
均化回路3のコンデンサCの容量値と抵抗R7の抵抗値と
でその時定数が決定されるが、交流電圧(e0)のリップ
ル分がその時定数の影響を受けない程度までその時定数
を短くすることができることから、それの応答性は速く
なる。更に、実効値の理論式に従った実効値変換を行っ
ているから、否波の影響は、疑似実効値変換方式に比較
して非常に小さくなり、信頼性に優れた実効値変換を行
うことができる。
In this embodiment, since the circuit and the element for limiting the frequency characteristic are not used, the frequency characteristic is good. The time constant is determined by the capacitance value of the capacitor C of the averaging circuit 3 and the resistance value of the resistor R7. However, the time constant is set to such an extent that the ripple component of the AC voltage (e 0 ) is not affected by the time constant. Since it can be shortened, it is more responsive. Furthermore, since the rms value conversion is performed according to the rms theoretical formula, the effect of the denial wave is extremely small compared to the pseudo rms conversion method, and rms value conversion with excellent reliability must be performed. You can

また、実施例の二乗回路2は、ダイオード近似であった
が、これに何等限定されるものではなく、例えば、トラ
ンジスタによる二乗回路であってもよい。
Further, although the squaring circuit 2 of the embodiment is a diode approximation, the squaring circuit 2 is not limited to this and may be, for example, a squaring circuit using transistors.

更に、実施例では整流電圧(e1)は負電圧であったが、
正電圧であってもよく、この場合はダイオードD1,D2の
極性向きを逆にするなどすればよい。
Further, although the rectified voltage (e 1 ) is a negative voltage in the embodiment,
A positive voltage may be used, and in this case, the polarities of the diodes D1 and D2 may be reversed.

【図面の簡単な説明】[Brief description of drawings]

図面は本発明の実施例に係り、第1図はこの実施例の回
路図、第2図は第1図の回路の動作説明に供する電流−
電圧の波形図である。 1は全波整流回路、2は二乗回路、 3は平均化回路、4は反転増幅回路。
The drawings relate to an embodiment of the present invention. FIG. 1 is a circuit diagram of this embodiment, and FIG. 2 is a current for explaining the operation of the circuit of FIG.
It is a wave form diagram of a voltage. 1 is a full-wave rectifier circuit, 2 is a square circuit, 3 is an averaging circuit, and 4 is an inverting amplifier circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】実効値変換されるべき整流電圧が与えられ
る入力部と二乗化電流が現れる出力部とを有する二乗回
路と、 演算増幅器を備え、この演算増幅器の一方の入力端子が
前記二乗回路の出力部に接続され、また他方の入力端子
には、この演算増幅器の出力を反転増幅した出力が与え
られ、前記二乗回路の出力部からの二乗化電流に基づい
て、前記整流電圧を平均化して実効値電圧として出力す
る平均化回路と、 前記平均化回路から出力される実効値電圧を反転増幅し
て前記演算増幅器の他方の入力端子に与える反転増幅回
路とを具備し、 前記二乗回路は、それの入力部と出力部との間に主路
を、また前記入力部に与えられる前記整流電圧と接地部
の電位との電圧差を分圧する分圧点と前記出力部との間
に副路をそれぞれ備え、かつ、前記主路には前記整流電
圧と前記演算増幅器の両入力端子におけるイマジナリシ
ョートによって当該出力部に現れる前記反転増幅回路出
力との電圧差と該主路内のインピーダンス値とに応じた
主電流が流れ、また、前記副路には前記分圧点の分圧電
圧と前記反転増幅回路出力との電圧差と該副路内のイン
ピーダンス値とに応じた副電流が流れるものであり、 さらに前記副路内には前記分圧電圧が前記反転増幅回路
出力よりも低いときに導通して前記副電流が流れるよう
にする向きに方向性素子が設けられるとともに、前記二
乗回路の出力部には前記主電流と副電流との加算電流が
前記整流電圧波形を二乗近似した二乗化電流波形となる
ように前記両インピーダンス値が設定されていることを
特徴とする交流実効値−直流変換回路。
1. A squaring circuit having an input section to which a rectified voltage to be converted into an effective value is applied and an output section in which a squared current appears, and an operational amplifier, wherein one input terminal of the operational amplifier is the squaring circuit. The output of the operational amplifier is inverted and amplified, and the other input terminal is connected to the output of the output of the square amplifier, and the rectified voltage is averaged based on the squared current from the output of the squaring circuit. And an inverting amplifier circuit that outputs as an effective value voltage, and an inverting amplifier circuit that inverts and amplifies the effective value voltage output from the averaging circuit and applies the inverted value to the other input terminal of the operational amplifier. , A main path between the input section and the output section, and a sub path between the output section and the voltage dividing point for dividing the voltage difference between the rectified voltage applied to the input section and the potential of the ground section. Each with a road and in front In the main path, a rectified voltage and a main current corresponding to an impedance value in the main path and a voltage difference between the inverting amplifier circuit output appearing in the output section due to an imaginary short circuit at both input terminals of the operational amplifier, In addition, a sub-current corresponding to a voltage difference between the divided voltage at the voltage dividing point and the output of the inverting amplifier circuit and an impedance value in the sub-path flows in the sub-path. Is provided with a directional element in a direction in which it conducts when the divided voltage is lower than the output of the inverting amplifier circuit so that the sub-current flows, and the main current and An AC effective value-DC conversion circuit, wherein both impedance values are set so that an added current with a sub-current has a squared current waveform obtained by approximating the rectified voltage waveform with a square.
JP24350285A 1985-10-30 1985-10-30 AC effective value-DC conversion circuit Expired - Fee Related JPH0785093B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24350285A JPH0785093B2 (en) 1985-10-30 1985-10-30 AC effective value-DC conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24350285A JPH0785093B2 (en) 1985-10-30 1985-10-30 AC effective value-DC conversion circuit

Publications (2)

Publication Number Publication Date
JPS62104476A JPS62104476A (en) 1987-05-14
JPH0785093B2 true JPH0785093B2 (en) 1995-09-13

Family

ID=17104847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24350285A Expired - Fee Related JPH0785093B2 (en) 1985-10-30 1985-10-30 AC effective value-DC conversion circuit

Country Status (1)

Country Link
JP (1) JPH0785093B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002098728A (en) * 2000-07-17 2002-04-05 Matsushita Electric Ind Co Ltd Earth leakage detection device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107179432A (en) * 2017-06-02 2017-09-19 深圳巴斯巴科技发展有限公司 A kind of automobile charging box and its current effective value measuring method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002098728A (en) * 2000-07-17 2002-04-05 Matsushita Electric Ind Co Ltd Earth leakage detection device

Also Published As

Publication number Publication date
JPS62104476A (en) 1987-05-14

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