JPH0786886B2 - Hardware design system and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hardware design system and method for obtaining connection information of a function or a logic circuit by inputting hardware specifications.

[0002]

2. Description of the Related Art In recent years, in the design of hardware, tools for inputting the operation and structure of hardware in a functional block diagram or a function or logic description language (hardware connection description language) have been developed. This kind of description language is
For example, “Iwanami Information Science Dictionary”, May 25, 1990
Line, p587 ",
A logical diagram used to define the specifications exactly.
Intuitive ease of understanding compared to surface expression
Slightly inferior in terms of accuracy, detail, and scale
A design method centered on CAD such as computer input
Versatile because it has many excellent features when adopted
Has been.

As an example, for the functional design, a functional design system such as a personal computer or an engineering workstation is used, a functional block diagram is drawn by a graphic editor or the like, and the graphic information is converted into a functional description language. Similarly, in the logic design, a functional drawing system such as a personal computer or an engineering workstation was used to draw a logic cell by drawing a logic cell with a graphic editor, and the graphic information was converted into a logical connection description language. .

[0004]

However, according to the above-mentioned conventional example, a logic cell often has a bit width, for example, in a data path, logic cells are often configured in units of 1 bit or 4 bits. Was difficult to see, and the number of drawings was large, making management difficult. In addition, it takes a lot of time to convert the drawing information into the hardware connection description language. Furthermore, specification creation, functional design,
Since the logical designs are different applications, there are problems that the operation of each system must be acquired and that the applications need to be complicatedly switched.

The present invention has been made in view of the above-mentioned circumstances, and specification specification, function design, and logic design can be realized in one environment such as a word processor or editor used by oneself, and the functions therein. A hardware design system and method that simplifies the design by expressing diagrams and logical diagrams and speeds up conversion to a hardware connection description language
The purpose is to provide the law .

[0006]

According to the present invention, a document file containing logic information expressing logic or function in the form of a table or an expression is created by using a text editor, and the document file created here is created. It is characterized in that the above logic information is extracted from the table and converted from a table or an expression into a hardware connection description language.

Further, effective data is extracted from the table, and this is expanded bit by bit to generate bit array data, and the above-mentioned bit array data is rearranged according to the array information of the library prepared for each cell and hardware is arranged. It is converted into a connection description language.

[0008]

With the above-described structure, first, the word processor or the editing program is used to create the document file by inserting the above logic information into the text such as the hardware design specifications. The logic information is extracted from this document file, and the tables and expressions are converted into a hardware connection description language (logic circuit connection description language or function description language).

As a result, hardware specifications, functional diagrams, logical development diagrams, etc. can be integrated into one file, and
It can be realized in one environment without extending to various applications, contributing to high-speed processing.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a CP that is the control center of the system.
U. A main memory 2 is used as a working area for storing an editor program for creating a document file and a language conversion program. The CPU 1 reads this program and executes the intended purpose.

A keyboard (KB) 3 is used to input specification information. The specification information includes logic information in addition to normal document information. In this logic information, logic or function is expressed in the form of a table or an expression.

The formats of the above table descriptions are shown in FIGS. Here, FIG. 2 shows a standard description, FIG. 3 (a) shows a register and latch description, FIG. 3 (b) shows a multiplexer description, and FIG. 3 (c) shows a decoder description. Further, the format of the above expression is shown in FIG.

In the figure, the first column shows the control command designation area, and the commands are M, I, O, C, S, E, and
F, Q, QN, E, etc. are prepared. The function of each command will be described later.

In the figure, reference numeral a is a command (M command) for designating a module name (description of a hierarchical name), and b is a command (I command) for designating a signal name for inputting a module.
In the figure, c is an area of a command (O command) for designating a signal name output from the module. d is a command (C command) for designating a comment line, and e is a region (S command region) of a table start mark (a start mark of a region for converting the hardware connection description language).

Reference numeral f denotes a unit name description area, which describes the name of a unit having one function. If it is a function, describe the block name of the function. If it is a logic, describe the cell name. g
Is a description area of the bit width of the output signal in the table. h is the output signal name, i is the input signal name 1, j is the input signal name 2,
Each is a description area.

K is an area (area of E command) of a table end mark (end mark of an area to be converted into the hardware connection description language). 1 is an area for a command (F command) for designating the end of a module (designating the end of one layer), and m is an area for a table start mark in a description of omitting registers and latches.

N is an abbreviated description of registers and latches, and Q
Command to specify that only the (Q output) side is converted to the language (if nothing is specified, it is converted to Q, Q bar) (Q
Command) area. o is a short description of registers and latches, and is a command (QN command) area for designating that only the Q bar (Q bar output) side is to be converted into a language. p is a table start mark area in the multiplexer abbreviation description, and q is a specified area of the multiplexer selection signal name in the multiplexer abbreviation description. r is an area of a command (D command) directly described in the logic circuit connection description language, s
Is a command (H command) written directly in the function description language
Area.

Returning to FIG. 1, reference numeral 4 is a display device (DISP), which displays document information input by the keyboard 3 and edited by the editor, and the result of language conversion by the language conversion program. . Reference numeral 5 denotes an external file device such as a floppy disk device or a hard disk device, which stores various files prepared for each cell in addition to the intermediate file. A system bus 6 is commonly connected to the CPU 1, the main memory 2, the keyboard 3, the display device 4, and the external file device 5 described above.

FIGS. 5 to 7 show a program for converting the description expressed in the table format shown in FIGS. 2 and 3 and the description expressed in the expression format shown in FIG. 4 into a hardware connection description language. Partial view of the flowchart showing the processing outline,
8 to 11 are partial diagrams of the flowcharts showing the procedure of the process of converting the table in FIG. 7 into TDL (Hardware Connection Description Language).

FIGS. 12 and 13 are diagrams for explaining the operation in the case of extracting valid data from a file containing logic information in a table format and converting it into a hardware connection description language, using a 4-bit latch as an example. .

In the figure, 121 is a document file (input file) containing logic information expressed in a table format, 122
Is a logic diagram represented by the same logic information, and 123 is an intermediate file (DATAS file) in which valid data extracted from the file 121 is written. In addition, 131
Is a bit array buffer in which the extracted valid data is expanded in bit units, 132 is a library prepared for each cell, and 133 is a hardware connection description language (TDL) converted from the bit array buffer 131.

The operation of the embodiment of the present invention will be described below with reference to FIGS. First, the CPU 1 uses the editor program stored in the main memory 2 to open the created document file (input file) 121 shown in FIG. 12, for example, which is input by the keyboard 3 (step 51 in FIG. 5). . Then, the CPU 1 sequentially reads the input file 121 record by record as described below, and extracts the logic information expressed in a table or an expression format.

That is, the CPU 1 sets the input file 121 to 1
Each record is read (step 52 in FIG. 5), and the M command is searched first to extract the module name (steps 53 and 54 in FIG. 5). Then, the CPU 1 opens the output file to create the conversion file and writes the module name. (Steps 55 and 56 in FIG. 5).

Next, the CPU 1 continues to read the record from the input file 121 (step 61 in FIG. 6), and this time searches the I command to extract the input signal and write it to the output file. (FIG. 6 Steps 62, 6
3).

Next, the CPU 1 continues reading the record from the input file 121 (step 64 in FIG. 6), and this time searches the O command to extract the output signal and write it into the output file. (FIG. 6 Steps 65, 6
6).

Then, the CPU 1 continues reading the record from the input file 121 (step 71 in FIG. 7), and if it detects the B command and extracts the bidirectional signal, writes it in the output file (steps 72, 73 in FIG. 7). ).
If an S command is detected (step 7 in FIG. 7).
4), the CPU 1 executes the process (step 75 in FIG. 7) of converting the table (logic information described in the table format) in the input file 121 into the hardware connection description language (TDL). The procedure of this conversion (TDL conversion) processing is made into a subroutine as shown in FIGS. 8 to 11, and the details will be described later.

Further, if the CPU 1 detects the D command by reading the record from the input file 121, it directly executes the description processing by the formula (steps 76 and 7 in FIG. 7).
7). Similarly, if the C command is detected, the CPU 1 performs comment processing (steps 78 and 79 in FIG. 7). Finally, the CPU 1 searches for an F command and performs writing processing to the output file.

Here, the conversion process (TDL conversion process) into the hardware connection description language by the subroutine will be described with reference to FIGS. 8 to 11. First CP
U1 marks the end of valid data in the table (E command)
Intermediate file (DATAS file) until is detected
The data is written in 123 and is taken into a certain buffer (# 1) (steps 81 and 82 in FIG. 8).

Then, the CPU 1 stores the output signal of the buffer (# 1) in the bit array buffer 131 (step 83 in FIG. 8), and bitwise expands the signal having a bit width and writes it in the bit array buffer 131 (step 8 in FIG. 8). 8
4). The CPU 1 loops this process by the number of output signals of the library 132 prepared for each cell.

Similarly, the CPU 1 stores the input signal of the buffer (# 1) in the bit array buffer 131 (step 91 in FIG. 9), and expands the signal having a bit width into the bit array buffer 131 (FIG. 9). Step 9
2). The CPU 1 loops this processing by the number of input signals of the library 132 prepared for each cell.

Finally, the CPU 1 arranges the data of the bit array buffer 131 according to the array information of the library 132 to create the hardware connection description language (TDL) 133 and writes it in the output file (step 93 in FIG. 9).
When the end mark (E command) in the table is detected (step S94 in FIG. 9), the series of TDL conversion processing ends.

[0033]

As described above, according to the present invention, an easy-to-see functional diagram and logical diagram can be expressed, and conversion into a hardware connection description language can be speeded up. In addition, a hardware internal specification, functional diagram (block diagram), logical expansion information, etc. can be integrated in one document file, and the specification, functional design, and logical design are used by the word processor. Alternatively, it can be realized in one environment such as an editor.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a system to which the present invention is applied.

FIG. 2 is a diagram showing an example of logic information expressed in a “table” used in the embodiment.

FIG. 3 is a diagram showing an example of logic information expressed in a “table” used in the embodiment.

FIG. 4 is a diagram showing an example of logic information represented by an “expression” used in the embodiment.

FIG. 5 is a partial view of a flowchart showing a processing outline of a program for converting the logic information into a hardware connection description language.

FIG. 6 is another partial view of the flowchart.

FIG. 7 is a remaining partial view of the same flowchart.

FIG. 8 is a partial view showing a specific processing procedure of a subroutine for realizing the conversion processing (step 75) into the hardware connection description language shown in FIG. 7.

FIG. 9 is another partial view showing the specific processing procedure of the subroutine.

FIG. 10 is still another partial view showing the specific processing procedure of the same subroutine.

FIG. 11 is a remaining partial view showing the specific processing procedure of the subroutine.

FIG. 12 is a diagram showing a part of an operation explanatory diagram for explaining an operation when valid data is extracted from a file including logic information in a tabular format and converted into a hardware connection description language by taking a 4-bit latch as an example. .

FIG. 13 is a diagram showing the rest of the same operation explanatory diagram.

[Explanation of symbols]

1 ... CPU, 2 ... main memory, 3 ... keyboard (KB), 4
... Display (DISP), 5 ... External file device,
6 ... System bus, 121 ... Input file (document file), 123 ... Intermediate file, 131 ... Bit array buffer, 133 ... TDL (hardware connection description language).

Claims (3)

[Claims] 1.Logic created by the document editing device
Or logic information that expresses functions in a predetermined table format,
First control command indicating the start position of the logic information
And a document file including a second control command indicating the end position.
Hardware that generates a hardware connection description language from
A wear design system, Means for reading data from the document file in predetermined units
When, The data read by this reading means is the first
Detection means for detecting that the control command is
When, The data read by the reading means is the second data.
Detection means for detecting that the control command is
When, The first detection means detects the first control command.
After being emitted, the second detection means then causes the second
By the time when the control command is detected,
Extracted data to be read as logic information
The extracted data according to the specified procedure.
Means for converting to a hardware connection description language, Hardware connection description converted by this converter
Means to store words in the output file Hardware design system characterized by comprising
Mu. 2.On the hardware connection description language for each cell
Further means for holding the array information that defines the data array of
Prepare, The conversion means develops the extracted data in bit units.
Open to generate bit array data, and
The data according to the array information of the corresponding cells.
To generate the hardware connection description language.
The hardware design system according to claim 1, which is a characteristic. 3.Logic created by the document editing device
Or logic information that expresses functions in a predetermined table format,
First control command indicating the start position of the logic information
And a document file including a second control command indicating the end position.
Hardware that generates a hardware connection description language from
Is a clothing design method, Before reading data from the document file in specified units
Note First and second control Detect the command, After detecting the first control command, the second control
Read from the document file before detecting the command
Extracted data as the logic information,
The output data is connected to the hardware according to the specified processing procedure.
Converted to a continuous description language, Output file of this converted hardware connection description language
A hardware design method characterized by storing in a memory.