JP3045123B2 - Machine-readable recording medium recording HDL editor and program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an HDL editor for inputting and editing a source code described in a hardware description language (HDL).

[0002]

2. Description of the Related Art Conventionally, in addition to a general-purpose editing function, various functions such as a coding function using a syntax template, a syntax checking function, an error display function, a reserved word automatic completion function, a reserved word highlighting function, and the like. HDL editors with functions have been put to practical use. By using the HDL editor to which such various functions are added, HDL
It is possible to efficiently input and edit the source code described in.

[0003]

In the hardware design using HDL, description of a clock signal and a reset signal is very important. However, the conventional HDL editor does not consider this point at all. Was. That is, the conventional HDL editor handles the description of the clock signal and the reset signal in the same manner as other descriptions.

[0004] For this reason, when hardware design is performed using a plurality of clock signals and reset signals, a description problem occurs only by looking at the source code displayed or printed out by the HDL editor. It is easy to miss a point. Therefore, if the input and editing of the source code were performed using the conventional HDL editor, inconvenience in the logic and timing could be easily found in the function verification and the timing verification, which are the subsequent processes, and the work was repeated every time. Must. Further, in the case of the design review of the HDL description, it takes a very long time since a person other than the designer must follow the HDL description in order to obtain information on the clock signal and the reset signal. . As described above, when the input and the editing of the source code are performed using the conventional HDL editor, the work is likely to return, and it is very difficult for a person other than the designer to obtain information on the clock signal and the reset signal. Since it takes time, there is a problem that it is difficult to improve productivity in hardware design. Incidentally, Japanese Patent Laid-Open No. 7-
Japanese Unexamined Patent Publication No. 73232 proposes a technique of extracting and outputting circuit scale, power consumption, test vector failure detection information, and the like indicated by the input HDL description. The above-mentioned problems cannot be solved.

An object of the present invention is to improve productivity in hardware design by making it possible to easily recognize information on a clock signal and a reset signal existing in a source code described in HDL. To make it happen.

[0006]

According to an aspect of the present invention, there is provided an HDL editor for inputting and editing a source code described in a hardware description language. Extracting means for extracting information on a clock signal and a reset signal from the extracted source code, and comment statement adding means for generating a source code in which information on the clock signal and the reset signal extracted by the extracting means is added in the form of a comment statement And

In this configuration, the extracting means extracts information (signal name, used process, used edge, etc.) relating to the clock signal and the reset signal from the source code described in the hardware description language, and adds a comment sentence. The means
A source code is generated in which information on the clock signal and the reset signal extracted by the extracting means is added in the form of a comment statement.

The HDL editor according to the present invention has a source code in which a comment statement is added by the comment statement adding means so that a designer can easily recognize a portion where a clock signal and a reset signal are used. Is displayed, and the designer selects information on a specific clock signal and reset signal in the comment statement,
There is provided information display means for highlighting a clock signal and a reset signal corresponding to the selected information.

In this configuration, when the designer selects information on a specific clock signal and reset signal in the comment text, the information display means highlights the clock signal and reset signal corresponding to the selected information. .

Further, the HDL editor of the present invention is
In order to make it easy to understand the relationship between the clock signal and the reset signal in the lower hierarchy, in a HDL editor that inputs and edits a source code described in a hardware description language, a source described in a hardware description language is used. Extracting means for extracting information on the clock signal and the reset signal from the code; comment comment adding means for generating a source code in which information on the clock signal and the reset signal extracted by the extracting means is added in the form of a comment statement;
Based on the contents of an upper source code indicating the connection of the lower block and a comment sentence added to the lower source code indicating the operation of the lower block and indicating information on a clock signal and a reset signal of the lower block. Extracting the correspondence between the clock signal and reset signal in the upper source code and the information on the clock signal and reset signal of the lower block, and generating a source code in which the extracted correspondence is added in the form of a comment statement. Hierarchical relationship extracting means.

In this configuration, when a high-order source code indicating the connection of the low-order block is input, the hierarchical relation extracting means performs the contents of the high-order source code and the low-order source code indicating the operation of the low-order block. Based on the comment sentence, the clock signal and reset signal in the upper source code and the clock signal and
Generates a source code in which the correspondence with the information regarding the reset signal is added in the form of a comment statement.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of an HDL editor according to the present invention. The data processor 1 comprises a computer, a storage device 2, a keyboard 3, a display device 4, a printer 5, a recording medium, and the like. 6 is comprised.

The keyboard 3 is used for inputting HDL source code and various commands of the HDL editor. The storage device 2 stores HDL source codes 21, 22 and the like. The display device 4 is H
Used to display DL source code and the like. The printer 5 is used to print out the HDL source code.

The data processing apparatus 1 comprises an extracting unit 11, a comment adding unit 12, an information displaying unit 13, and a text editing unit 14.

The text editing means 14 has a function of storing the HDL source code 21 input from the keyboard 3 in the storage device 2 and a function of editing.

The extracting means 11 has a function of reading the HDL source code 21 from the storage device 2 and analyzing the syntax thereof to extract information on the clock signal and the reset signal existing in the HDL source code 21.

The comment statement adding means 12 adds the clock signal extracted by the extracting means 11 to the HDL source code 21.
A new HDL source code 22 in which information on the reset signal is added in the form of a comment statement is generated, and the storage device 2
Has the function of storing in

The information display means 13 has a function of displaying the HDL source code 22 to which the comment statement has been added on the display device 4 and a function of highlighting a clock signal and a reset signal designated by the designer. I have.

Recording medium 6 provided in data processing device 1
Is a disk, a semiconductor memory, or another recording medium in which a program for an HDL editor is recorded.
The program for the HDL editor is read by the data processing device 1, and by controlling the operation of the data processing device 1, the extracting means 11, the comment sentence adding means 12, the information display means 13 are provided on the data processing device 1. ,
The text editing means 14 is realized.

FIG. 2 is a flowchart showing a processing example of the data processing apparatus 1. The operation will be described below with reference to the drawings.

When the designer creates the HDL source code,
The HDL source code 21 is input from the keyboard 3 and an editing command is input as needed.

The text editing means 14 stores the HDL source code 21 input from the keyboard 3 in the storage device 2 and edits the HDL source code 21 in accordance with an editing command input from the keyboard 3.

When the HDL source code 21 is completed, the designer inputs from the keyboard 3 an information extraction command for extracting information on the clock signal and the reset signal.

Thus, the extracting means 11 operates, analyzes the HDL source code 21 stored in the storage device 2, and extracts information on the clock signal and the reset signal (S21). Here, the description specific to the clock signal in the HDL source code 21 is detected, and based on the detected description, the clock signal name, the used edge of the clock signal (whether a rising edge or a falling edge is used, or both). Indicates whether an edge is used), the name of the reset signal associated with the clock signal, the polarity of the reset, the label name of the process in which the clock signal is used, and the row where the clock signal and reset signal are described. Extract numbers and so on. After extracting the information on the clock signal and the reset signal, the extracting unit 11 passes the information to the comment adding unit 12.

The comment sentence adding means 12 includes the extracting means 11
When the information about the clock signal and the reset signal is passed from, the information about the signal is arranged in a line in association with the signal name, and the information passed from the extracting means 11 is organized in a legible manner (S22).

Thereafter, the comment sentence adding means 12 generates an HDL source code 22 in which the information arranged above is added to the source code in the form of a comment sentence, and stores it in the storage device 2 (S23).

The designer can highlight the clock signal and the reset signal existing on the HDL source code 22 as necessary (S24). in this case,
The designer first inputs a display command for the HDL source code 22 to which the comment statement has been added. Thus, the information display unit 13 displays the HDL source code 22 on the display device 4. Next, the designer specifies a clock signal and a reset signal to be highlighted.
This instruction is performed by, for example, selecting information on a clock signal and a reset signal to be highlighted in the comment text displayed on the display device 4 using a cursor. Thereafter, the designer inputs a highlight display command from the keyboard 3. As a result, the information display unit 13 highlights the specified clock signal and reset signal on the HDL source code 22 displayed on the display device 4. At this time, the label of the process statement including the highlighted clock signal and reset signal may be highlighted.

Further, the designer can print out the HDL source code 22 to which a comment statement has been added as necessary (S25). In this case, the designer inputs a command to print out the HDL source code 22 from the keyboard 3. This allows
The data processing device 1 reads the HDL source code 22 from the storage device 2 and prints out using the printer 5. Since information on the clock signal and the reset signal is added to the HDL source code 22 printed out from the printer 5 in the form of a comment statement, the designer can add information on the clock signal and the reset signal based on the comment statement. You can easily find out.

FIG. 3 is a block diagram showing another example of the configuration of the HDL editor according to the present invention. The data processing unit 31 comprises a computer, a storage unit 32, and a keyboard 33.
, A display device 34, a printer 35, and a recording medium 36.

The keyboard 33 is used for inputting HDL source code and various commands of the HDL editor. The storage device 32 stores HDL source codes 321, 322, 323-1 to 323-n and the like. The display device 34 is used for displaying HDL source code and the like. The printer 35 is an HD
It is used to print out L source code and the like.

The data processing device 31 includes an extraction unit 311
, Comment adding means 312, and information displaying means 313
, Text editing means 314 and hierarchical relation extracting means 31
5 is provided.

The text editing means 314 includes a keyboard 3
3 has a function of storing the HDL source code input from the storage device 32 in the storage device 32 and a function of editing the HDL source code.

The extracting means 311 has a function of inputting the designated HDL source code from the storage device 32 and analyzing the syntax thereof to extract information on the clock signal and the reset signal in the HDL source code.

The hierarchical relation extracting means 315 outputs a higher-level HD indicating the connection of the lower-level block specified by the designer.
It has a function of associating a clock signal and a reset signal in the L source code with information on the clock signal and the reset signal in the lower HDL source code representing the operation of the lower block.

The comment sentence adding means 312 adds information on the clock signal and reset signal extracted by the extracting means 311 to the HDL source code which is currently being processed,
It has a function of creating a new HDL source code in which the result of the association performed by the hierarchical relationship extraction unit 315 is added in the form of a comment statement.

The information display means 313 has a function of displaying the HDL source code specified by the designer on the display device 34 and a function of highlighting the clock signal and the reset signal specified by the designer.

The recording medium 36 provided in the data processing device 31 is a disk, a semiconductor memory, or another recording medium, in which a program for an HDL editor is recorded. The program for the HDL editor is read by the data processing device 31, and by controlling the operation of the data processing device 31, the extracting means 311, the comment sentence adding means 312, the information display means 31
3, text editing means 314, hierarchical relation extracting means 315
To achieve.

FIG. 4 is a flowchart showing a processing example of the data processing device 31 when a hierarchical relation extraction command is input.
The operation will be described below with reference to the drawings.

When the designer uses the keyboard 33 to
When you perform input operation and edit operation of source code,
The same processing as that of the text editing means 14 shown in FIG. 1 is performed in the text editing means 314, and the HDL source code is input and edited. When the designer designates an HDL source code for extracting information on a clock signal and a reset signal and inputs a command for information extraction, the extraction means 311 and the comment statement addition means 312 show in FIG. Extracting means 11, comment adding means 12
New HDL in which information about the clock signal and the reset signal is added in the form of a comment statement
Source code is generated and stored in the storage device 32.

Now, for example, if the designer performs an input operation and an edit operation of the upper HDL source code 321 indicating the connection of the lower block by using the keyboard 33, the text editing unit 314 operates according to the above operation. The upper HDL source code 321 is stored in the storage device 32 and edited.

Thereafter, the designer specifies the clock signal and reset signal of the upper HDL source code 321 and the lower HDL source code 321.
When a hierarchical relationship extraction command designating the HDL source code 321 is input to extract the relationship between the clock signal and the reset signal information of the DL source code, the following processing is performed. At this point,
The lower HDL source code (for example, HDL source codes 323-1 and 323-1) to which a comment statement has already been added.
It is assumed that 3-2) is stored in the storage device 32.

The command for extracting the hierarchical relationship is the keyboard 33
, The hierarchical relation extraction means 315 outputs
Based on the contents of the source code 321, a lower block describing the connection is obtained, and further, the contents of the upper HDL source code 321 stored in the storage device 32 and the lower HDL source code 323-1 , 323-2
And the lower HDL source code 323-1 and 323 based on the clock signal and reset signal of the upper HDL source code 321,
A correspondence relationship between the clock signal of -2 and the information on the reset signal is determined (FIG. 4, S41).

Thereafter, the hierarchical relation extracting means 315 instructs the extracting means 311 to extract information on the clock signal and the reset signal of the upper HDL source code 321.

As a result, the extracting means 311 outputs the upper H
The information related to the clock signal and the reset signal of the DL source code 321 is extracted, and the extracted information is passed to the hierarchical relation extracting unit 315 (S42).

Thereafter, the hierarchical relation extracting means 315 determines whether
1, the information obtained in S42 is passed to the comment sentence adding means 312.

Thus, the comment sentence adding means 312
Generates the HDL source code 322 in which the information passed from the hierarchical relation extracting means 315 is arranged in an easy-to-view form, and the organized information is added in the form of a comment sentence.
2 is stored.

The clock signal and the reset signal in the HDL source code 322 are highlighted,
To print out the DL source code 322, the same operation as described above may be performed.

[0049]

Next, an embodiment of the present invention will be described.

FIGS. 5 and 6 respectively show the HD shown in FIG.
FIG. 3 is a diagram showing an example of L source codes 21 and 22;
The operation at the TL level is described by VHDL.

The designer uses the keyboard 3 and the text editing means 14 to input the HDL source code 2 as shown in FIG.
1 is created and stored in the storage device 2, an information extraction command specifying the HDL source code 21 is input from the keyboard 3.

As a result, the extraction means 11 operates and the HD
Information on the clock signal and the reset signal existing in the L source code 21 is extracted (S21).

In this example, the extraction means 11 first
The clock signal names “CLK_A” and “CLK” are searched by searching for the description “clock signal name 'event” specific to the clock signal existing in the HDL source code 21 shown in FIG.
_B ”and its line numbers“ 18 ”and“ 2 ”.
7 "is extracted. In addition, as the description peculiar to the clock, wai
The same applies when a t statement is used.

Next, the extraction means 11 outputs “CLK_A =“ 0 ”” and “C” following “clock signal name“ event ”.
LK_B = “1” causes the clock signals CLK_A, C
The used edge of LK_B is extracted. In the case of this example, the used edges of the clock signals CLK_A and CLE_B are falling (fall) and rising (rise), respectively.
Becomes

Thereafter, the extraction means 11 outputs the clock signal C
The signal names and polarities of the reset signals related to LK_A and CLK_B are designated by the clock signals CLK_A and CLK, respectively.
_B is extracted from the conditional statement at the same depth as the conditional statement of the clock description in the same process statement. In this example, the signal name “RSET” and the polarity “0” are extracted.

Further, the extracting means 11 extracts the label name of the process statement for associating the clock signal with the reset signal and the row number of the reset signal. In the case of this example, the label names “U1” and “U2” and the line numbers “16”,
“25” is extracted.

When the extracting means 11 extracts the above information on the clock signal and the reset signal, it passes them to the comment sentence adding means 12.

As a result, the comment sentence adding means 12
The passed information is referred to as clock signal names “CLK_A”, “CL
A comment is created by organizing the “K_B” and the reset signal name “RST” (S22). After that, the comment sentence adding means 12 adds the comment sentence COM created in S22 to the HDL source code 21 shown in FIG.
The HDL source code 22 shown in FIG.

"CL" in the comment sentence COM shown in FIG.
“K_A (fall): U1 (L = 27)” is a description of the clock signal CLK_A, and the signal name is “CL”.
K_A ", the used edge is" falling (fall) ",
This shows that the label name of the used process statement is “U1” and the line number used is “27”.
The line number “27” is the same as the line number “1” extracted in S21.
This is obtained by adding the number of lines “9” increased by adding the comment sentence COM to “8”.

Further, "CLK_B (ri
ze): U2 (L = 36) "is the clock signal CLK_
This is a description of B, where the signal name is "CLK_B", the used edge is "rise", the label name of the used process statement is "U2", and the used line number is "36". It is shown that.

Further, "RST (0): U" in the comment sentence
1 (L25), U2 (L34) "are reset signals RS
This is a description of T, the signal name is “RST”, the polarity is “0”, and the label name of the used process statement is “U”.
1 "and" U2 ", and the row numbers are" 25 "and" 34 ".

Next, an operation for highlighting a specific clock signal and reset signal in the HDL source code 22 will be described.

In this case, the designer first sets the keyboard 3
, The display command of the HDL source code 22 is input. As a result, the information display means 13 operates to display the HDL source code 22 to which the comment sentence COM has been added on the display device 4.

Thereafter, the designer sets the HDL source code 2
The information on the clock signal and the reset signal to be highlighted and displayed in the comment COM added to 2 is selected using a cursor or the like. Accordingly, the information display unit 14 highlights the clock signal and the reset signal corresponding to the information selected by the designer. For example, if the user wants to highlight all the used clock signals, the user may select “CLK_A” in the comment text COM.
(Fall): U1 (L = 27) and “CLK_B (r
size): U2 (L = 36) is selected. This allows
The information display unit 13 highlights character strings “CLK_A” and “CLK_B” existing in the HDL source code 22. Note that, in addition to the above-described character string, a label may be highlighted for a process sentence using the signal.

Next, the HDL to which the comment statement is added
The operation when the source code 22 is printed out will be described.

In this case, the designer sends H
A command to print out the DL source code 22 is input. Accordingly, the data processing device 1 reads the HDL source code 22 to which the comment sentence COM has been added from the storage device 2 and outputs the HDL source code 22 to the printer 5.

Next, another embodiment of the present invention will be described.

FIG. 7 is a diagram showing an example of the HDL source code 321 shown in FIG. 3, and the connection of the lower blocks is represented by a VHDL description.

The block name of the HDL source code 321 shown in FIG. 7 is “TOP” and has two lower blocks “TEST” and “TEST2”. The unique names of the blocks “TOP” of the lower blocks “TEST” and “TEST2” are “BLOCK1”,
"BLOCK2".

When the designer creates the upper HDL source code 321 as shown in FIG.
A hierarchical relation extraction command specifying the L source code 321 is input.

As a result, the hierarchical relation extracting means 315 operates to obtain the lower block in which the connection is described based on the contents of the HDL source code 321, and
The contents of the HDL source code 321 and the lower HDL source code to which the comment statement has already been added (the HDL source code describing the operation of the lower blocks “TEST” and “TEST2”. Source code 321-1, 321-2), the clock signal and reset signal of the HDL source code 321 and the HDL source code 323-
Correspondence with the information about the clock signal and the reset signal of 1,323-2 is determined (FIG. 4, S41).

The processing in S41 will be described in detail as follows.

The hierarchical relation extracting means 315 first refers to the port map statement of the “TOP” description in the HDL source code 321 shown in FIG. The blocks are “TEST” and “TEST2”, and the block name is “BL”.
OCK1 "and" BLOCK2 ".

Next, the hierarchical relation extracting means 315 extracts comments from lower HDL source codes 323-1 and 323-2 in which the operations of the lower blocks “TEST” and “TEST 2” are described and comment statements are added. Get the contents of a sentence.

Here, in the hierarchical relation extracting means 315, the HDL source codes 323-1 and 323-2 describe the operations of the lower blocks "TEST" and "TEST2", and a comment statement is added. It is necessary to be able to recognize that the HDL source code is the HDL source code. For example, the HDL source code of the lower block to which the comment statement has been added is stored in the file name “entity name of lower block.vh”.
By storing the information in a file “dl”, it can be made recognizable. Here, vhdl is an extension. That is, in this example, the HDL source codes 323-1 and 323-2 have the file names “T
EST. vhdl ”and“ TEST2.vhdl ”.
In 15, the lower blocks “TEST” and “TEST2”
Based on the entity name of
The HDL source code in which the operations of “T” and “TEST2” are described and a comment statement is added is stored in a file with the file name “TEST.vhdl” or “TEST2.vhdl”.
1,323-2.

After that, the hierarchical relation extracting means 315 outputs the information on the clock signal and the reset signal indicated by the comment statement in the lower HDL source codes 323-1 and 323-2, the clock signal of the upper HDL source code 321 and the reset signal. Find the correspondence with the reset signal.

Now, for example, assuming that the contents of the HDL source code 323-1 describing the operation of the lower block “TEST” are as shown in FIG. 6, the comment added to the HDL source code 323-1 From the contents of the statement COM, it can be seen that the clock signals used in the lower block “TEST” are “CLK_A” and “CLK_B” and the reset signal is “RST”. Further, FIG.
Port of the upper HDL source code 321 shown in
From the map statement, “CLK_A” and “CLK_B” are “T
In the HDL source code 321 of "OP", it can be seen that they are connected to "ACLK" and "BCLK", respectively, and that "RST" is connected to "TRST".

Therefore, the upper HDL source code 321
The relationship between the clock signal and the reset signal shown in FIG. 6 and the information about the clock signal and the reset signal (the information about the clock signal and the reset signal of the block “TEST”) indicated by the comment sentence in FIG. 6 is as follows.

A. “ACLK” is the block “TES”
T regarding the clock signal “CLK_A” of “T”
K_A (fall): U1 (L27). " b. “BCLK” is information “CLK_B (riz) related to the clock signal“ CLK_B ”of the block“ TEST ”.
e): U2 (L36) ". c. “TRST” is information “RST (0): U1 (L) related to the reset signal“ RST ”of the block“ TEST ”.
= 25), U2 (L = 34) ".

The hierarchical relation extracting means 315 performs such processing by using the HDL source code 32 in which the operation of the lower block “TEST2” is described and a comment statement is added.
3-2, the upper HDL source code 32
1 and the information on the clock signal and the reset signal (the information on the clock signal and the reset signal of the block “TEST2”) indicated by the comment statement in the lower HDL source code 323-2. Ask for a relationship. The above is the details of the processing performed in S41.

Thereafter, the hierarchical relation extracting means 315 instructs the extracting means 311 to extract information on the clock signal and the reset signal of the upper HDL source code 321.

Thus, the extracting means 311 outputs the upper H
The information related to the clock signal and the reset signal of the DL source code 321 is extracted, and the extracted information is passed to the hierarchical relation extracting unit 315 (S42). In the case of the example shown in FIG. 7, the description "clock signal name 'ev
Since “ent” does not exist, no information relating to the clock signal and the reset signal is extracted, and the extracting means 311 notifies the hierarchical relation extracting means 315 of this.

Thereafter, the hierarchical relation extracting means 315 determines whether
1, the information obtained in S42 and the information indicating the upper HDL source code 321 are passed to the comment sentence adding means 312.
In this case, since information relating to the clock signal and the reset signal is not extracted in S42, the information extracted in S41 and the information indicating the HDL source code 321 are passed to the comment sentence adding unit 312.

Thus, the comment sentence adding means 312
Is an HDL in which the information passed from the hierarchical relation extracting means 315 is arranged in an easy-to-view form, and the information arranged above is added to the description of the HDL source code 321 in the form of a comment statement.
The source code 322 is generated and stored in the storage device 32 (S43, S44).

FIG. 8 is a diagram showing an example of the HDL source code 322 to which a comment sentence has been added by the comment sentence adding means 312. In this example, a comment sentence COM1 regarding the hierarchy, a comment sentence COM2 regarding the relationship between the clock signal hierarchies, and a comment sentence COM3 regarding the relationship between the reset signal hierarchies are added.

In the comment sentence COM1, the upper block “TOP” is divided into two blocks “TEST” and “TES”.
T2 "and their names are" BLOCK1 ", BLOCK
K2 ".

“ACLK: TE” in the comment sentence COM2
“ST (CLK_A (fall))” indicates that the clock signal “ACLK” in the upper block “TOP” corresponds to the clock signal CLK_A in the lower block “TEST”, and its used edge is falling. . Furthermore, “BCLK: TES” in the comment sentence COM2
T (CLK_B (rise)). TEST2 (CLK
(Rise)) indicates that the clock signal “BCLK” in the upper block “TOP” is equal to the clock signal “CL” in the lower block “TEST” whose use edge is rising.
K_B ”and the clock signal“ CLK ”of the lower block“ TEST2 ”whose use edge is rising.

[0088]

As described above, the present invention provides an HDL
Information about the clock signal and reset signal used in the source code is added to the source code described in the description language in the form of a comment statement.
Since the information on the clock signal and the reset signal can be easily grasped based on the comment text without referring to other design materials, the productivity of the hardware design can be improved. Further, since information on the clock signal and the reset signal is added to the source code in the form of a comment statement, there is an effect that management becomes easy.

Further, according to the present invention, the clock signal and the reset signal designated by the designer are highlighted on the source code, so that the designer can easily find a problem in logic and timing. Therefore, backtracking in logic verification and timing verification is reduced, and the productivity of hardware design is improved.

Further, according to the present invention, a hierarchy for generating a source code in which a correspondence between a clock signal and a reset signal in an upper source code and information on a lower block clock signal and a reset signal are added in the form of a comment statement is provided. Since the relation extracting means is provided, the designer can easily understand the relation between the clock signal and the reset signal in the upper and lower layers based on the comment text.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an HDL editor according to the present invention.

FIG. 2 is a data processing device 1 when an information extraction command is input.
6 is a flowchart showing an example of the processing of FIG.

FIG. 3 is a block diagram showing another configuration example of the HDL editor of the present invention.

FIG. 4 is a flowchart showing a processing example of a data processing device 31 when a hierarchical relation extraction command is input.

FIG. 5 is a diagram showing an example of an HDL source code 21.

FIG. 6 is a diagram showing an example of an HDL source code 22.

FIG. 7 is a diagram showing an example of an HDL source code 321.

FIG. 8 is a diagram showing an example of an HDL source code 322.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data processing apparatus 11 ... Extraction means 12 ... Comment sentence addition means 13 ... Information display means 14 ... Text editing means 2 ... Storage device 21, 22 ... HDL source code 3 ... Keyboard 4 ... Display device 5 ... Printer 6 ... Recording medium Reference Signs List 31 data processing device 311 extracting means 312 comment adding means 313 information displaying means 314 text editing means 315 hierarchical relation extracting means 32 storage devices 321, 322, 323-1 to 323-n HDL source code 33 keyboard 34 display device 35 printer 36 recording medium

Claims (10)

(57) [Claims] 1. An HDL editor for inputting and editing a source code described in a hardware description language, an extracting means for extracting information about a clock signal and a reset signal from a source code described in a hardware description language. An HDL editor comprising: comment statement adding means for generating a source code in which information on the clock signal and reset signal extracted by the extracting means is added in the form of a comment statement. 2. A source code to which a comment sentence is added by the comment sentence adding means, and a designer selects information on a specific clock signal and a reset signal in the comment sentence, thereby displaying the selected information and 2. The HDL according to claim 1, further comprising information display means for highlighting the corresponding clock signal and reset signal.
editor. 3. The HDL editor according to claim 2, wherein said information display means has a configuration for highlighting a label of a process statement including a clock signal and a reset signal to be highlighted. 4. A clock signal extracted by said extracting means,
The HDL editor according to claim 1, wherein the information on the reset signal includes a signal name. 5. A clock signal extracted by said extracting means,
The HDL editor according to claim 4, wherein the information on the reset signal includes a used edge of the clock signal. 6. A clock signal extracted by said extracting means,
6. The HDL editor according to claim 5, wherein the information on the reset signal includes a label name of a statement in which the clock signal and the reset signal are used. 7. A clock signal extracted by said extracting means,
The information on the reset signal includes a line number of a sentence in which the clock signal and the reset signal are used, and the comment sentence adding unit outputs a comment sentence including a line number corrected based on the number of comment lines to be added. 7. The HDL editor according to claim 6, further comprising an additional configuration. 8. An HDL editor for inputting and editing a source code described in a hardware description language, comprising: extraction means for extracting information about a clock signal and a reset signal from the source code described in the hardware description language. Comment statement adding means for generating a source code in which information on the clock signal and reset signal extracted by the extracting means is added in the form of a comment statement; contents of an upper source code indicating a connection of a lower block; A clock signal and a reset signal in the upper-level source code, based on a comment sentence indicating information on the clock signal and the reset signal of the lower-level block added to the lower-level source code indicating the operation of the block. The correspondence between the clock signal and reset signal information of the lower block is extracted. And a hierarchical relation extracting means for generating a source code in which the extracted correspondence is added in the form of a comment sentence.
L editor. 9. A recording medium storing a program for causing a computer to operate as an HDL editor for inputting and editing source code described in a hardware description language, wherein the computer is described in a hardware description language. Extracting means for extracting information relating to a clock signal and a reset signal from the extracted source code, as comment statement adding means for generating source code in which information relating to the clock signal and the reset signal extracted by the extracting means is added in the form of a comment statement A machine-readable recording medium on which a program for functioning is recorded. 10. The computer is displayed by displaying a source code to which a comment sentence is added by the comment sentence adding means, and a designer selects information on a specific clock signal and a reset signal in the comment sentence. 10. A machine-readable recording medium storing a program according to claim 9, wherein a program for functioning as an information display means for highlighting a clock signal and a reset signal corresponding to the obtained information is recorded.