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JPH0787200B2 - Mounting method of semiconductor chip - Google Patents
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JPH0787200B2 - Mounting method of semiconductor chip - Google Patents

Mounting method of semiconductor chip

Info

Publication number
JPH0787200B2
JPH0787200B2 JP62085005A JP8500587A JPH0787200B2 JP H0787200 B2 JPH0787200 B2 JP H0787200B2 JP 62085005 A JP62085005 A JP 62085005A JP 8500587 A JP8500587 A JP 8500587A JP H0787200 B2 JPH0787200 B2 JP H0787200B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
thermosetting resin
resin layer
connection
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62085005A
Other languages
Japanese (ja)
Other versions
JPS63250140A (en
Inventor
佳久 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62085005A priority Critical patent/JPH0787200B2/en
Publication of JPS63250140A publication Critical patent/JPS63250140A/en
Publication of JPH0787200B2 publication Critical patent/JPH0787200B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Manufacturing Of Electrical Connectors (AREA)
  • Multi-Conductor Connections (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体チップの配線基板への実装方法に関する
もので、特に半導体チップの接続電極を直接配線基板上
の接続電極に接続するフェースダウンボンディング法の
改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor chip on a wiring board, and more particularly to a face-down bonding method for directly connecting the connection electrode of the semiconductor chip to the connection electrode on the wiring board. It is about improvement.

従来の技術 近年、電気回路の小型モジュール化が注目をあびてお
り、特に、半導体チップの実装においても配線基板への
直接搭載の方向へ進んでいる。すなわち、従来、半導体
チップと配線基板との接続には、ワイヤーボンディング
法が主流であったが、配線基板上における半導体チップ
接続のための面積等の効率化から、フェースダウンボン
ディング法が見直されている。
2. Description of the Related Art In recent years, attention has been paid to miniaturization of electric circuits, and in particular, even in the mounting of semiconductor chips, there is a tendency toward direct mounting on a wiring board. That is, conventionally, the wire bonding method has been mainly used for the connection between the semiconductor chip and the wiring substrate, but the face-down bonding method has been reconsidered because of the efficiency of the area for connecting the semiconductor chip on the wiring substrate. There is.

このフェースダウンボンディング法においては、通常半
導体チップの接続電極の上には、バンプと呼ばれる突起
電極が形成されており、このバンプと配線基板の導電電
極とを対向させ、リフロー等により一括ボンディングさ
れる。
In this face-down bonding method, a bump electrode called a bump is usually formed on the connection electrode of the semiconductor chip, and the bump and the conductive electrode of the wiring substrate are opposed to each other and are collectively bonded by reflow or the like. .

次に、このバンプの形成工程の代表例を、第2図を用い
て説明する。通常半導体チップ1は、a図に示すように
接続電極2の回りを表面保護層3が覆うように形成され
ている。この半導体チップ1にb図に示すように、スパ
ッタあるいは蒸着により、Tiよりなる拡散防止層5とCu
よりなる接着層6を形成する。しかる後、c図に示すよ
うに前もって、表面保護層3の設けられていない区域を
略々残してフォトレジスト層7を形成し、その上にd図
に示すようにAuメッキ層8を形成し、e図に示すように
フォトレジスト層7を剥離、Ti,Cu層をエッチングし、
熱処理工程を通して形成される。以上のように形成され
たバンプは、配線基板上の導電電極と超音波加熱方式等
により直接接続される。
Next, a representative example of the bump forming process will be described with reference to FIG. Usually, the semiconductor chip 1 is formed so that the surface protection layer 3 covers the periphery of the connection electrode 2 as shown in FIG. As shown in FIG. 2B, the semiconductor chip 1 is formed by sputtering or vapor deposition with a diffusion prevention layer 5 made of Ti and Cu.
The adhesive layer 6 is formed. Then, as shown in FIG. 7C, a photoresist layer 7 is formed in advance, leaving a region where the surface protective layer 3 is not provided, and an Au plating layer 8 is formed thereon as shown in FIG. , The photoresist layer 7 is peeled off as shown in FIG.
It is formed through a heat treatment process. The bumps formed as described above are directly connected to the conductive electrodes on the wiring board by an ultrasonic heating method or the like.

発明が解決しようとする問題点 しかしながら、上記のような方法では、バンプ形成に多
くの工程を通らねばならず、チップコストの面で不利で
あり、また、フォトレジスト,エッチング工程を通るた
め、イオン等による半導体チップへの悪影響,信頼性の
低下等の問題点を有していた。
Problems to be Solved by the Invention However, in the method as described above, many steps must be performed for bump formation, which is disadvantageous in terms of chip cost, and because the photoresist and etching steps are performed, the ion However, there are problems such as adverse effects on the semiconductor chip due to the above, and deterioration of reliability.

本発明は上記問題点に鑑み、短い工程でしかも安価で信
頼性の高い接続方法を提供するものである。
In view of the above problems, the present invention provides an inexpensive and highly reliable connection method with a short process.

問題点を解決するための手段 この目的を達成するために、本発明の半導体チップの実
装方法は、半導体チップの接続電極が形成されている表
面に、少なくとも前記接続電極を覆うように金属フィラ
ーが混入された感光性の熱硬化性樹脂層を形成した後、
前記接続電極上の前記熱硬化性樹脂層を残して他の熱硬
化性樹脂層をフォトリゾ工法により除去し、その接続電
極上にのみ熱硬化性樹脂層が形成された半導体チップ
を、熱硬化性樹脂層が配線基板の導電電極上に位置する
ように載置し、加熱圧着することにより前記熱硬化性樹
脂を介して前記接続電極と導電電極との電気的および機
械的な接続を行うものである。
Means for Solving the Problems In order to achieve this object, a method for mounting a semiconductor chip of the present invention is such that a metal filler is provided on a surface of a semiconductor chip on which connection electrodes are formed so as to cover at least the connection electrodes. After forming the mixed photosensitive thermosetting resin layer,
Other thermosetting resin layers are removed by a photolithography method while leaving the thermosetting resin layer on the connection electrode, and the semiconductor chip having the thermosetting resin layer formed only on the connection electrode is thermoset. The resin layer is placed so that it is located on the conductive electrode of the wiring board, and the connection electrode and the conductive electrode are electrically and mechanically connected via the thermosetting resin by thermocompression bonding. is there.

作用 この構成によると、金属フィラーが混入された感光性の
熱硬化性樹脂を使用しているため、フォトリゾ工法によ
りスクリーン印刷法に比べてより精度よく半導体チップ
の接続電極上にのみ選択的に熱硬化性樹脂層を形成する
ことができ、従来のようにバンプ形成のための工程が簡
素化され、信頼性の高い接続が可能となる。
Function According to this structure, since the photosensitive thermosetting resin mixed with the metal filler is used, the photolithography method selectively heats only the connecting electrodes of the semiconductor chip more accurately than the screen printing method. The curable resin layer can be formed, the process for bump formation can be simplified as in the conventional case, and highly reliable connection can be achieved.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。第1図は本実施例における実装方法の代表的
な工程図を示すものであり、従来構成と同一構成部分に
は、同一符号を付して示している。
Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a typical process diagram of the mounting method in this embodiment, and the same components as those of the conventional configuration are designated by the same reference numerals.

第1図において4は、金属フィラーを含有する感光性樹
脂層、10は導電電極、11は配線基板である。以下、その
工程について説明する。まず、a図に示すように、半導
体チップ1の表面に金属フィラーを含有する感光性樹脂
4を均一に塗布する。ここで、金属フィラーは、Ag,Ni,
Cuなど導電体材料の単体あるいは混合体から成り、粒径
は約2〜10μmφである。また、感光性樹脂は、エポキ
シあるいはポリイミドなどを基本骨格にもつ熱硬化性樹
脂であり、金属フィラーとの混合比は、体積比で40〜80
%である。
In FIG. 1, 4 is a photosensitive resin layer containing a metal filler, 10 is a conductive electrode, and 11 is a wiring board. The process will be described below. First, as shown in FIG. A, the photosensitive resin 4 containing a metal filler is uniformly applied to the surface of the semiconductor chip 1. Here, the metal filler is Ag, Ni,
It is composed of a single material or a mixture of conductive materials such as Cu, and has a particle size of about 2 to 10 μmφ. The photosensitive resin is a thermosetting resin having epoxy or polyimide as a basic skeleton, and the mixing ratio with the metal filler is 40 to 80 by volume.
%.

次に、例えば80℃,30分のプリベークを行ない半導体チ
ップ1と樹脂層4の接着力を高めた後に、b図に示すよ
うに通常のフォトリソ工程により、露光,現像等行な
い、接続電極2上に所望の樹脂層9を残す。そしてc図
に示すように、配線基板11の所定の導電電極10と、前記
樹脂層9が一致するよう整合させた後、加熱圧着を行な
い、その両者を接続させる。
Next, for example, after prebaking at 80 ° C. for 30 minutes to increase the adhesive force between the semiconductor chip 1 and the resin layer 4, exposure and development are performed by a normal photolithography process as shown in FIG. The desired resin layer 9 is left on. Then, as shown in FIG. 7C, after the predetermined conductive electrodes 10 of the wiring board 11 and the resin layer 9 are aligned with each other, thermocompression bonding is performed to connect them.

以上のように、本実施例によれば、短い工程で簡単にフ
ェースダウンボンディング法により、配線基板と半導体
チップとを接続することができる。また、信頼性におい
ても、高温高湿(60℃,90%RH)試験で1000時間,高温
放置(100℃)試験で1000時間、ヒートサイクル(−10
℃〜100℃)試験で100サイクル等、通常のワイヤーボン
ディング法と遜色のないものであった。
As described above, according to the present embodiment, the wiring substrate and the semiconductor chip can be easily connected by the face-down bonding method in a short process. In terms of reliability, the high temperature and high humidity (60 ℃, 90% RH) test is 1000 hours, the high temperature storage (100 ℃) test is 1000 hours, and the heat cycle (-10
℃ ~ 100 ℃) test, 100 cycles, etc., was comparable to the normal wire bonding method.

発明の効果 以上のように本発明によれば、金属フィラーの混入され
た熱硬化性樹脂を使用することにより、フォトリゾ工法
により、半導体チップの接続電極上にのみ選択的に熱硬
化性樹脂層を形成することができ、従来のようにバンプ
形成のための工程が簡素化され、信頼性の高い接続が可
能となる。
EFFECTS OF THE INVENTION As described above, according to the present invention, by using a thermosetting resin mixed with a metal filler, by the photolithography method, a thermosetting resin layer is selectively formed only on the connection electrodes of the semiconductor chip. It can be formed, the process for forming bumps can be simplified as in the conventional case, and highly reliable connection can be achieved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の半導体チップの実装方法の一実施例に
おける主要工程を示す図、第2図は従来の半導体チップ
へのバンプ形成における主要工程を示す図である。 1……半導体チップ、2……接続電極、3……表面保護
層、4,9……金属フィラー含有樹脂層、5……拡散防止
層、6……接着層、7……フォトレジスト層、8……バ
ンプ、10……導電電極、11……配線基板。
FIG. 1 is a view showing main steps in an embodiment of a semiconductor chip mounting method of the present invention, and FIG. 2 is a view showing main steps in forming bumps on a conventional semiconductor chip. 1 ... Semiconductor chip, 2 ... Connection electrode, 3 ... Surface protection layer, 4,9 ... Metal filler containing resin layer, 5 ... Diffusion prevention layer, 6 ... Adhesive layer, 7 ... Photoresist layer, 8 ... Bump, 10 ... Conductive electrode, 11 ... Wiring board.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体チップの接続電極が形成されている
表面に、少なくとも前記接続電極を覆うように金属フィ
ラーが混入された感光性の熱硬化性樹脂層を形成した
後、前記接続電極上の前記熱硬化性樹脂層を残して他の
熱硬化性樹脂層をフォトリゾ工法により除去し、その接
続電極上にのみ熱硬化性樹脂層が形成された半導体チッ
プを、熱硬化性樹脂層が配線基板の導電電極上に位置す
るように載置し、加熱圧着することにより前記熱硬化性
樹脂を介して前記接続電極と導電電極との電気的および
機械的な接続を行う半導体チップの実装方法。
1. A photosensitive thermosetting resin layer mixed with a metal filler is formed on a surface of a semiconductor chip on which connection electrodes are formed, so that at least the connection electrodes are covered with the photosensitive thermosetting resin layer. The other thermosetting resin layer is left by the photolithography method while leaving the thermosetting resin layer, and the semiconductor chip in which the thermosetting resin layer is formed only on the connection electrode is a wiring board having the thermosetting resin layer. The method for mounting a semiconductor chip in which the connection electrode and the conductive electrode are electrically and mechanically connected to each other through the thermosetting resin by placing the semiconductor chip on the conductive electrode and thermocompression bonding.
JP62085005A 1987-04-07 1987-04-07 Mounting method of semiconductor chip Expired - Fee Related JPH0787200B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62085005A JPH0787200B2 (en) 1987-04-07 1987-04-07 Mounting method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62085005A JPH0787200B2 (en) 1987-04-07 1987-04-07 Mounting method of semiconductor chip

Publications (2)

Publication Number Publication Date
JPS63250140A JPS63250140A (en) 1988-10-18
JPH0787200B2 true JPH0787200B2 (en) 1995-09-20

Family

ID=13846614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62085005A Expired - Fee Related JPH0787200B2 (en) 1987-04-07 1987-04-07 Mounting method of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH0787200B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4994098B2 (en) * 2007-04-25 2012-08-08 株式会社リコー Semiconductor sensor and manufacturing method thereof
CN112822866B (en) * 2021-01-07 2022-05-27 Tcl华星光电技术有限公司 Solder paste for surface mount, driver circuit board, and surface mount method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4868170A (en) * 1971-12-20 1973-09-17
JPS592179B2 (en) * 1975-03-03 1984-01-17 セイコーエプソン株式会社 Method of manufacturing electrical components
JPS52113196A (en) * 1976-03-18 1977-09-22 Seiko Epson Corp Liquid crystal unit

Also Published As

Publication number Publication date
JPS63250140A (en) 1988-10-18

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