JPH0787442B2 - Information monitor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A monitor device for monitoring status information and inventory information by a common control unit for each of a plurality of line units (channel units) connected to a PCM multiplexing circuit. The number of units can be reduced and the line unit hardware can be configured in a small scale, and in synchronization with the channel clocks supplied to each line unit, each line unit separates from the main signal system data. The information is sent to the common control unit, and the common control unit (12) determines and monitors the information of each line unit based on the frame pulse from the multiplexing circuit.

[Industrial application field]

The present invention relates to what kind of channel board is used for each status information (information indicating the status of equipment) and inventory information for each of a plurality of line units connected to the PCM multiplexing circuit, and what manufacturer. The present invention relates to a monitor device that monitors information indicating whether or not the common control unit.

In the voice PCM transmission line, as shown in FIG. 4, a telephone or an interface circuit 1 (for example, a PBX (Private Branch Exchange Telephone) or a data terminal) is connected to line units 2 ₁ , 2 ₂ , ...
, And after being coded into, for example, an 8-bit PCM signal, the signal is multiplexed by the multiplexing circuit (MUX) 3 and transmitted. In this case, the multiplexing circuit 3 has line units 2 ₁ , 2 ₂ , ... For each telephone or interface circuit, and these line units 2 ₁ , 2 ₂ ,. Various channel boards have been demanded.

In such a transmission line system that handles many types of line units, it becomes difficult to manage each line unit on the station side. Therefore, in recent years, there has been a strong demand for monitoring status information and inventory information for each line unit with a common control unit (BCU: Bank Control Unit).

[Conventional technology]

FIG. 5 is a diagram generally showing how a main signal is exchanged between a multiplexing circuit and a line unit, and FIG. 6 is an operation timing chart thereof. In FIG. 5, a plurality of line units (channel units) 2 ₁ , 2 ₂ , ... Are connected to the MUX 3, for example, the main clock of 1.544 MHz (FIG. 6 (A)) and the channel number of the line unit. The channel clock shown (FIG. 6 (B) shows the channel clock of the line unit 2 ₁ ) is shown in each line unit 2 ₁ , 2 ₂ ,
Is being sent to. The channel clocks are sequentially output from the reference point sequentially with different phases for each line unit. PC from line unit 2 ₁ , 2 ₂ , ...
The M-coded PCM data (the solid line in FIG. 6C indicates the PCM data of the line unit 2 ₁ and the broken line indicates the timing of the PCM data of the line unit 2 ₂ ) is the phase of each channel clock. It is taken out synchronously, supplied to MUX3, and multiplexed there with a carrier. The above is the state of the main signal exchange.

FIG. 7 shows a block diagram of a conventional example in which the BCU monitors the status information and inventory information of each line unit. In the figure, the address of each line unit is set by a so-called addressing pin setting method in which a level of 1 or 0 is set to a plurality of pin terminals in combination. Line unit 2 ₁ has 4 pin terminals, for example +5
V, earth, earth, + giving 5V is set to the address of "1001", for example, the line unit 2 ₂ The four pin terminals + 5V, ground, + 5V, giving ground "1010"
Is set to the address. Line unit 2 ₁ , 2 ₂ ,…
Each CPU 4 _1, 4 ₂ are provided, each CPU 4 _1, 4 _2, ... recognizes their addresses by pins. The ROM 5 ₁ , 5 ₂ stores status information or inventory information for each line unit.

The number of pin terminals of each line unit increases as the number of line units increases.

Here, when the status information or inventory information of the line unit is monitored by the common control unit (BCU) 6, the CPU 7 in the BCU 6 accesses the address of the predetermined line unit. Since each CPU 4 ₁ , 4 ₂ , ... recognizes its own address, each CPU 4 ₁ , 4 ₂ , ... can judge whether the address accessed from the BCU 6 corresponds to each individual, and the corresponding line unit From the CPU of each R in synchronization with the clock
Status information or inventory information for each line unit in the OM is sent out and taken into BCU6.

[Problems to be Solved by the Invention]

In the above-mentioned conventional example, each line unit needs a pin terminal for address setting, and when there are many line units, the number of pin terminals is large, and the line unit cannot be miniaturized. Also, each line unit requires a CPU for recognizing its own address,
There was a problem that the hardware became large-scale.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information monitor device which can be reduced in size by reducing the number of pins of a line unit and which can configure the hardware of the line unit in a small scale.

[Means for Solving the Problems]

FIG. 1 shows a principle block diagram of the device of the present invention. In the figure,
10 is a multiplexing circuit, which is a main lock and each line unit
11 _1, 11 _2, the line unit 11 ₁ channel clock indicating a channel number of ..., 11 _2, and sends to .... Multiplexing circuit 10PC
M data is multiplexed and transmitted. Line unit 11 ₁ , 1
1 _2, ... are transmitted in the main signal system data in synchronism with the channel clock having different phases to be supplied each line unit 11 _1, 11 ₂ to the multiplexing circuit 10, from ... from the multiplexing circuit (10) At the same time, the information (status information or inventory information) different from the main signal system data is sent to the common control section (12) in synchronization with the channel clock. The common control unit 12 judges each line unit 11 ₁ , 11c ₂ , ... With reference to the frame pulse from the multiplexing circuit 10 and monitors the other information.

[Action]

Using the channel clock from the multiplexing circuit 10 used for data transfer of the main signal system, each line unit 11 ₁ , 11 ₂ ,
, And sends the other information to the common control unit 12 in synchronization with the channel clock. In the common control unit 12, the multiplexing circuit 10
Based on the frame pulse from each line unit 11 ₁ , 11
_2, to determine ..., each line unit 11 _1, 11 _2, ... to monitor the specific information for each. As described above, in the common controller 12, each line unit 11 ₁ ,
Since 11 ₂ , ... can be judged, each line unit does not need a pin terminal for address setting as in the conventional example,
Further, each line unit does not need a CPU for recognizing its own address set by the pin terminal.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the device of the present invention, and FIG. 3 shows an operation timing chart of the present invention. In FIG. 2, reference numeral 10 is a multiplexing circuit (MUX), to which a plurality of line units 11 ₁ , 11 ₂ , ...
The main clock of Hz (FIG. 3 (A)) and the channel clock indicating the channel number of each line unit 11 ₁ , 11 ₂ , ... (FIG. 3 (B) indicates the channel clock of line unit 11 ₁ ) It is sent to the line units 11 ₁ , 11 ₂ , .... The channel clocks are sequentially and sequentially output with different phases for each line unit with reference to a frame pulse (FIG. 3 (E)) serving as a reference point. The PCM data which is the main signal from the line units 11 ₁ , 11 ₂ , ... (The solid line in FIG. 3C is the line unit 11 ₁
PCM data) is taken out in synchronism with each channel clock and multiplexed by MUX10. The line units 11 ₁ , 11 ₂ , ... Are not provided with a CPU as in the conventional example.

A common control unit (BCU) 12 is supplied with a main clock and a frame pulse extracted from the MUX 10 as described later, and each line unit is based on this frame pulse.
11 ₁ , 11 ₂ , ... are judged. Also, each line unit 11 ₁ , 11 ₂ ,
From here, status information or inventory information is sent to the BCU 12 at the same timing as the main signal as described later.

Here, the operation of the device of the present invention will be described with reference to FIGS. 2 and 3.

Regarding the transmission of the PCM data of the main signal system, the line units 11 ₁ , 11 ₂ , ... Are synchronized with the channel clock (FIG. 3 (B)) sent from the MUX 10, as in the conventional example.
The PCM data (the PCM data of the line unit 11 ₁ is the solid line shown in FIG. 3 (C), the PCM data of the line units 11 ₂ and 11 ₃ is the timing shown by the broken line in FIG. 3 (C)) is taken out, and is output to the MUX 10. Supplied and multiplexed.

On the other hand, as shown in FIG. 2, each line unit 11 ₁ , 11 ₂ , ...
Are supplied with a channel clock and a main clock, and both of these clocks are ANDed by AND gates 13 ₁ , ... And used as shift register drive control clocks, and are supplied to shift registers 14 ₁ ,. That is, the shift registers 14 ₁ , ... Of each line unit 11 ₁ , 11 ₂ , ... Are driven by the shift register drive control clock only when the channel clock of their own line unit comes in. As a result, the status information or inventory information (indicated by the information ~) peculiar to each line unit 11 ₁ , 112 ₂ , ... Is shifted by the shift register 14 ₁ ,. It is output to the information bus 16 via ₁ , ...

That is, the line units 11 ₁ , 11 ₂ , ... Use the channel clock of the main signal system to unique status information or inventory information (the solid line in FIG. 3D indicates the line unit 11 ₁
, The information from the line units 11 ₂ , 11 ₃ , ... Is taken out at the timing of the broken line), and these are sequentially output in synchronization with the channel clock.

The status information of each line unit sent to the information bus 16 is serial / parallel converted by the shift register (serial / parallel converter) 17 of the BCU 12 and stored in the RAM 18. In this case, a frame pulse (FIG. 3 (E)) is supplied from the MUX 10 to the CPU 19 provided in the BCU 12, and the CPU 19 uses each line unit 11 ₁ , 11 ₂ , ..., Based on the generation timing of the frame pulse.
The status information or inventory information of each line unit 11 ₁ , 11 ₂ , ... Is written in the RAM 18. In this way, the CPU 19 controls each line unit based on the frame path generation timing.
The contents of the status information or the inventory information of the predetermined line unit can be read from the RAM 18, 11 ₁ , 11 ₂ , ... The ROM 20 is a memory in which the operation program of the CPU 19 is set.

〔The invention's effect〕

As described above, according to the present invention, since the common control unit can determine each line unit based on the frame pulse, each line unit does not need a pin terminal for address setting unlike the conventional example, The line unit can be miniaturized, and each line unit does not require a CPU for recognizing its own address set by a pin terminal, and its hardware scale can be small.

[Brief description of drawings]

1 is a block diagram of the principle of the device of the present invention, FIG. 2 is a block diagram of an embodiment of the device of the present invention, FIG. 3 is an operation timing chart of the present invention, and FIG. 4 is provided with a plurality of line units. FIG. 5 is a block diagram of a voice PCM transmission system, FIG. 5 is a diagram showing a main signal exchange between a general MUX and a line unit, FIG. 6 is an operation timing chart of the block diagram shown in FIG. 5, and FIG. It is a block diagram. In the figure, 10 is a multiplexing circuit, (MUX), 11 ₁ , 11 ₂ , 11 ₃ , ... are line units (channel units), 12 is a common control unit (BCU), 13 ₁ is an AND gate, 14 ₁ , 17 Is a shift register, 16 is an information bus, 18 is RAM, and 19 is a CPU.

Claims (1)

[Claims] 1. A multiplexer circuit (10) sequentially supplies channel clocks having different phases to a plurality of line units (11 ₁ , 11 ₂ , ...), and the line units (11 ₁ , 11 ₂ ,
...) to send the main signal system data to the multiplexing circuit (10) in synchronization with the respective channel clocks, and the main signal system data in the line units (11 ₁ , 11 ₂ , ...) is in information monitoring apparatus for monitoring the different information in the common control unit (12), each line unit (11 _1, 11 _2, ...) in synchronization with the channel clock respectively supplied each line unit (11 ₁ , 11 ₂ , ...) sends the other information to the common control section (12), and the common control section (12) causes the multiplexing circuit (1
The information monitor device is configured to judge and monitor the information from each of the line units (11 ₁ , 11 ₂ , ...) On the basis of the frame pulse from (0).