JPH0787444B2 - Bit error protection method - Google Patents

Description

The present invention relates to a bit error protection method for removing an interfering signal from a binary input signal that arrives at a fixed period, and a logical value of the binary input signal is changed by an external interfering signal. In this case, in order not to easily follow the fluctuations of the input signal, the binary input signal arriving at a fixed period is added when it shows one logical value, and when it shows the other logical value. The counting means for subtracting and counting the accumulated value, the accumulating means for accumulating the accumulated value counted by the counting means, the accumulated value is compared with a predetermined reference value, and the accumulated value reaches the reference value. In the case where the input signal indicating one of the logical values is input in the state where the output signal is output by the comparing means that outputs the output signal in the case of
Setting means for setting the accumulated value accumulated by the accumulating means to the upper limit value which is set to be larger than the reference value is provided.

[Industrial application field]

The present invention relates to a bit error protection system that removes an interfering signal from a binary input signal that arrives at regular intervals.

[Conventional technology]

FIG. 4 is a diagram showing an example of the remote control system which is the subject of the present invention, and FIG. 5 is a diagram showing an example of the remote control command in FIG.

In FIG. 4, a plurality of (x) subscribers 3 (individual subscribers are referred to as 3-1 to 3-x, and so on) are provided in a remote device 2 provided at a remote location from the master exchange 1. It is housed.

From the central office switch 1, a remote control command having a structure as shown in FIG. 5 is transmitted from the main station exchange 1 in a predetermined cycle T in order to perform control such as active spare switching of the subscriber circuit accommodating each subscriber 3 for example. Each time, it is transmitted to the remote device 2 via the transmission path 4.

In FIG. 5, the remote control command is composed of a predetermined number of control bits b _{1 to} b _y transmitted for each subscriber corresponding time region S _{1 to} S _x corresponding to each subscriber 3, and each has a predetermined cycle T. It is repeatedly transmitted every time.

Each of the control bits b _{1 to} b _y corresponds to a unique control item, and indicates whether or not to execute the corresponding control according to the logical value of each of the control bits b _{1 to} b _y .

For example, _if the control bit b ₁ in each subscriber corresponding time region S _{1 to} S _x corresponds to the switching control of the working spare of the subscriber circuit, the subscriber corresponding to the subscriber 3-1 in the master exchange 1 is handled. set the logical value of the control bit b ₁ in the time domain S ₁ to a predetermined value (e.g., logic "1"), is transmitted to the remote device 2 through the transmission path 4.

In the remote device 2, a remote control command transmitted from the master exchange 1 via the transmission path 4 at every predetermined cycle T,
Each control bit for each subscriber corresponding time domain is monitored, and when it is detected that the control bit b ₁ in the subscriber corresponding time domain S ₁ has changed from logic “0” to logic “1”, the subscriber 3- The subscriber circuit corresponding to 1 is switched from the working circuit to the protection circuit.

Note that, while the subscriber circuit corresponding to the subscriber 3-1 is not switched, while the control bit b ₁ in the subscriber corresponding time area S ₁ is being transmitted via the transmission path 4, Logic “0” to logic “1” due to interference signals such as noise generated in 4
When it changes to, the remote unit 2 detects the change in the logical value of the control bit b ₁ as described above and executes the switching of the subscriber circuit of the subscriber 3-1.

[Problems to be Solved by the Invention]

As is apparent from the above description, in the conventional remote control system, the remote unit 2 has the control bits b _{1 to} b in the subscriber corresponding time regions S _{1 to} S _x of the remote control command arriving from the transmission path 4. _When the logical value of _y changes, the corresponding control is executed immediately. Therefore, _if the logical values of the control bits b _{1 to} b _y change erroneously due to an interference signal such as noise generated on the transmission path 4, for example. The control irrelevant to the instruction from the master station exchange 1 is executed, and depending on the control item, the system may be seriously affected.

It is an object of the present invention to prevent a logical value of a binary input signal from easily following the fluctuation of the input signal when the logical value of the binary input signal fluctuates due to an external interference signal.

[Means for Solving the Problems]

 FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a counting means provided by the present invention.

200 is a storage means provided by the present invention.

300 is a comparison means provided by the present invention.

400 is a setting means provided by the present invention.

[Action]

The counting means 100 receives a binary input signal i arriving at a constant cycle.
Is added when one of the logical values indicates one, and subtracted when the other logical value is indicated to count the accumulated value n.

The accumulating means 200 accumulates the accumulated value n counted by the counting means 100.

The comparing means 300 compares the accumulated value n with a predetermined reference value th, and outputs the output signal o when the accumulated value n reaches the reference value th.
Is output.

The setting means 400 makes the accumulated value n accumulated by the accumulating means 200 larger than the reference value th when the input signal i indicating one of the logical values is input while the comparing means 300 outputs the output signal o. The upper limit value m is set.

Therefore, the logical value of the input signal changes the logical value of the output signal only when the change of the logical value of the input signal is connected, and invalidation due to frequent fluctuations due to external disturbance of the logical value of the input signal. Control can be prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a signal receiving circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a bit error protection process in FIG. The same reference numerals denote the same objects throughout the drawings. The target remote control system is as shown in FIG. 4, and the target remote control command is as shown in FIG.

In FIG. 2, a counting circuit 21 and an analysis unit 22 are provided as the counting means 100 in FIG. 1, and a memory 23 is provided as the storage means 200 in FIG.
A comparison circuit 24 is provided as the comparison means 300 in the figure,
Further, as the setting means 400 in FIG.
5 and a selector 26 are provided.

In the remote control system shown in FIG. 4, the signal receiving circuit shown in FIG. 2 has the control bits in the subscriber corresponding time regions S _{1 to} S _x corresponding to the respective subscribers 3 in the remote unit 2.
case b ₁ to the ones provided corresponding to b _y, the following description which receives the control bit b ₁ of the subscriber corresponding time domain S ₁ corresponding to the subscriber 3-1 as an input signal i explain.

2 and 3, in the initial state, the cumulative value n accumulated by the counting circuit 21 in the memory 22 is "0" (where "n" is a decimal number), and the cumulative value is cumulative. The flag f stored together with the value n is set to logic "0", and the selection signal s ₁ transmitted from the selection signal generation unit 25 to the selector 26 and the selection signal s ₂ input from the outside to the selector 27 are set. Are both set to logic "0", and the selectors 26 and 27 are both selecting the input terminal A side.

In this state, the binary input signal i arriving from the transmission path 4 every predetermined period T is input to the counting circuit 21, the analysis unit 22, and the selector 27.

The analysis unit 22 controls the counting format of the counting circuit 21 based on the logical value of the input signal i and the accumulated value n stored in the memory 23.

In the first cycle T ₁ , when the input signal i indicates a logic “0” and the accumulated value n indicates “0”, the analysis unit 22 does not cause the counting circuit 21 to perform any counting.

As a result, the counting circuit 21 outputs the accumulated value n (= “0”) output from the memory 23 to the comparison circuit 24 and transmits it to the comparison circuit 24. Input with "0").

The comparison circuit 24 compares the accumulated value n transmitted from the counting circuit 21 with
Since the preset reference value th (“4” in FIG. 3) is compared and the condition n <th is satisfied,
The output comparison signal c is set to logic "0" and input to the selection signal generator 25 and the input terminal A of the selector 27.

The selector 27 has a comparison signal c (=
The logic "0") is output as the output signal o (= logic "0").

The selection signal generation unit 25 selects the selector 26 when either the comparison signal c or the input signal i is set to logic “0”.
Set the selection signal s ₁ to be transmitted to the logic "0".

As a result, the selector 26 stores the accumulated value n (= “0”) and the flag f (= logical “0”) input to the input terminal A in the memory 23.

When the input signal i arriving in the subsequent second cycle T ₂ changes to the logic “1” due to the interference signal from the outside, the analysis unit 22 indicates that the input signal i indicates the logic “1” and the accumulated value n (= Since “0”) is less than the upper limit value m (“8” in FIG. 3) that is set in advance larger than the reference value th (= “4”),
The counting circuit 21 is caused to count “+1”.

As a result, the counting circuit 21 adds "1" to the accumulated value n (= "0") output from the memory 23 and outputs n (= "1").

The comparison circuit 24 uses the accumulated value n and the reference value th (=
"4") is compared, and the condition n <th is still satisfied, the comparison signal c to be output is set to logic "0".

As a result, the output signal o output from the selector 27 is maintained at the logic "0".

Since the selection signal generator 25 sets the selection signal s ₁ to be output to logic “0” because the comparison signal c is logic “0”, the accumulated value n (= “1” is stored in the memory 23). )) And flag f (= logical “0”) are stored via selector 26.

When the input signal i arriving in the subsequent third cycle T ₃ is also connected to the logic “1” by the interfering signal, the analysis unit 22 indicates that the input signal i indicates the logic “1” and the accumulated value n (= “1”). Is less than the upper limit value m, the counting circuit 21 is instructed to count “+1”, and the counting circuit 21 adds “1” to the accumulated value n (= “1”) to accumulate the accumulated value n ( = “2”), and the comparison circuit 24 still outputs the condition n.
Since <th is satisfied, the output comparison signal c is set to logic “0”, and as a result, the output signal o is still set to logic “0”, and the selection signal s ₁ is also set to logic “0”. Therefore, the accumulated value n (= “2”) and the flag f are stored in the memory 23.
(= Logical “0”) is stored.

When the effect of the interfering signal is removed in the subsequent fourth cycle T ₄ and the arriving input signal i returns to logic “0”, the analysis unit 22 indicates that the input signal i indicates logic “0” and the accumulated value n ( = “2”) is greater than “0”, the counting circuit 21 is caused to count “−1”.

As a result, the counting circuit 21 subtracts “1” from the accumulated value n (= “2”) output from the memory 23 and outputs n (= “1”), and the comparison circuit 24 is the same as described above. The accumulated value n and the reference value
Compared with th (= “4”) and the condition n <th is still satisfied, the output comparison signal c is set to logic “0”.

As a result, the output signal o output from the selector 27 maintains the logic “0”, and the selection signal s ₁ output from the selection signal generator 25 is also set to the logic “0”. Stores a cumulative value n (= “1”) and a flag f (= logical “0”).

When the input signal i arriving in the subsequent fifth cycle T ₅ is also connected to the logic “0”, the analysis unit 22 indicates that the input signal i indicates the logic “0” and the accumulated value n (= “1”) is “0”. Since it is larger than “”, the counting circuit 21 is instructed to count “−1”, and the counting circuit 21 subtracts “1” from the accumulated value n (= “1”) to calculate the accumulated value n (=
"0") and the comparison circuit 24 still satisfies the condition n <th. Therefore, the comparison signal c to be output is set to logic "0", and as a result, the output signal o is also set to logic "0". Since the selection signal s ₁ is also set to logic “0”, the memory
A cumulative value n (= “0”) and a flag f (= logical “0”) are stored in 23.

When the input signal i arriving at the subsequent sixth cycle T ₆ is also connected to the logic “0”, the analysis unit 22 does not cause the counting circuit 21 to perform any counting, as in the first cycle T ₁ , and thus the output signal i o is set to logic "0", and the accumulated value n (= "0") and the flag f (= logic "0") are stored in the memory 23.

After the subsequent seventh cycle T ₇ , in order to execute the switching control of the subscriber circuit of the subscriber 3-1 from the master exchange 1, the control bit b ₁
The set to a logic "1", also becomes possible to set to a logic "1" input signal i to arrive after the seventh cycle T _7, the second period
As in T ₂ and the third period T ₃ , the analysis unit 22 instructs the counting circuit 21 to count “+1”, and the counting circuit 21 outputs “1” to the accumulated value n output from the memory 23. Are sequentially added, and as a result, the accumulated value n increases to “1”, and the tenth cycle T ₁₀
Reaches "4" at.

Comparison circuit 24, until the ninth cycle T ₉ are accumulated value n is the reference value th (=
Since it is less than “4”), the output comparison signal c is set to logic “0”, but the accumulated value n reaches the reference value th (= “4”) in the tenth cycle T ₁₀ . If the condition n ≧ th holds,
The output comparison signal c is set to logic "1".

As a result, the selector 27 sets the output signal o to the logic "1" in the tenth cycle T ₁₀ .

When both the input signal i and the comparison signal c input from the comparison circuit 24 are set to logic “1”, the selection signal generation unit 25 sets the selection signal s ₁ to be transmitted to the selector 26 to logic “ ₁ ”. 1 "
Set to.

When the selection signal s ₁ input from the selection signal generation unit 25 is set to logic “1”, the selector 26 inputs the upper limit value m (= “8”) and the flag f (= “8”) input to the input terminal B side. The logical “1”) is stored in the memory 23.

When the input signal i arriving at the eleventh cycle T ₁₁ is still set to the logic “1”, the analysis unit 22 indicates that the input signal i indicates the logic “1” and the accumulated value n output from the memory 23 is n. Is the upper limit value m (=
When "8") is indicated, the counting circuit 21 is not allowed to perform any counting.

As a result, the counting circuit 21 outputs the accumulated value n (= upper limit value m = “8”) output from the memory 23 on its side.

The comparison circuit 24 compares the accumulated value n (= upper limit value m = “8”) with the reference value th (= “4”), and the condition n ≧ th is still satisfied. Is maintained at logic "1".

As a result, the output signal o output from the selector 27 maintains the logic “1”, and the selection signal s ₁ output from the selection signal generator 25 is also set to the logic “1”. Is the upper limit value m (= “8”) and flag f (= logical “1”)
Is stored.

When the input signal i arriving at the subsequent twelfth cycle T ₁₂ changes from the interference signal to the logic “0”, the analysis unit 22 indicates that the input signal i indicates the logic “0” and the accumulated value n (= upper limit value). Since m = “8”) is larger than “0”, the counting circuit 21 is caused to count “−1” as in the fourth cycle T ₄ and the fifth cycle T ₅ .

As a result, the counting circuit 21 subtracts “1” from the accumulated value n (upper limit value m = “8”) output from the memory 23 to obtain n (=
"7") is output.

The comparison circuit 27 compares the accumulated value n (= “7”) with the reference value th (= “4”) in the same manner as described above, and the condition n ≧ th is still satisfied. Is set to logic "1".

As a result, the output signal o output from the selector 27 maintains the logic "1".

On the other hand, the selection signal generation unit 25 always sets the selection signal s ₁ to the logic “0” when the input signal i is set to the logic “0”.

As a result, the selector 26 selects the input terminal A side and stores the accumulated value n (= “7”) output from the counting circuit 21 in the memory 23 together with the flag f (= logical “0”).

Continued the thirteenth input signal i arriving to the period T ₁₃ is also connected a logic "0, the analysis unit 22 instructs the counting of" -1 "to the counter circuit 21 as in the twelfth cycle T _12, the counting The circuit 21 subtracts “1” from the accumulated value n (= “7”) to calculate the accumulated value n.
(= "6") is output, and the comparison circuit 24 outputs the accumulated value n (=
“6”) is compared with the reference value th (= “4”), and since the condition n ≧ th is still satisfied, the output comparison signal c is set to logic “1”, and as a result, the output signal o is also set. Since the logic signal is still set to the logic "1" and the selection signal s ₁ is also set to the logic "0", the accumulated value n (= "6") and the flag f are stored in the memory 23.
(= Logical “0”) is stored.

When the influence of the interfering signal is removed in the following fourteenth cycle T ₁₄ , and the arriving input signal i returns to logic “1”, the analysis unit 22 causes the input signal i to indicate logic “1” and the accumulated value n. (= “6”)
Since the value is less than the upper limit value m (= “8”), the counting circuit 21
To count "+1".

As a result, the counting circuit 21 adds "1" to the accumulated value n (= "6") output from the memory 23 and outputs n (= "7").

The comparison circuit 24 uses the accumulated value n and the reference value th (=
"4") is compared, and the condition n ≧ th is still satisfied, the comparison signal c to be output is set to the logic “1”.

As a result, the output signal o output from the selector 27 maintains the logic "1", and the selection signal generation unit 25 outputs the input signal i.
Since the comparison signal c and the comparison signal c are both set to logic "1", the selection signal s ₁ is set to logic "1" as in the tenth cycle T ₁₀ .

As a result, the selector 26 stores the upper limit value m (= “8”) and the flag f (= logical “1”) input to the input terminal B side in the memory 23, as in the tenth cycle T ₁₀ . .

After that, if the master exchange 1 holds the control bit b ₁ at the logic “1” and the input signal i is maintained at the logic “1” until the _20th cycle T ₂₀ , as in the 11th cycle T ₁₁ , Since the analysis unit 22 does not cause the counting circuit 21 to perform any counting, the output signal o is set to logic "1", and the accumulated value n (= upper limit value m =
“8”) and the flag f (= logical “1”) are stored.

Subsequent to the _21st cycle T ₂₁ onward, from the parent exchange 1 to the subscriber 3
When the control bit b ₁ is set to logic “0” in order to execute the switching recovery control of the subscriber circuit of −1, the _21st cycle T ₂₁
Input signal i to arrive after also becomes possible to set to a logic "0", as in the twelfth cycle T ₁₂ and the thirteenth cycle T _13, "-1 for the analysis unit 22 counting circuit 21 The counting circuit 21 sequentially subtracts “1” from the accumulated value n output from the memory 23, and as a result, the accumulated value n is “1”.
It decreases to "4" in the _24th cycle T ₂₄ .

The comparison circuit 24 sets the comparison signal c to be output to logic “1” because the condition n ≧ th is satisfied until the _24th cycle T _24, but the accumulated value is set in the 25th cycle T _25. When n becomes "3" and the condition n <th is satisfied, the comparison signal c to be subsequently output is set to the logic "0".

As a result, the output signal o output from the selector 27 is also
Until twenty-fourth period T ₂₄ is maintained at logic "1", but twenty-fifth cycle T ₂₅ after being set and maintained in the logic "0".

The selection signal generator 25 outputs the selection signal s _{1 as} well as the input signal i
There order is set to a logic "0" in the twenty-first cycle T ₂₁ after being set to a logic "0", the selector 26, the twenty-first cycle T ₂₁
After the cycle, the input terminal A side is selected, and the accumulated value n output from the counting circuit 21 is stored in the memory together with the flag f (= logical “0”).
Store in 23.

As a result, the accumulated value n stored in the memory 23 maintains the upper limit value m (= “8”) until the _20th cycle T _{20 and} decreases to “1” after the _21st cycle T ₂₁ , Reference value th in the _24th cycle T ₂₄
After reaching (= “4”), it becomes “0” in the twenty-eighth cycle T ₂₈ , and becomes the same state as the first cycle T ₁ again.

As apparent from the above description, according to this embodiment, when the input signal i arriving at the signal receiving circuit is set to a logic "1" seventh period T ₇ or later, the tenth cycle since output after three cycles The signal o is set to logic "1", and the input signal i becomes _21st cycle T _21.
After that, if set to logic "0", the 25th cycle after 4 cycles
After T _{25, the} output signal o is set to logic “0”, and the input signal i is set to logic “1” due to the interference signal in the second period T ₂ and the third period T _3.
Set be output signal o is maintained at logic "0", the addition input signal i for the interfering signal in the twelfth cycle T ₁₂ and the thirteenth period T ₁₃ is also set to a logic "0" Output signal o is logical "1"
To maintain.

Therefore, if the remote device 2 executes the switching control of the subscriber circuit of the subscriber 3-1 based on the output signal o, the invalid switching control by the interfering signal is not executed, and the stable switching control can be surely executed. Become.

When it is necessary to directly output the input signal i as the output signal o when testing the remote device 2 or the like, the selection signal s ₂ input to the selector 27 from the outside is set to the logic “1”. As a result, the input signal i input to the input terminal B of the selector 27 is output as its side output signal o.

It is to be noted that FIGS. 2 and 3 are merely examples of the present invention until now, and the reference value th and the upper limit value m are not limited to those shown in the figure, and many other modifications are considered. However, the effect of the present invention does not change in any case. It goes without saying that the subject matter of the present invention is not limited to the remote control system and the signal receiving circuit shown.

〔The invention's effect〕

As described above, according to the present invention, the logic value of the input signal changes the logic value of the output signal only when the change of the logic value of the input signal is connected. It is possible to prevent invalid control caused by such a fluctuation.

[Brief description of drawings]

1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a signal receiving circuit according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of a bit error protection process in FIG. 2, and FIG. FIG. 5 is a diagram showing an example of a remote control system to which the present invention is applied;
The figure is a diagram showing an example of the remote control command in FIG. In the figure, 1 is a central office switch, 2 is a remote device, 3 is a subscriber, 4 is a transmission line, 21 is a counting circuit, 22 is an analysis unit, 23 is a memory, 24 is a comparison circuit, 25 is a selection signal generation unit, 26 and 27 are selectors, 100 is counting means, 200 is storage means, 300 is comparison means, and 400 is setting means.

Claims (1)

[Claims] 1. A binary input signal (i) arriving at a fixed period.
Counting means (10) for counting the accumulated value (n) by adding when one indicates a logical value and subtracting when indicating the other logical value.
0), an accumulating means (200) for accumulating the accumulated value (n) counted by the counting means (100), and comparing the accumulated value (n) with a predetermined reference value (th), A comparison means (300) that outputs an output signal (o) when the accumulated value (n) reaches the reference value (th), and the comparison means (300) outputs the output signal (o). In this state, when the input signal (i) indicating the one logical value is input, the accumulated value (n) accumulated by the accumulating means (200) is set to be larger than the reference value (th). A bit error protection method comprising: a setting means (400) for setting an upper limit value (m).