JPH0787536B2 - Digital horizontal sync playback circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital horizontal sync reproduction circuit used in a digital television receiver.

[Technical background of the invention]

2. Description of the Related Art Recently, due to advances in semiconductor technology, digital television receivers that digitize baseband video signals and perform various signal processing have been developed. In this digital television receiver, in order to facilitate the color demodulation process, the frequency of the sampling clock is selected to be three times or four times the color subcarrier frequency, and the sampling clock is phase-synchronized with the color burst signal. It is processing.

On the other hand, in the television receiver, the phase relationship between the sampling clock and the horizontal synchronizing signal is not specified. In addition, the phase relationship with the sampling clock is not particularly defined for the horizontal sync reproduction signal whose oscillation cycle is normally limited internally in synchronization with the horizontal sync signal. Therefore, when the horizontal sync signal detection for signals of black-and-white broadcasting, video tape recorder, etc. is performed in the unit of the sampling clock, there is a dead zone of phase detection in the sampling period. As a result, jitter occurs in the horizontal sync reproduction.

For example, if the sampling clock is four times the color subcarrier frequency of the NTSC system signal, the sampling period is 70
It is nsec, and the jitter caused by this has a great adverse effect on the screen.

Therefore, there is a demand for a horizontal sync reproduction circuit that can detect a horizontal sync signal with high accuracy and obtain a horizontal sync reproduction signal with less jitter.

[Object of the Invention]

The present invention has been made in view of the above circumstances. The horizontal synchronization signal is detected with high accuracy, an error signal smaller than the sampling clock period is obtained, and the horizontal synchronization reproduction signal is corrected and the horizontal synchronization reproduction signal is corrected. It is an object of the present invention to provide a digital horizontal sync reproduction circuit in which the cycle of the generation unit can be corrected with high accuracy.

[Outline of Invention]

According to the present invention, for example, as shown in FIGS. 1 to 4, as phase information of a horizontal synchronization detection signal, phase information smaller than the unit of sampling clock φS is used as a phase correction signal (CSΔ
τ). Next, when the horizontal sync reproduction signal (HCTR) is produced in synchronization with the horizontal sync detection signal (HS), the cycle of this signal is corrected by the phase correction signal (CSΔτ). Further, in this case, the phase error (HCΔτ) included in the horizontal sync reproduction signal generator can be detected and the horizontal sync reproduction signal (HCTR) can be corrected together with the phase correction signal (CSΔτ).

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital horizontal synchronizing circuit according to an embodiment of the present invention. The analog video signal (AVS) is converted into a sampling clock (φ
It is converted into a digital video signal (DVS) by S). In this embodiment, the frequency of the sampling clock (φS) is selected to be four times the color subcarrier frequency (s), and this clock (φS) becomes the basic clock of the entire system.

The digital video signal (DVS) is supplied to the sync separation circuit 12 and the sampling clock phase detection circuit 13. The sync separation circuit 12 performs level comparison between the digital video signal (DVS) and the sync separation level (SEP), separates the sync signal, and obtains a composite sync signal (CS). Composite sync signal (C
S) is guided to the horizontal sync detection circuit 14. The horizontal sync detection circuit 14 obtains a horizontal sync detection signal (HS) by detecting the pulse period and width of the composite sync signal.

The sampling clock phase detection circuit 13 has a sampling clock φ as described in detail with reference to FIGS. 2 and 3.
The phase difference between S and the rising edge of the horizontal sync detection signal (HS) is detected to obtain the phase correction signal (CSΔτ).

Means for obtaining the above phase correction signal (CSΔτ)
This will be described with reference to FIGS. 2 and 3.

FIG. 2 is a time chart showing the rising portion of the horizontal synchronizing signal in an enlarged manner. In the figure, the digital video signal (DVS) is shown in analog form for the sake of clarity. Actually, what is obtained as a digital value is only the portion where the signal (DVS) is marked with a black circle (the rising portion of the sampling clock φS). Therefore, the rising edge of the composite sync signal (CS) is
The horizontal sync detection signal (HS) detected from the composite sync signal (CS) is synchronized with the rising edge of S and the composite sync signal (C)
Phase synchronization with the rising edge of S).

However, if the horizontal sync signal (HS) rises at point B in the figure, the time at which the actual horizontal sync signal seems to have crossed the sync separation level (SEP) is CSΔτ before the point B in the figure. Is. If CSΔτ is obtained, the rising phase error of the horizontal synchronizing signal (HS) with a precision smaller than the cycle of the sampling clock φS can be detected.

FIG. 3 shows the inter-sampling clock phase detection circuit 13 for obtaining the above CSΔτ as a phase correction signal.

The separation level cross point detection circuit 131 obtains data (DA) at time (A) and data (DB) at time (B) immediately before the rising detection time (B) of the horizontal synchronization detection signal (HS).

This data (DA) (DB) is used for the inter-clock phase operation circuit 13
Entered in 2. The arithmetic circuit 132 further uses the synchronization separation level (SEP) to perform the next arithmetic operation.

Here, the slope of the video signal before and after the sync separation level is
The approximation is made to be constant. By this calculation, the phase correction signal (CSΔτ) is obtained.

Returning to FIG. 1, description will be made.

Horizontal sync detection signal (HS), phase correction signal (CSΔτ)
Is supplied to the horizontal phase error detection circuit 15.

The horizontal phase error detection circuit 15 includes a horizontal loop filter 16 and a digital control oscillator 17, as described in detail in FIG.
It forms a phase-locked loop. This horizontal phase-locked loop detects the phase difference between the oscillation output phase of the digitally controlled oscillator 17 (predetermined phase of the horizontal counter output) and the horizontal sync signal in the video signal with high accuracy and converts it into the horizontal sync signal in the video signal. Horizontal counter output (CHTR) In other words, it works so that the specified phase of the horizontal sync playback signal is locked accurately.

The phase locked loop will be described with reference to FIG.

The digitally controlled oscillator 17 is an all-digital oscillator whose oscillation cycle is controlled by a horizontal sync detection signal (HS), and can operate with high precision of a clock φS or higher. The digitally controlled oscillator 17 has a horizontal counter 171. The horizontal counter 171 is reset by the horizontal counter reset signal (RS) and counts the clock φS.

The count output (HCTR) as the horizontal synchronizing reproduction signal of the horizontal counter 171 is supplied to the coincidence detection circuit 172 and the latch circuit 151 in the horizontal phase error detection circuit 15.

The latch circuit 151 latches the horizontal count output (HCTR) by the previous horizontal synchronization detection signal (HS) and supplies the value to the subtractor 152.

The subtractor 152 subtracts the previous phase correction signal (CSΔτ) from the output value of the latch circuit 151. This is equivalent to converting the phase of the horizontal sync detection signal (HS) into the phase (value) of the horizontal counter output and subtracting the previous phase correction signal (CSΔτ) from this value.

The output of the subtractor 152 is input to the subtractor 153. Subtractor 15
3 further subtracts the output phase correction signal (HCΔτ) of the horizontal counter 171 from the output value of the subtractor 152.
This means that even if the relationship between the count output phase of the horizontal counter 171 and the phase of the horizontal sync detection signal (HS) becomes a predetermined phase relationship, if the horizontal counter 171 itself has an error, true synchronization is obtained. Because I can't.

Next, the output of the subtractor 153 is further supplied to the subtractor 154,
The horizontal counter target phase value (Href) is subtracted. That is, if the horizontal synchronization detection signal (HS) and the output phase of the horizontal counter 171 have a predetermined relationship, the output value of the subtractor 154 can be calculated in advance. Therefore, if the subtractor 154 subtracts the horizontal counter target phase value (Href) from the output value of the subtractor 153, an error from the target phase value (Href) can be obtained.

The output of the subtractor 154 is supplied to the limiter circuit 155. The limiter circuit 155 limits the signal with a large error from the subtractor 154. The limiter circuit 155 works effectively to maintain stable operation of the circuit when the horizontal sync detection signal (HS) is erroneously detected. The output of the limiter circuit 155 is supplied to the loop filter 16.

The loop filter 16 determines the stability of the feedback loop system, the convergence time, and the like. In this embodiment, the coefficient multiplier 16 is applied to the phase error signal (ER1) from the limiter circuit 155.
The coefficient a is multiplied by 1 and the coefficient b is multiplied by the coefficient multiplier 165. The coefficients a and b set the time constant of the loop filter 16. The output of the coefficient multiplier 161 is the adder 162
And the latch circuit 163.
The integrated output is added to the output of the coefficient multiplier 165 in the adder 164.

The output of the loop filter 16 outputs a horizontal cycle signal (CH). Horizontal period signal (CH) is digitally controlled oscillator
It gives 17 oscillation cycles.

The horizontal cycle signal (CH) is divided into an integer component (CH1) (upper bit) and a fractional component (CH2) (lower bit), and the integer component (CH1) is supplied to the adder 173 and the fractional component (CH2). ) Is supplied to the adder 174. Integer component (CH1)
Indicates the oscillation cycle in units of clock φS, and the decimal component (CH
2) means the oscillation cycle within one cycle of the clock φS.
In the adder 173, the integer component (CH1) and the horizontal standard period value are added. Further, the adder 174 constitutes an integrating circuit together with the latch circuit 175. And adder 1
The carry of 74 (CRY) is added to the adder 173.

Now, the horizontal counter 171 sets the clock φS to 9 during one horizontal period.
10 shall be counted. Here, if the phase error does not occur at any place, the horizontal period signal (CH) is all 0s. If 910 is set as the horizontal standard cycle value, the horizontal counter 1
When 71 counts 910 clocks φS, a coincidence pulse (RS) is obtained. This coincidence pulse (RS) is used as a reset signal of the horizontal counter 171 and a latch pulse of the latch circuit 175.

Now, suppose that a phase shift of 1 clock φS occurs in 4 horizontal cycles, and φS is the fractional adjustment (CH2).
Data of 0.25 minutes of the cycle appears. This data is accumulated in the integrating circuit, becomes “1” at 4 × 0.25 (4 horizontal cycles), and is input to the adder 173 as a carry. Therefore,
At this time, the horizontal counter 171 is reset by the coincidence pulse (RS) when counting 910 + 1. Since the output of the latch circuit 175 is also given to the subtracter 153 of the horizontal phase error detection circuit 15, the above-mentioned loop corrects the phase as if the loop φS is further divided into one cycle. To do. The output of the latch circuit 175 is a horizontal counter correction signal (HCΔτ).

Returning to FIG. 1, description will be made. The above circuit first obtains the phase error of the horizontal sync detection signal (HS) existing for the sampling period of the clock φS, and further corrects the phase of the horizontal count output with an accuracy equal to or higher than the period of the clock φS. .

Further, it is possible to perform correction so that the phase of the horizontal count output becomes a predetermined phase with respect to the horizontal synchronizing signal of the video signal.

The horizontal counter correction signal (HCΔτ) and the horizontal count output (HCTR) described above are supplied to the horizontal drive circuit 21 and the flyback phase error detection circuit 19.

The flyback phase error detection circuit 19 is used to set the phase relationship between the flyback pulse (HFB) of the television receiver and the horizontal synchronizing signal to a predetermined phase. First, the flyback pulse (HFB) is the sampling clock φS
The phase within one cycle is detected. This detection circuit is a sampling clock phase detection circuit 18.

The inter-sampling clock phase detection circuit 18 supplies a flypack phase correction signal (FBΔτ) and a read timing pulse (FBT) of this signal to the flyback phase error detection circuit 19. Flyback phase error detection circuit 19
Is the horizontal counter output (HCTR) and timing pulse (FB
T) (synchronized with the sampling clock), the phase difference information is detected, and then the flyback phase correction signal (FB
Δτ) and the horizontal counter correction signal (HCΔτ) are used to correct the phase difference information. Further, the phase difference information thus corrected is corrected by the horizontal screen position control signal (HPH). The horizontal screen position information (HPH) is a signal externally given to adjust the screen position according to the characteristics of the receiver and the preference of the user.

The flyback phase error detection circuit 19 obtains the flyback phase error signal (ER2). This signal (ER2) is taken out as a horizontal drive / flyback pulse phase control signal (DEB) via the flyback loop filter 20 and supplied to the horizontal drive generation circuit 21. The horizontal drive generation circuit 21 has a horizontal drive width counter described in FIG. 7 and a comparator for comparing the horizontal drive width control signal (HPW) to obtain a horizontal drive pulse (HD). In this case, the phase of the horizontal drive pulse (HD) has a predetermined phase relationship with the horizontal counter 171 (shown in FIG. 4) and with the flyback pulse (HFB). Here, the horizontal counter 171 corrects the phase relationship with the horizontal synchronizing signal to a predetermined relationship, and also obtains the phase information within one cycle of the sampling clock φS of the flyback pulse (HFB). Therefore, the phase of the horizontal drive pulse (HD) can be controlled with an accuracy of the clock φS or higher.

The configurations of the inter-clock phase detection circuit 18, the flyback phase error detection circuit 19, the loop filter 20, and the horizontal drive generation circuit 21 will be described more specifically.

FIG. 5 shows the inter-clock phase detection circuit 18, and FIG. 6 is a time chart for explaining the operation thereof.

The flyback pulse (HFB) is supplied to the gate delay circuit 182 via the input terminal 181. The gate delay circuit 182 is a series circuit of 16 gate delay elements that are non-inverters and have a delay amount of about 1/16 of the sampling clock φS. Therefore, the outputs (d1 to d16) of each gate delay element are shifted by 1/16 period of one cycle of the sampling clock φS, as shown in FIG.

The outputs d1 to d16 are supplied to a latch circuit 183 that latches these at the rising edge of the sampling clock φS. The latch circuit 183 has outputs e1 to e16 corresponding to d1 to d16,
Only the output e1 is supplied to the latch circuit 184, and the other outputs e2 to e
16 is supplied to the latch circuit 185. The latch circuit 184 is
1 is latched at the rising edge of the sampling clock φS, and its output is supplied to the clock input terminal of the latch circuit 185. Further, the output of the latch circuit 184 is the read timing pulse (FB) of the flyback phase correction signal (FBΔτ).
Used as T). Output of latch circuit 185 (f2 to f1
6) is supplied to the counting circuit 186. This counting circuit 186
Counts "1" among the outputs (f2 to f16) and outputs the value as a flyback position correction signal (FBΔτ). This flyback phase correction signal FBΔτ is treated as a decimal component. That is, it is treated equivalently to the value obtained by multiplying the count value of "1" by (1/16).

Now, as shown in FIG. 6, it is assumed that the phase information of the flyback pulse (HFB) is latched at the rising time (t61) of the sampling clock φS. However, since the actual flyback pulse (FBT) rises at the time point (t60) before the time point (t61), FBΔτ in the figure corresponds to the flyback phase correction amount. Therefore, the latch circuit
If the number of "1" s in 185 is counted, this can be used as a phase correction signal. Since the phase correction signal (FBΔτ) must be read within one cycle of the sampling clock φS, the sampling clock φS falls (t6
In 2), the tamping pulse (FBT) is configured to rise.

FIG. 7 shows the flyback phase error detection circuit 19, the loop filter 20, and the horizontal drive generation circuit 21.

The count output (HCTR) from the horizontal counter 171 in the horizontal phase error detection circuit 15 is latched by the latch circuit 191 at the rising edge of the previous timing pulse (FBT).
By this, the phase information of the horizontal count output (HCTR) and the timing pulse (FBT) can be obtained. The output of the latch circuit 191 is supplied to the subtractor 192. In the subtractor 192, the flyback phase correction signal (FB
Δτ) is subtracted. Further, the output of the subtractor 192 is the subtracter 1
It is supplied to 93, where the phase correction signal (HCΔτ) of the horizontal counter 171 is subtracted. As a result, the correction of the phase information can be obtained in units smaller than one cycle of the sampling clock φS. In this processing path, the operation bit string of the sampling clock φs in a cycle unit is assigned as an integer, and the operation bit string in a unit smaller than one cycle is assigned as a decimal. Further, the output of the subtractor 192 is supplied to the subtractor 194, where an error between the subtractor 192 and the horizontal screen position control signal (HPH) is calculated. The output of the subtractor 194 is the limiter 195.
To the flyback phase error signal (ER2).

The flyback phase error signal (ER2) is fed to the loop filter 2
The coefficient C is multiplied by the coefficient multiplier 201 of 0, and the signal obtained as a result is integrated by the integrating circuit configured by the adder 202 and the latch circuit 203. And the integrated output is
The phase control signal (DFB) between flyback pulses is supplied to the subtractor 211 of the horizontal drive generation circuit 21.

The horizontal drive generation circuit 21 holds the phase relationship between the flyback pulse whose phase error is detected as described above and the horizontal drive pulse (HD) in a predetermined relationship.

The phase control signal (DFB) is input to the subtractor 211. A horizontal screen position control signal (HPH) is supplied to the subtractor 211. In the subtractor 211, the horizontal drive / flyback pulse phase control signal (DFB) is subtracted from the horizontal screen position control signal (HPH) to determine the rising phase of the horizontal drive pulse. The subtractor 211 corrects the delay amount of the flyback pulse.

Next, the output of the subtractor 211 is supplied to the adder 212, and is added to the horizontal counter phase correction signal (HCΔτ). This is because before the comparison with the horizontal counter output (HCTR) in φS unit is performed, the correction is performed with a precision smaller than one cycle of the sampling clock φS, and as a result, the precision of the horizontal drive pulse (HD) is improved. .

The integer part (CF1) of the upper bits of the output of the adder 211 is supplied to the coincidence circuit 213, and the decimal part (CF2) of the lower bits is given to the selection circuit 217 as a control signal. In the matching circuit 213, a reset pulse (RS2) is obtained when the integer (CF1) and the horizontal count output (HCTR) match,
This reset pulse (RS2) resets the horizontal drive width counter 214.

When reset, the horizontal drive width counter 214 raises a drive pulse (HDS) in units of φS and counts the clock φS. This count value is
At 5, it is compared with the horizontal drive width control signal (HPW). The comparator 215 causes the drive pulse (HDS) to fall when the output value of the horizontal drive width counter 214 becomes larger than the horizontal drive sub-control signal (HPW).

The drive pulse (HDS) is supplied to the gate delay circuit 216. The gate delay circuit 216 has the same structure as the gate delay circuit 182 shown in FIG. 5, and obtains a plurality of drive pulses having a phase with a precision smaller than the cycle of the clock φS. Any one of the plurality of drive pulses is selected by the selection circuit 217 and output as a true horizontal drive pulse (HD). The selection circuit 217, according to the decimal component (CF2) from the adder 212,
Determine the selection pulse. That is, the horizontal drive pulse (HD) is controlled to a phase with a finer precision than the cycle of the sampling clock φS.

The above horizontal flyback phase error detection circuit 19, flyback pulse loop filter 20, horizontal drive generation circuit 21
As shown in Fig. 8, the horizontal flyback pulse (HF
The rising phase of B) works to match the time (t81) when the value of the horizontal counter 171 and the value of the water screen position control signal (HPH) match. Therefore, horizontal drive pulse (HD)
The phase error detection circuit 19 and the loop filter 20 obtain the time delay information from the time when is generated until the horizontal flyback pulse (HFB) is obtained, that is, DFB. in this case,
The phase of the timing information obtained from the flyback pulse is
The phase is finer than that of the clock φS, and the phase of the count information obtained from the count output of the horizontal counter 171 is also finer than that of the clock φS. Then, the phase of the horizontal drive pulse (HD) is accurately determined based on the horizontal drive / flyback phase control signal (DFB).

FIG. 9 shows the basic principle of the inter-sampling clock phase detection circuit 18 of FIG. 5 and the circuit of FIG. 7 in blocks. Therefore, the synchronization means 31 and the correction signal generation means
Reference numeral 32 denotes the sampling clock phase detection circuit 18, and phase control means 33 is the flyback phase error detection circuit 19
Means the horizontal drive means 34 is a horizontal drive generation circuit.
Means 21 Further, although the horizontal synchronization detection signal HS is shown as being input to the phase control means 33, it is actually a horizontal count output HCTR synchronized with the horizontal synchronization detection signal HS. As shown in FIG. 9, the synchronizing means 31 synchronizes the horizontal flyback pulse (HFB) with the sampling clock φS. Next, the correction signal generating means 32 obtains a flyback phase correction signal (FBΔτ) which is the difference between the phase of the synchronization signal of the flyback pulse (HFB) and the predetermined phase of the sampling clock φS.

On the other hand, the horizontal drive means 34 generates a horizontal drive pulse (HD) using the horizontal synchronizing signal. Furthermore, the phase of the horizontal drive pulse (HD) is controlled by the horizontal drive flyback pulse phase control signal (DFB).

Horizontal drive flyback pulse phase control signal (DF
B) is obtained by the phase controller 33 integrating the phase difference between the timing signal (FBT) synchronized with the cycle of the sampling clock φS and the horizontal synchronizing signal.

Therefore, the phase control means 33 is further input with a flyback phase correction signal (FBΔτ) representing the phase information of the flyback pulse (HFB) in a unit smaller than the cycle of the sampling clock φS, and the phase control signal (FBΔτ) is input. DF
By correcting B), the horizontal jitter due to the flyback pulse (HFB) can be reduced.

〔The invention's effect〕

As described above, according to the present invention, the horizontal sync signal can be detected with high accuracy, the phase information of the horizontal sync detection signal can be corrected with the resolution of the sampling clock or more, and the cycle of the horizontal sync reproduction signal can be made highly accurate. Moreover, an error in the horizontal synchronizing signal generator can be detected with high accuracy.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a configuration of an embodiment of the present invention, FIG. 2 is an operation waveform diagram shown for obtaining a horizontal synchronization correction signal, and FIG. 3 is a detailed explanation of the inter-clock phase detection circuit of FIG. FIG. 4 is a more detailed view of the horizontal sync reproduction signal generator of FIG. 1, FIG. 5 is a detailed view of the flyback clock phase detection circuit of FIG. 1, and FIG. 6 is FIG. Waveform diagram of the circuit of FIG. 7, FIG. 7 is a diagram showing the horizontal drive pulse generator of FIG. 1 in more detail, FIG. 8 is a waveform diagram of the operation of the circuit of FIG. 1, FIG. 9 is FIG. 2 is a diagram showing the circuit of FIG. 11 ... Analog / digital converter, 12 ... Synchronous separation circuit, 13 ... Sampling clock phase detection circuit, 14 ...
… Horizontal sync detection circuit, 15… Horizontal phase error detection circuit, 16
...... Horizontal loop filter, 17 …… Digitally controlled oscillator,
18 …… Sampling clock phase detection circuit, 19 …… Flyback phase error detection circuit, 20 …… Flyback loop filter, 21 …… Horizontal drive generation circuit.

Claims (2)

[Claims] 1. An analog-digital converter for sampling an analog video signal at a predetermined sampling clock to convert it into a digital video signal, and a synchronization for comparing the digital video signal with a sync separation level to separate a composite sync signal. Separation means, and horizontal sync detection for obtaining a horizontal sync detection signal (HS) synchronized with the cycle of the sampling clock by detecting a signal corresponding to a predetermined pulse cycle and pulse width from the composite sync signal. Means, detecting values (DA), (DB) immediately before and after the sync separation level (SEP) from the digital video signal sampled at the sampling clock cycle, (DB-SEP) / (DB-DA) = CSΔτ, the sampling clock interval for obtaining the phase correction signal (CSΔτ) of the horizontal synchronization detection signal (HS) Phase detection means, a horizontal counter driven by the sampling clock, and reset control means for controlling the reset timing of this horizontal counter are provided, and the count output that is normally reset in a standard horizontal cycle is used as a horizontal synchronization reproduction signal. A digital control oscillating means which is capable of controlling the phase of the horizontal synchronizing reproduction signal by inputting a control signal to the reset controlling means, and the horizontal synchronizing detecting signal for detecting the horizontal synchronizing reproduction signal from the digital control generating means. When sampling with a signal and feeding back the error between the sampled value and the set value as the control signal of the digital control oscillation means, the value of the error is further adjusted by the phase correction signal (CSΔτ),
Horizontal phase error detection and control means for adjusting the phase of the horizontal sync reproduction signal to the phase of the horizontal sync detection signal so as to adjust the phase of the horizontal sync reproduction signal to the phase of the sampling clock as well. And a digital horizontal synchronization reproducing circuit. 2. The digital control oscillation means, wherein the control signal for controlling the phase of the count output is first control data corresponding to phase adjustment for each cycle unit of the sampling clock, and the sampling clock. Second control data corresponding to phase adjustment within one cycle of the digital control oscillator, and the count output is supplied to one input end, and a comparison input is supplied to the other input end. A match detection circuit that generates a reset pulse for resetting the horizontal counter when the comparison input and the count output match, a value that provides a standard horizontal cycle as the reset cycle of the count output, and A first adder for adding the first control data and applying the first control data to the coincidence detection circuit as the comparison input; Adding the data in the period of the reset pulse, the digital horizontal sync reproducing circuit claimed in claim 1, characterized in that having a second adder providing a carry output to the first adder, a.