JPH0789264B2 - Display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device that displays a still image handled in a word processor, a personal computer or the like.

2. Description of the Related Art A liquid crystal layer is interposed between a plurality of scanning electrodes and a plurality of data electrodes arranged in a direction intersecting with each other, and the scanning electrodes are provided with a potential corresponding to display data applied to the data electrodes. In a simple matrix type liquid crystal display device which is driven by sequentially applying a selection potential to
2 depending on whether the picture element is driven on or off
It has been attempted in the past to perform not only a value display but also an intermediate gradation display that also displays intermediate brightness over several steps. As a method of this intermediate gradation display, a method of modulating the pulse width of the voltage applied to the data side electrode and a method of setting a plurality of frame periods as one cycle and displaying the voltage applied to the data side electrode in each frame within the cycle 2. Description of the Related Art A data thinning method that performs data thinning processing for selectively switching from a voltage to a voltage corresponding to non-display is well known.

Assuming that gradation display of 2 ⁿ (n is an integer) level is performed, in the method of modulating the pulse width, the data side drive circuit for applying a voltage corresponding to display data to the data side electrode is input. A gradation control circuit that modulates the pulse width of the voltage waveform applied to the data-side electrode is incorporated according to the incoming n-bit gradation data, and gradation display is thereby performed. On the other hand, in the data thinning method, a gray scale control circuit and a frame discrimination circuit are incorporated in a liquid crystal display control circuit composed of a large-scale integrated circuit (hereinafter, abbreviated as LSI) and stored in a display memory. The gradation control circuit reads the n-bit grayscale data per picture element, and performs the necessary signal processing for thinning out the read grayscale data on the basis of the output of the frame discrimination circuit. Is converted from a parallel signal to a serial signal and the serial signal is transmitted as display data to the data side drive circuit by the gradation control circuit, and the series output from the gradation control circuit as display data is performed. Grayscale display is performed by the signal.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention By the way, in the case of the above-mentioned pulse width modulation method, the data side drive circuit having a built-in gradation control circuit and the display data of n bits per pixel (when performing 2 ⁿ gradation display) A liquid crystal display control circuit dedicated to the pulse width modulation method that can output at the same time is required. Therefore, general liquid crystal drive circuits and liquid crystal display control circuit LSIs used for non-grayscale display can be used as they are for grayscale display. It is impossible to realize.

Further, in the case of the above-described conventional data thinning method, a liquid crystal display control circuit LSI dedicated to the data thinning method, which includes a gradation control circuit for performing thinning signal processing, is required, and is generally used for non-gradation display. It is impossible to realize gradation display by using the liquid crystal display control circuit as it is. Further, even when the liquid crystal display control circuit LSI dedicated to the data thinning method is used, each pixel is driven by the voltage waveform with one cycle of a plurality of frame periods, so that the driving frequency of the pixel for displaying halftone is low. In addition, since the thinning processing by the gradation control circuit is performed only on the basis of the frame discrimination signal, when a plurality of consecutive picture elements in the arrangement are displayed in the same gradation, they are applied to the respective picture elements. The timing at which the voltage changes from the voltage corresponding to the display to the voltage corresponding to the non-display is synchronized. Therefore, the frequency with one cycle of the above-mentioned multiple frame period is
If the frequency is about 40 Hz or less, there is a problem that flicker becomes conspicuous in adjacent picture element groups of the same gradation display and the display quality is degraded.

Therefore, an object of the present invention is to combine either a general display control circuit and a drive circuit used for non-gradation display or a combination of a display control circuit dedicated to a pulse width modulation system and a general drive circuit. It is an object of the present invention to provide a display device which is capable of performing gradation display even when used and has a good display quality in which flicker is not conspicuous in adjacent pixel groups of the same gradation display.

Means for Solving the Problems According to the present invention, a plurality of picture elements arranged in a matrix are formed in a state where a potential corresponding to display data is applied to a plurality of data side electrodes arranged in the column direction of the picture elements. In a display device which is driven by sequentially applying a selection potential to a plurality of scanning-side electrodes arranged in the row direction of a pixel and completes display of one frame, a plurality of bits for causing the pixel to perform gradation display Based on the gradation data output means for outputting the gradation data of each of the pixels in association with each picture element and the frame start signal for giving the frame start timing, each frame in the cycle is defined as one cycle of a plurality of frames. A frame discriminating means for outputting a frame discriminating signal for discriminating and a scanning side electrode for giving a selection potential are switched and designated, and correspond to display data of picture elements on the designated scanning side electrode. A line discriminating means for outputting a line discriminating signal for discriminating each scanning line in the frame on the basis of the data latch signal for applying an electric potential to the data side electrode and the frame discriminating signal, and the data thinning means, The means is
As the display data of the picture element in each scanning line of each frame discriminated by the frame discrimination signal and the line discrimination signal, each bit of the gradation data is set so that the output number of the high-order digit is larger than the output number of the lower-order digit. The number of times corresponding to the weight of each digit is output over the one cycle, and each digit is selected and output for each frame. Shift,
A display device is provided with data thinning means for selectively changing the periodic order of selecting each digit for each frame between adjacent picture elements on the same scanning line so as to be different from each other.

Operation According to the present invention, one from a plurality of predetermined frames
Each scanning line of each frame in the cycle is discriminated by the frame discrimination signal output from the frame discriminating means and the line discrimination signal output from the line discriminating means, and the discrimination of the picture elements in each scanning line of each frame discriminated is performed. As the display data, either ON data corresponding to display or OFF data corresponding to non-display is selectively output by the data thinning means, and one screen is displayed by the above one cycle. Since the number of times ON data is output to each pixel over one cycle is determined according to the gradation data, the display on one screen is a gradation display. The output order is determined according to each scan line, and the on-data output order is different even between adjacent picture elements on the same scan line, so the voltage waveform applied between adjacent picture elements displayed in the same gray scale. The flicker is reduced because the phases are not synchronized.

That is, in the present invention, the grayscale data of the grayscale data output means is output in bit parallel of a plurality of bits DH, DM, DL, and the data thinning means outputs (a) each bit of the grayscale data. , So that the number of outputs of the high-order digit is larger than the number of outputs of the lower-order digit, the output is performed over the one cycle by the number of times corresponding to the weight of each digit. For example, in the embodiment described later, it is related to Table 3. As described above, the upper bit data DH is output four times in the eight frames constituting one cycle, the middle bit data DM is output twice, and the lower bit data DL is output once. In addition, (b) a predetermined periodical order for selecting and outputting each digit for each frame is defined by a plurality of predetermined scanning lines (in the embodiment described later, four lines L _{4y + 1 to} L _{4 (y + 1))} . Is shifted for each scanning line, for example, in the embodiment described later, Of the frame - in Table 3, the scanning lines, DH → DM → DH → DL →
DH → DM → DH → “0” or “1” is output, and on the line, DH → DL → DH → DM → DH → “0” or “1” → DH →
Each digit is selected to be DM, and (c) between adjacent picture elements on the same scan line, the periodic order of selecting each digit is selectively changed for each frame so as to be different from each other. In this embodiment, the even-numbered column data D0 and the odd-numbered column data D1 adjacent thereto are different from each other as shown in Table 3. The data thinning means has such a structure.
By including a, b, and c, the present invention can be easily implemented in connection with a conventional non-gradation display device, and flicker can be prevented.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device which is an embodiment of the display device of the present invention. This liquid crystal display device includes a simple matrix type liquid crystal display element 1 in which a plurality of data side electrodes C and a plurality of scanning side electrodes L are arranged so as to intersect each other with a liquid crystal layer interposed, and the liquid crystal display element 1. A general data-side liquid crystal drive circuit 2 for non-gradation display in which either a voltage corresponding to display or a voltage corresponding to non-display is applied to the data-side electrode C of the liquid crystal display element 1 according to display data. A general scanning-side liquid crystal drive circuit 3 for non-gradation display in which either a voltage corresponding to selection or a voltage corresponding to non-selection is applied to the scanning-side electrode L of A liquid crystal driving voltage dividing generation circuit 4 for supplying a voltage corresponding to non-display and a voltage corresponding to selection / non-selection to the scanning side liquid crystal driving circuit 3, a data side liquid crystal driving circuit 2 for each frame, and Scanning side liquid crystal drive In order to cause the picture elements of the liquid crystal display element 1 to perform 8-gradation display, the AC inversion signal generation circuit 5 that generates the AC inversion signal M for frame switching control that inverts the polarity of the voltage applied to the path 3. 3-bit gradation data [DH, DM,
DL], a scanning start signal S for starting the scanning of each frame, and a control for selecting the scanning line and a timing for applying a voltage corresponding to the display data of the picture element on each scanning line to the data-side electrode C. Data latch signal CP
Liquid crystal display control circuit 6 for pulse width modulation method for outputting
And a display data generation circuit 7 for generating display data D of the data thinning method based on the output signal from the liquid crystal display control circuit 6.

FIG. 2 is a circuit diagram showing a specific configuration of the display data generation circuit 7 described above. Here, in order to simplify the description, among the data side electrodes C _X of the even columns of the liquid crystal display element 1. a display data D ₀ corresponding to an arbitrary one, only the portion having the function of generating a one second display data D ₁ corresponding to the data side electrodes C _{X + 1} of the odd columns adjacent to the data side electrodes C _X It is shown.

In FIG. 2, the frame discrimination circuit 8 sets the drive period for eight frames of this liquid crystal display device as one cycle based on the scanning start signal S output from the above-mentioned liquid crystal display control circuit 6 and giving the timing of frame start. This is a circuit for discriminating each frame within the cycle, and includes three flip-flops 8a, 8b, 8c and two EX-OR gates 9a, 9b.
, AND gate 10, and output Q of the line discrimination circuit 12 described later.
AND gate 11a for obtaining a logical product STAT70 of _AB and the non-inverted output Q _O of the flip-flop 8a, the output Q _AB of the line discrimination circuit 12 and the inverted output of the flip-flop 8a ▲ ▼
And an AND gate 11b for obtaining a logical product STAT71 of The three flip-flops 8a, 8b,
8c, two EX-OR gates 9a and 9b, and an AND gate 10 constitute a synchronous 3-bit binary counter which uses the scanning start signal S as a clock pulse.

The line discrimination circuit 12 outputs the data latch signal CP output from the liquid crystal display control circuit 6 described above and the output from the synchronous 3-bit binary counter of the frame discrimination circuit 7 described above (outputs [Q ₂ , Q ₁ here). , Upper 2 bits of Q ₀ ], Q ₂ , Q ₁ )
Is a circuit for discriminating each scanning line (selected scanning-side electrode L) in each frame on the basis of the following, and includes two flip-flops 13a and 13b, a NAND gate 14, and five ANDs.
Gates 15a, 15b, 15c, 15d, 15e and four inverters 16a, 16
It is composed of a 2-bit binary counter with a load function consisting of b, 16c and 16d, and an AND gate 17 for obtaining a logical product Q _AB of the output Q _A of the flip-flop 13a and the flip-flop 13b.

In the 2-bit binary counter with the load function described above, the scanning start signal S is H and the data latch signal CP is from H to L.
At the timing of falling to (the timing of starting scanning of the first scanning line), the frame discrimination circuit 8
Output from the synchronous 3-bit binary counter of [Q ₂ , Q ₁ ,
The upper two bits Q ₂ and Q ₁ of Q ₀ ] are flipped respectively.
After loading the flops 13b and 13a, the data latch signal C
It has a function to count up every time P rises from L to H and the scanning line is switched.

The even-numbered column data thinning circuit 18a uses the even-numbered column data-side electrode C
As the data corresponding to the picture element on x, 3-bit gradation data [DH _O , DM
_O, DL and _O], 3-bit data [Q _B of the output of the frame discriminator circuit 8 and the line discrimination circuit 12 described above, Q _A,
Q _O ], and the thinned-out display data D _O corresponding to the picture element on the data-side electrode Cx (ON data corresponding to display in non-gradation display or OFF data corresponding to non-display)
Is a signal processing circuit for generating.

This even column data thinning circuit 18a is a line discrimination circuit 12
According to the input SELAO corresponding to the output Q _A of the output and the input SELBO corresponding to the output Q _O of the frame discrimination circuit 8, from among the 3-bit grayscale data [DH _O , DM _O , DL _O ] as the state of the output D _SELO. A 3-to-1 data selector circuit 40a for selecting the state of one bit, an OR gate 19 for obtaining the logical sum of each bit of grayscale data [DHo, DMo, DLo], an output of this OR gate 19 and a frame discrimination circuit AND gate 20 that obtains the logical product of the discrimination output STAT70 from 7 and the output of this AND gate 20 and the output D _SELO of the above 3: 1 data selector circuit are ORed,
It is constituted by an OR gate 21 which supplies this to the data side liquid crystal drive circuit 2 as display data Do corresponding to the picture elements on the data side electrodes Cx in even columns. The 3-to-1 data selector circuit 40a includes one 4-input OR gate 22 and eight NANDs.
It is composed of gates 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h and eight inverters 24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h.

Similarly, the odd-numbered-column data thinning circuit 18b outputs the 3-bit grayscale data [DH ₁ output from the liquid crystal display control circuit 6 described above as corresponding to the picture element on the data-side electrode C _{X + 1} of the odd-numbered column. , DM ₁ , DL ₁ ], and 3-bit data [Q of the outputs of the frame discrimination circuit 8 and the line discrimination circuit 12 described above]
_B1 , Q _A1 , ▲ ▼] and a signal processing circuit for generating display data D ₁ of the thinning method corresponding to the picture element on the data side electrode C _{X + 1} .

This odd-column thinning circuit 18b outputs the output Q of the line discrimination circuit 12.
_According to the input SELA1 corresponding to _A and the input SELB1 corresponding to the output ▲ ▼ of the frame discrimination circuit 8, the output D _SEL1
The 3-to-1 data selector circuit 40b for selecting the state of one bit from the 3-bit grayscale data [DH ₁ , DM ₁ , DL ₁ ] and the grayscale data [DH ₁ , DM ₁ , DL ₁ ] OR gate 25 for obtaining the logical sum of each bit, the output of this OR gate 25 and the discrimination output STAT71 from the frame discrimination circuit 8 (state is ST
AND gate 26 to obtain the logical product of
And the output of the AND gate 26 and the output D _SEL1 of the 3-to-1 data selector circuit 40b are ORed, and this is the display data D corresponding to the picture element on the data side electrode C _{X + 1} of the odd column. It is constituted by an OR gate 27 which is given to the data side liquid crystal drive circuit 2 as ₁ . 3: 1 data selector circuit 40
b is one OR gate 28 and eight NAND gates 29a, 29b, 29
c, 29e, 29f, 29g, 29h and 8 inverters 30a, 30b, 30c, 30
It is composed of d, 30e, 30f, 30g and 30h.

FIG. 3 is a schematic diagram showing a part of the arrangement configuration of the electrodes of the liquid crystal display element 1 described above. In each frame, four consecutive scanning lines L _{4y + 1} , L _{4y + 2} , L _{4y + 3} , L shown in FIG.
Line discrimination circuit shown in Fig. 2 when _{4 (y + 1)} is selected
12 and outputs of frame discrimination circuit 8 Q _A , Q _B , ▲ ▼, Q
Table 1 shows the states of the inputs SELA0, SELB0, SELA1, and SELB1 of the ₀ , Q ₁ , Q ₂ and the even column data thinning circuit 18a and the odd column data thinning circuit 18b. However, in Table 1, T _{8m + 1} , T
_{8m + 2} , _{T8m + 3} , _{T8m + 4} , _{T8m + 5} , _{T8m + 6} , _{T8m + 7} , T8 _{(m + 1)} indicate each frame period of the above-mentioned eight frames.

Further, in each frame, the discrimination outputs [Q _B , Q _A , Q from the frame discrimination circuit 8 and the line discrimination circuit 12 shown in FIG. 2 when four consecutive scanning lines shown in FIG. 3 are selected. _O ], [Q _B , Q _A , ▲ ▼] status STAT0 to STAT7
Is shown in Table 2. As is clear from the correspondence with Table 1,
STAT0 is the discrimination output [Q _B , Q _A , Q _O ], [Q _B , Q _A , ▲ ▼] is [0,0,0], STAT1 is [0,0,1], and STAT2 is When [0,1,0], STAT3 is [0,1,1], STAT4 is [1,0,0], STAT5 is [1,0,1], STAT6 is [1 , 1,0], STAT7 represents [1,1,1]. Therefore, in FIG. 2, the frame discrimination circuit 8
AND gate 11a output STAT70 shows the state of STAT7 in which the discrimination output [Q _B , Q _A , Q _O ] becomes [1,1,1], and AND gate 11b
The output of STAT71 is also the discrimination output [Q _B , Q _A , ▲ ▼] is [1,1,
1] indicates the status of STAT7.

Furthermore, in each frame, four consecutive 4 shown in FIG.
Even row data thinning circuit 18a and odd column data thinning circuit 18b shown in FIG. 2 when one scanning line is selected.
Table 3 shows the states of the outputs D ₀ and D ₁ of the.

However, in Table 3, “DH” indicates that the upper bit data DH of the 3-bit gradation data [DH, DM, DL] is selected as the output, and “DM” indicates the gradation data [DH , DM,
[DL] indicates that the middle bit data DM of the DL is selected as the output, and “DL” indicates that the lower bit data DL of the grayscale data [DH, DM, DL] is selected as the output. Is shown.

"1" indicates that the H level is selected as the output when the gradation data [DH, DM, DL] is other than [0, 0, 0] corresponding to non-display, and "O" indicates the gradation. It shows that the L level is selected as the output when the data [DH, DM, DL] is [0, 0, 0]. In Tables 1 to 3, the subscript x,
Any integer is applicable to y and m.

Next, the operation of the liquid crystal display device described above will be described with reference to FIGS.
This will be described with reference to the timing chart shown in the figure and Tables 1 to 3.

Frame discrimination circuit 8 and line discrimination circuit shown in FIG.
By the operation of 12, in each line selection period of the drive period of the liquid crystal display device, as shown in Table 1, each discriminant output has 8 types of drive periods for 8 frames, and 8 types within that period. It is discriminated into the state of. Therefore, the discrimination status STAT0 in each line selection period of each frame
~ STAT7 is as shown in Table 2.

That is, the discrimination state in which the even-numbered-column data thinning circuit 18a and the odd-numbered-column data thinning circuit 18b perform the thinning-out signal processing corresponding to each picture element with 8 picture elements of 2 columns × 4 rows as one unit is always one frame. While shifting the phase for a period
Changes from STAT0 to STAT7.

For example, in frame T _{8m + 1} , picture element A _{x, 4y + 1} (subscript x, 4
y + 1 represents a pixel at the intersection of the scanning side electrode L _{4y + 1} and the data side electrode C _X. The same _{shall apply} hereinafter) → _{Picture element} A _{x + 1,4y + 1} →
_{Picture element} A _{x, 4y + 2} → _{Picture element} A _{x + 1,4y + 2} → _{Picture element} A _{x, 4y + 3}
→ _{Picture element} A _{x + 1,4y + 3} → _{Picture element} A _{x, 4 (y + 1)} → _{Picture element} A
Discrimination state STA described above in the order of _{x + 1,4 (y + 1)}
T0 to STAT7 are assigned. Even column data thinning circuit 1
In Table 8a and the odd column data thinning circuit 18b, one bit of the gradation data [DH, DM, DL] at that time is shown in Table 3 as the display data D ₀ , D ₁ in the above-mentioned discrimination states STAT0 to STAT7. Select and output as shown.

That is, when the discrimination state is STAT0, STAT2, STAT4, STAT6, the upper bit data DH of the gradation data [DH, DM, DL] is selected as the display data D ₀ , D ₁ , and the discrimination state is ST.
When AT1 and STAT5 are selected, middle bit data DM is selected, and when the discrimination state is STAT3, lower bit data DL
Is selected. When the discrimination state is STAT7, unless the grayscale data [DH, DM, DL] is [0,0,0], “1” is output as the display data D ₀ and D ₁ , and the grayscale data [ DH, DM, D
When L] is [0,0,0], “0” is output as the display data D0, D1.

Therefore, as the display data D ₀ and D ₁ corresponding to one picture _element , the driving period for 8 frames is set as one cycle, and the data DH of the upper bits is the data DM of the middle bits for 4 frames in the cycle. Data of lower bit for 2 frame period
DL is output for one frame period, and "0" or "1" is output for one frame period.

In this way, since the data of each bit of the gradation data [DH, DM, DL] is output only the number of times according to the weight of each digit,
The number of “1” data output as the display data D ₀ , D ₁ during the period of 8 frames, that is, the number of on-data corresponding to the display in the non-gradation display is the gradation data [DH, DM, DL]. It becomes a value corresponding to gradations 0 to 7 (the darkest display gradation is 0 and the brightest display is gradation 7) determined by In other frame periods, data of "0", that is, off data corresponding to non-display in the case of non-gradation display, is output. Further, as described above, the discrimination states corresponding to the 8 picture elements of 2 columns × 4 rows are different, and the phase is sequentially shifted by 1 frame. Therefore, the display data D ₀ , D ₁ in the driving period is increased by 8 frames.
The output waveform of is also out of phase by one frame.

FIG. 4 shows the even column data thinning circuit 18 as described above.
The voltage applied from the data side liquid crystal drive circuit 2 to the data side electrodes C _X of the even-numbered columns in response to the display data D ₀ generated in a and the scan side liquid crystal drive circuit 3 to the scan side electrodes L _{4y + 1} , L _{4y + 2}
FIG. 4 is a timing chart showing the relationship between the voltage waveform applied to the picture element at the intersection of these electrodes and the relationship between the scan start signal S and the data latch signal CP due to the difference with the voltage applied to 4A shows the waveform of the scan start signal S, FIG. 4B shows the waveform of the data latch signal CP, and FIG. 4C shows the waveform of the voltage applied to the picture elements A _x, 4 _{y + 1} . FIG. 4 (d) shows a voltage waveform applied to the picture element A _{x, 4y + 2} .

FIG. 5 shows the voltage applied to the data side electrode C _{x + 1} from the data side liquid crystal drive circuit 2 in response to the display data D ₁ generated by the odd number column data thinning circuit 18b and the scanning side liquid crystal drive. Due to the difference between the voltage applied from the circuit 3 to the scanning side electrodes L _{4y + 1} and L _{4y + 2} , the voltage waveform applied to the picture element at the intersection of these electrodes, the scanning start signal S and the data latch signal CP. 5 (a) shows the waveform of the scanning start signal S, FIG. 5 (b) shows the waveform of the data latch signal CP, and FIG. The waveform of the applied voltage to the picture element A _{x + 1,4y + 1} is shown, and FIG. 5 (d) shows the waveform of the applied voltage to the picture element A _{x + 1,4y + 2} .

As shown in FIG. 4 (c), for the picture element A _{x, 4y + 1} , gradations 0 to 7 determined by the gradation data [DH _O , DM _O , DL _O ] corresponding to this picture element. Accordingly, the driving period for 8 frames is set as one cycle, and the frame period in which the instantaneous voltage ± V _OP corresponding to the display is applied is 0 in each cycle.
Frame period (when gradation is 0), 2 frame periods (when gradation is 1)
,), ..., 8 frame periods (when the gradation is 7),
In other frame periods, the instantaneous voltage ± V _OP (1-2 / a) corresponding to non-display (where a is the ratio of the applied voltage when the display pixel is not selected) is applied. Picture element A
Similar voltages are applied to _{x, 4y + 2} , A _{x + 1,4y + 1} and A _{x + 1,4y + 2 as} shown in FIGS. 4 (d), 5 (c) and 5 (d), respectively. As a result, an effective voltage corresponding to the required gradation 0 to 7 is applied to each picture element,
Gradation display is performed.

In addition, the voltage applied to the picture element A _{x, 4y + 1} and the picture element A
_The voltages applied to _{x + 1} and _{4y + 1} have waveforms whose phases are shifted by one frame period, as is clear from the comparison between FIGS. 4 (c) and 5 (c). This is
Also between the voltage waveform applied to the picture element A _{x + 1,4y + 1} shown in FIG. 5 (c) and the voltage waveform applied to the picture element A _{x, 4y + 2} shown in FIG. 4 (d), and also in FIG. Picture element A shown in (d)
_{The same} is true between the voltage waveform applied to _{x, 4y + 2} and the voltage waveform applied to the picture element A _{x + 1,4y + 2} shown in FIG. 5 (d). That is, as shown in Table 3, the phase of the applied voltage waveform is deviated from each other by one frame period between the picture elements in this unit, with one picture element corresponding to 8 picture elements of 2 columns × 4 rows. Therefore, when a plurality of continuous picture elements are displayed in the same gradation, the phases of the voltage waveforms applied to the respective picture elements are not synchronized. Therefore, the thinning-out processing frequency with one cycle of a plurality of frame periods is set to 40 Hz or less. Without flicker,
A good display quality can be obtained.

In this embodiment, the case of gradation display by the liquid crystal display device has been described, but the present invention is not limited to this, and a case where a still image is gradation-displayed on another display device such as a display device using an electroluminescent element is also applicable. The same applies.

EFFECTS OF THE INVENTION As described above, according to the display device of the present invention, (1) in addition to the device used for non-gradation display, a frame discriminating means, a line discriminating means, and a data thinning means are separately added. Only with this, gradation display can be easily performed.

(2) Also, by combining the display control circuit for the pulse width modulation method and the general drive circuit for non-gradation display,
It is also possible to perform gradation display.

(3) Further, as compared with a conventional thinning-out type display device in which thinning-out processing is performed only on the basis of a frame discrimination signal,
When a plurality of consecutive picture elements are displayed in the same gradation, the phases of the voltage waveforms applied to the respective picture elements are not synchronized,
The frequency of the decimation process with multiple frame periods as one cycle
Even if it is 40 Hz or less, flicker does not occur and good display quality can be obtained.

In particular, according to the present invention, the data thinning-out means (a) outputs each bit of the multi-bit DH, DM, DL bit-parallel gradation data such that the output number of the high-order digit is larger than the output number of the lower-order digit. In addition, (b) the periodic predetermined order of outputting the digits for each frame by the number of times corresponding to the weight of each digit and selectively outputting each digit is set between the plurality of predetermined scan lines. And (c) selectively change the periodic order of selecting each digit for each frame between adjacent picture elements on the same scanning line so as to be different from each other.
This makes it possible to further eliminate the occurrence of flicker.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a display data generating circuit 7 of the display device, and FIG. 3 is a display thereof. A schematic view showing a part of the electrode arrangement configuration of the liquid crystal display element of the device,
FIG. 4 is a timing chart showing the driving of picture elements on the data side electrodes of the even columns of the display device, and FIG. 5 is a timing chart showing the driving of picture elements on the data side electrodes of the odd column of the display device. is there. 1 ... Liquid crystal display element, 2 ... Data side liquid crystal drive circuit, 3
...... Scanning side liquid crystal drive circuit, 4 ...... Liquid crystal drive partial pressure generation circuit, 5 ...... AC inversion signal generation circuit, 6 ...... Liquid crystal display control circuit, 7 ...... Display data generation circuit, 8 ...... Frame discrimination circuit , 12 …… Line discrimination circuit, 18a …… Even column data thinning circuit, 18b …… Odd column data thinning circuit

Claims (1)

[Claims] 1. A plurality of picture elements arranged in a matrix are arranged in a row direction of picture elements in a state in which a potential corresponding to display data is applied to a plurality of data side electrodes arranged in the column direction of the picture elements. In a display device which is driven by sequentially applying a selection potential to the plurality of scanning-side electrodes and completes the display of one frame, a plurality of bits of grayscale data for performing grayscale display on the picture elements are displayed. Based on the grayscale data output means for outputting in association with the picture element and the frame start signal for giving the start timing of the frame, a frame discrimination signal for discriminating each frame within the period with a period for a plurality of frames as one period The frame discrimination means for outputting and the scanning side electrode to which the selection potential is applied are switched and designated, and the potential corresponding to the display data of the picture element is applied to the data side electrode on the designated scanning side electrode. Based on the order of the data latch signal and said frame discrimination signal, a line discriminating means for outputting a line discrimination signal for discriminating the scanning lines in the frame, a data thinning means, the data reducing means,
As the display data of the picture element in each scanning line of each frame discriminated by the frame discrimination signal and the line discrimination signal, each bit of the gradation data is set so that the output number of the high-order digit is larger than the output number of the lower-order digit. The number of times corresponding to the weight of each digit is output over the one cycle, and each digit is selected and output for each frame. Shift,
A display device, comprising: data thinning means for selectively changing the periodic order of selecting each digit for each frame between adjacent picture elements on the same scanning line so as to be different from each other.