JPH0789281B2 - Redundant transmission device automatic switching device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic switching device for a duplex transmission device, which automatically switches between a main system and a slave system of the duplex transmission device using a programmable controller.

2. Description of the Related Art In general, when a programmable controller (hereinafter referred to as a PC) is used to perform process control, the PC is duplicated in order to improve the control reliability.

Problems to be solved by the invention Normally, as a means for duplicating PCs, the same PC is connected in parallel to the bus, and one is set as the master PC and the other is set as the slave PC.
PC is the slave setting element (this element is usually a manual switch)
It is provided on the substrate on which the CPU and other components that compose the are attached. This setting element is usually set so that the master PC operates, and when the master PC fails, the slave PC operates the slave PC setting element to operate the slave PC. .

However, when a failure occurs, the setting element is manually switched, so that the switching operation cannot be performed instantaneously, which may seriously hinder the process control.

Means and Actions for Solving Problems This invention sets the determination signal of the master PC or the slave PC to zero potential or to the positive potential, and the setting signal and the master PC are set.
When the judgment signal is given to the judgment unit and it is judged that the master PC has become inactive, the judgment signal and the master / slave switching information exchange signal are used. A switching signal is sent from the master / slave switching unit to automatically switch to the conventional PC when the master PC fails, and to automatically switch from the slave PC to the master PC when the master PC recovers from the failure.

Embodiment Hereinafter, the present invention will be described based on an embodiment with reference to the drawings.

In Fig. 1, 1 and 2 are a master PC and a slave PC connected in parallel between the bus lines 3 and 4. Normally, the master PC1 is connected between the bus lines 3 and 4, and the slave PC2 is usually It is electrically disconnected from between the bus lines 3 and 4. Reference numeral 5 is a master / slave system determination signal sending section for judging whether the master system PC 1 or the slave PC 2 is provided.
A predetermined determination signal is given from 1 and the slave PC 2.
The signal judged by the sending unit 5 is input to the master / slave PC operation / non-operation judging unit 6. A signal from an operation detection signal transmitting section 7 for detecting which of the master PC 1 and the slave PC 2 is operating is input to the determination section 6. Judgment unit 6 is a sending unit
A signal from 5 or 7 is used to judge whether the main system PC1 is operating or not, and a switching signal is given to the main system sub system switching unit 8. An information exchange signal for switching the master system and the slave system is given to the switching unit 8 from the transmitting unit 9. As a result, the switching unit 8
Sends a signal for switching the operation from the master PC1 to the slave PC2.

With the above-described configuration, when the main system PC1 fails, the operation detection signal transmission unit 7 causes the determination unit 6 to operate on the main system PC1.
The non-operation signal of is input. The judging section 6 judges from the judgment signal from the sending section 5 and gives the judgment signal to the switching section 8.
The switching unit 8 switches and connects the bus lines 3 and 4 to the slave PC 2 based on the relationship between the input judgment signal and the switching information exchange signal.

Next, an example for carrying out FIG. 1 is shown in FIG. 2 and FIG. FIG. 2 shows a mother board 11 on which a printed circuit board (not shown) that constitutes a main PC1 and a slave PC2 is mounted, and patterns 12 and 13 of positive potential lines and zero potential lines are formed on the mother board 11. . The circles in the drawing are connector (not shown) mounting portions for mounting a printed circuit board. The portion surrounded by the broken line 14 in the drawing is for the master PC, and the portion surrounded by the broken line 15 is for the slave PC. Of the circles, reference numeral 14a is connected to the zero potential line pattern 13, and reference numeral 15a is connected to the positive potential line pattern 12. Further, reference numerals 14b and 15b are connected by a common connection line 16 and are used as an information exchange signal line MASACTL (hereinafter referred to as MTL) for switching a main system and a slave system. This FIG. 2 is for obtaining the signals transmitted from the master-slave system determination signal transmitter 5, the operation detection signal transmitter 7, and the information exchange signal transmitter 9 shown in FIG.

FIG. 3 shows the judging unit 6 and the main / slave switching unit 8 of FIG.
In particular, FIG. 3 is a circuit configuration diagram of only the main system, and the slave system also has the same circuit configuration.

In FIG. 3, reference numeral 21 is the signal MAS of reference numeral 14a shown in FIG.
The first NOT circuit to which TERL (hereinafter referred to as STL) is input, and the output signal of this first NOT circuit 21 is the open collector first NAN.
It is supplied to the first input of the D circuit 22. The PC operation signal OWNACTH (hereinafter referred to as OWH) is input to the second input of the first NAND circuit 22. This operation signal OWH is sent from the operation detection signal sending unit 7 in FIG. The output terminal of the first NAND circuit 22 is connected to the power supply line via the pull-up resistor 23 and also connected to the information exchange signal line MTL. 24 is the second NA
In the ND circuit, the output signal of the first NAND circuit 22 is supplied to the first input of the circuit 24, and the output signal of the first NOT circuit 21 is supplied to the second input. Reference numeral 25 is a third NAND circuit. The output signal of the first NAND circuit 22 is input to the second NOT of the third NAND circuit 25 at its first input.
The signal inverted by the circuit 26 is input, and the signal is input to the second input.
The signal OWH is input to the STL and the third input, respectively. 2nd N
The output signals of the AND circuit 24 and the third NAND circuit 25 are
It is input to the 4NAND circuit 27. The output signal of the fourth NAND circuit 27 is input to the first and second timer circuits 28 and 29, the first timer circuit 28 starts its operation at the rising edge of the signal, and the second timer circuit 29 operates at the falling edge of the signal. It is the one to start. The output signals {T ₁ (timer value of the first timer circuit), T ₂ (timer value of the second timer circuit)} of both timer circuits 28 and 29 are NO.
It is supplied to the input terminal C of the D-type flip-flop 31 through the R circuit 30. The input end D of the D-type flip-flop 31 has a
The output signal of the 4NAND circuit 27 is inverted by the third NOT circuit 32 and supplied. The output signal of the D-type flip-flop 31 is the first and second A
It is supplied to the first inputs of the ND circuits 33 and 34. The first AND circuit 33 is a gate for transmitting the transmission data TXDATA to the transmission path, and the internal transmission transmission data TXH is input to its second input. Also,
The second AND circuit 34 is a gate for fetching the reception data RXDATA from the transmission line, the reception data is input to the second input, and the internal transmission reception data RXH is obtained at the output.

Next, the operation of the circuit configuration shown in FIG. 3 will be described with reference to FIGS. 4 to 7. First, to describe each signal, the signal ST
L is the input from the master PC or slave PC determined by the position of the bus line. If it is the master PC, it is judged as logic "0", and if it is slave, it is judged as logic "1". The signal is sent out. Further, the signal OWH indicates that the own system is in operation. When it is in operation, it becomes a logic "1" and becomes a logic "0" due to a failure or stop of the internal processor. This signal is sent from the operation detection signal sending unit 7. To be done. The initial signal INITL is sent when the power is turned on, and has a signal of logic "0".

Next, the case where the main PC is operating by the timing chart will be described. In FIG. 4, when the main system PC itself changes from operating to non-operating at time (a), the output H of the flip-flop 31 becomes logic "0" at time (b). Then, the gates of the first and second AND circuits 33 and 34 are closed, and transmission to the outside and reception from the outside are stopped. At the time point (c), the main system PC returns from non-operation to the operation, and at the time point (d) after the elapse of the timer T ₂ time from this point, the output H of the flip-flop 31 becomes “1” and the first and second AND circuit
The gates of 33 and 34 are opened, and the transmission and reception of data can be performed.

FIG. 5 shows a timing chart of a subordinate system, which is operated as shown in FIG. 5 by a circuit configured similarly to FIG. In FIG. 5, at time (a), the non-operation of the master PC is identified, and at time (b), the output H of the flip-flop (not shown) on the slave side becomes logic "1" instead of the master PC. Communication with the outside becomes possible and the slave PC becomes operable from the master PC. When the master PC is restored at the time (c) and starts to operate, the output H of the flip-flop becomes logic "0" at the time (d) and the slave PC cannot communicate with the outside.

When a non-operation such as a failure of the master PC is detected as described above, the slave PC automatically operates in place of the master PC, and when the master PC returns, the slave system returns to the waiting state again.

Fig. 6 shows that when the subordinate system becomes a failure, etc. while the subordinate system is communicating with the outside on behalf of the main system PC at the time (b), it becomes inactive at the time (c) and ) Is a timing chart when interrupting the external communication of the subordinate.

FIG. 7 shows a timing chart at the time of initialization.
The timer circuits 28 and 29 are operated in both the subordinate system and the third NO in FIG.
The output of the T circuit 32 is sampled by the flip-flop 31,
The output of flip-flop 31 is set to H. Here, the output indicates the state of whether external communication is possible regardless of the master system and the slave system. = 0 means no communication, = 1 means communication is possible. The arrow (a) in FIG. 7 indicates that either the first or second timer circuit 28 or 29 is driven in the state of the output D of the fourth NAND circuit 27, and the timer circuit 28 is operated when the output D = 1. When the output D = 0, the timer circuit 29 is operated.

In addition, comparing FIG. 4 and FIG. 5, it is found that T ₁ <T ₂ .
This disconnects the PC that becomes inactive for communication with the outside early, delays the communication of the PC for communication with the outside, and sets the timer values T ₁ and T ₂ in order to prevent both sides from communicating. Set different values. Also, when the main system PC is unplugged by a hot line, the signal logic of the bus signal MTL is always set to zero when it is in operation. Enabled to detect motion.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is not necessary to preset the master / slave of the duplexed transmission device.
Moreover, since the switching of the master / slave system is automatically performed at the time of a failure, the master / slave setting element can be omitted. Also, even if the main system is pulled out by the hot line, it automatically switches to the slave system, so it does not affect the process control, and it is possible to switch so that both the master and slave systems do not enter the communication state at the same time. Fast switching is possible because there is no CPU intervention. Further, there is an advantage that a changeover connection can be made without using a mechanical changeover switch.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIGS. 2 and 3 show an embodiment of the present invention. FIG. 2 shows the arrangement state of a main system slave PC mounted on a mother board. FIG. 3 is a circuit diagram showing a concrete embodiment of the judgment unit and the main / slave switching unit shown in FIG. 1, and FIGS. 4 to 7 show the operation of the above embodiment. It is a timing chart for explaining. 1 ... Master PC, 2 ... Slave PC, 5 ... Master / Slave judgment signal sending unit, 6 ... Judgment unit, 7 ... Motion detection signal sending unit, 8 ...
… Main / slave switching unit, 9 …… Signal sending unit for information exchange.

Claims (1)

[Claims] 1. A duplex system formed by connecting a main programmable controller and a slave programmable controller in parallel to a bus line for duplexing, and switching to the latter controller when the former controller becomes unable to transmit. In the transmission device, an operation determination signal of the main programmable controller or the slave programmable controller is set in advance, and a master-slave system determination signal sending unit that determines whether the operation is the main system programmable controller or the slave programmable controller by the determination signal, An operation detection signal transmitting section for detecting whether the main programmable controller or the slave programmable controller is operating, and the output signals of this operation detection signal transmitting section and the main / slave determination signal transmitting section are input, and from this output signal Which type of programmer The control unit that determines whether or not the programmable controller is operating and which system's programmable controller is not operating, and the determination output signal from this determination unit, and the master / slave switching information exchange signal. Is given, and when switching from both signals to the normal system of the main system and the slave system programmable controller, the programmable controller that becomes inactive for communication with the outside is cut off early, and the programmable controller An automatic switching device for a duplexed transmission device, comprising: a main-slave switching unit that switches communication so as to be delayed.