JPH0789436B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory) and, for example, relates to a technique effectively applied to a dynamic RAM including a read-modify-write function. It is a thing.

[Background technology]

The read-modify-write function is known as one of the operations in the dynamic RAM (see Nikkei Electronics, April 18, 1977, pages 65 to 73).

In the conventional dynamic RAM, since the data input buffer is operated by the timing signal formed by the write enable signal ▲ ▼, for example, the wasteful operating time for the read / modify / write operation is It has been clarified by the research of the inventor of the present invention that this occurs. In other words, read modify
In the write operation, the read operation is performed first, so even though the memory array is already in the selected state, the data input buffer becomes the operation state and the write signal is set after the write enable signal ▲ ▼ becomes the low level. Is taken in, the operating time is added to the write cycle.

[Object of the Invention]

It is an object of the present invention to provide a dynamic RAM which has a simple structure and has a high speed.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the data input buffer is made to operate by the timing signal of the row system so that the writing to the memory array can be performed immediately by the low level of the write enable signal.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of a dynamic RAM according to the present invention.

In the embodiment circuit shown in the figure, an IGFET (Insulated Gate Field Effect Transistor) typified by an n-channel MOSFET is used.
tor) as an example.

The 1-bit memory cell MC has an information storage capacitor Cs and an address selection MOSFET as shown as a representative.
The information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not. To read information, turn on the MOSFET Qm, connect the capacitor Cs to the common data line DL, and sense how the potential of the data line DL changes according to the amount of charge accumulated in the capacitor Cs. Done by

Since the memory cell MC is formed small and many memory cells are connected to the common data line DL to form a highly integrated and large capacity memory matrix, the capacitor Cs and the stray capacitance Co of the common data line DL (Fig. The relationship with (not shown) is Cs / C
The ratio of o becomes a very small value. Therefore, the potential change of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very minute signal. A dummy cell DC is provided as a reference for detecting such a minute signal. The dummy cell DC is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is about half that of the capacitor Cs of the memory cell MC. The capacitor Cd is charged to the ground potential by the MOSFET Qd 'prior to addressing.

As described above, the capacitor Cd is set to have a capacitance value which is about half that of the capacitor Cs, and therefore forms a reference voltage that is approximately half the read signal from the memory cell MC.

In the figure, SA is a sense amplifier that expands such a potential change difference caused by the addressing to a sense period determined by timing signals (sense amplifier control signals) φ _pa1 and φ _pa2 (the operation will be described later). The input / output node is coupled to a pair of complementary data lines DL, ▲ arranged in parallel. Complementary data line DL, ▲ ▼
The number of memory cells coupled to is equalized in order to improve the detection accuracy, and is set to 1 for each complementary data line DL, ▲ ▼.
Dummy cells are individually connected. Further, each memory cell MC is coupled at the intersection of one word line WL and one of the complementary data lines. Since each word line WL intersects with both data line pairs, even if the noise component generated in the word line WL is on the data line due to electrostatic coupling, the noise component is generated in both data line pairs DL, ▲ ▼. And appear to be canceled by the differential sense amplifier SA.

In the above addressing, complementary data line DL, ▲
One of the pair of dummy word lines DWL, ▲ ▼ is selected so that when the memory cell MC coupled to one of the ▼ is selected, the dummy cell DC is always coupled to the other data line.

The sense amplifier SA is composed of a pair of cross-connected MOSFETQs.
1 and Q2, and by these positive feedback action, complementary data line
The small signal appearing on DL, ▲ ▼ is differentially amplified.
This positive feedback operation is performed in two stages and is started at the same time when the _MOSFET Q7 having a relatively small conductance characteristic starts to conduct by the relatively early timing signal φ _pa1 , and the complementary data line DL,
Based on the potential difference given to ▼, the higher data line potential is slower and the lower data line potential is faster, and the difference spreads while the difference spreads. At this time, the _{MOSFET Q8} having a relatively large conductance characteristic is _{turned on} by the timing signal φ _{pa2 at the} timing when the difference potential becomes large to some extent, so that the lower data line potential is rapidly lowered. In this way, the operation of the sense amplifier SA is performed in two stages, so that the higher potential drop is prevented. Thus, when the lower potential drops below the threshold voltage of the cross-coupled MOSFET, the positive feedback operation ends,
The fall of the higher potential stays at a potential lower than the power supply voltage V _{cc and} higher than the threshold voltage, and the lower potential finally reaches the ground potential (0V).

During the above addressing, the stored information in the memory cell MC which is about to be destroyed is restored by directly receiving the high level or low level potential obtained by the sensing operation. However, if the high level falls to a certain level or more with respect to the power supply voltage V _cc as described above, a malfunction occurs where it is read as a logic "0" during repeated reading and rewriting. The active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR
Has a function of selectively boosting the high level signal to the potential of the power supply voltage V _cc without affecting the low level signal.

Data line pair DL, which is shown as a representative in the figure, ▲
▼ is connected to the common complementary data line pair CDL, ▲ ▼ via MOSFETs Q3 and Q4 that form the column switch CW. For the data line pair shown as another representative, the common complementary data line pair CDL,
Connected to ▲ ▼. This common complementary data line pair CD
L and ▲ ▼ are connected to the input terminal of the data output buffer DOB including the output amplifier and the output terminal of the data input buffer DIB. Although not particularly limited, in this embodiment, the data input buffer DIB is an input buffer that is activated by the timing signal φ _in and a drive that receives this output signal and forms a drive signal for the common complementary data line CDL, ▲ ▼. Write enable signal to the circuit and this drive output ▲
The drive output signal is transferred to the common complementary data line CDL, ▲ by the timing signal (not shown) formed by ▼.
And a gate circuit for transmitting to ▼.

The row decoder and column decoder R, C-DCR receives the internal complementary address signal processed and processed in the address buffer ADB, forms one word line and dummy word line, and a column switch selection signal to form a memory cell and a dummy cell. Addressing. That is, the address buffer ADB processes and forms the internal complementary address signal in accordance with the applied external address signals AX0 to AXi, and synchronizes with the timing signal φ _ar formed by the row address strobe signal ▲ ▼. To the row decoder R-DCR. The row decoder R-DCR receives the internal complementary address signal and the word line selection timing signal φx and performs a predetermined word line and dummy word line selection operation. Further, the address buffer ADB processes and forms an internal complementary address signal according to the applied external address signals AY0 to AYi, and a column address strobe signal ▲
In synchronization with the timing signal φ _ac formed by ▼,
It is sent to the column decoder C-DCR. The column decoder C-DCR receives the internal complementary address signal and the data line selection timing signal φy and performs a data line selection operation.

The timing generation circuit TG is not particularly limited, but the row address strobe signal ▲ ▼ and the column address strobe signal ▲ ▼ respectively supplied from the external terminals.
And a write enable signal (5) to form various timing signals necessary for the above operation.

Next, the read-modify-write operation in the dynamic RAM of this embodiment will be described with reference to the timing chart shown in FIG.

The supplied address signal Ai is taken in as a row address signal AX (AX0 to AXi) in synchronization with the change of the row level of the row address strobe signal {circle around ()} and transmitted to the row address decoder R-DCR. As a result, the word line selecting operation designated by the address signal Ai is performed.

Then, the next supplied address signal Ai is taken in as a column address signal AY (AY0 to AYi) in synchronization with the column address strobe signal (), and transmitted to the column address decoder C-DCR. As a result, the data line selection operation is performed.

In this embodiment, the row address strobe signal ▲
An input circuit that configures the data input buffer DIB by setting the row-related timing signal formed at the low level of ▼, for example, the timing signal φ _in formed by the same timing signal as the operation timing signal φ _ar of the row address buffer to the high level. Is to be put into operation.

The read signal of the memory cell selected by the addressing of the memory array MARY is sent from the output terminal while the data output buffer DOB is in operation by the high level of the timing signal φ _op formed by the column timing signal. After the read operation is completed, when the write enable signal ▲ ▼ is set to the low level, the drive signal already formed by the data input buffer DIB is generated by the timing signal formed together with the low level of the write enable signal ▲ ▼. Is transmitted to the common complementary data line CDL, ▲ ▼,
Writing is immediately performed to the selected memory cell.

〔effect〕

(1) The data input buffer can be operated by the row-related timing signal and the already formed write drive signal can be immediately written to the memory array in synchronization with the low level of the write enable signal. Therefore, the signal delay time in the data input buffer can be substantially eliminated as compared with the case where the operation of the data input buffer is started after the write enable signal becomes low level and the data input buffer is fetched. As a result, the effect that the write operation after the read operation can be performed at high speed is obtained.

(2) Due to the above (1), multiple memory arrays MARY
Are simultaneously addressed, and a multi-bit signal is serially written or read to or from each memory array. In nibble mode, byte mode, etc., multiple bits are written or read by one address setting. Since the above-mentioned delay time can be eliminated by applying the present invention, the effect that the operation time as a whole can be greatly shortened, in other words, the operation speed can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the timing signal φ _in that activates the data input buffer does not necessarily have to be the same timing signal as the row address signal, and is already at the latest when the write enable signal ▲ ▼ in the read-modify-write operation becomes low level. Any device may be used as long as it uses a row timing signal capable of forming a write drive signal. Further, the specific circuit configuration of the peripheral circuits such as the address buffer, the address decoder, the data input buffer, the data output buffer, etc. can take various embodiments.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used for a dynamic RAM that multiplexes and supplies an external address signal using an address strobe signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM to which the present invention is applied, and FIG. 2 is a timing chart showing an example of the read-modify-write operation. MC ... Memory cell, DC ... Dummy cell, CW ... Column switch, SA ... Sense amplifier, AR ... Active restore circuit, RC-DCR ... Row / column decoder, ADB ... Address buffer, DOB ... Data Output buffer, DIB ...
Data input buffer, TG ... Timing generator

Claims (1)

[Claims] 1. A row address buffer and a column address buffer for fetching an external address signal multiplexed and supplied in synchronization with a row address strobe signal and a column address strobe signal, respectively, and fetched by the row address buffer and the column address buffer. An address selection circuit for forming a selection signal of a memory array in which a dynamic memory cell composed of an information storage capacitor and an address selection MOSFET is arranged in a matrix by the generated address signal, and formed based on the row address strobe signal. The write signal supplied from the data input pin can be fetched until the operation is started by the row timing signal and the write enable signal at the read-modify-write operation becomes active level. Input buffer, a drive circuit for receiving the write signal fetched by the input buffer and forming a write drive signal, and a drive signal formed by the drive circuit in synchronization with the change of the write enable signal to the active level. And a data input buffer including a gate circuit for transmitting the data to the memory array.