JPH0789440B2 - Write protect circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write inhibit circuit, and more particularly to a write-free EEPROM (el
ctrically erasable programmable read only memory)
Write protection circuit.

2. Description of the Related Art Conventionally, in this type of EEPROM write inhibit circuit, the EEPROM is controlled by controlling the chip enable (CE) terminal.
Writing to was prohibited.

In such a conventional EEPROM write inhibit circuit, the chip enable pin was controlled to inhibit writing to the EEPROM.
If writing to the EEPROM is prohibited, reading of the EEPROM is also prohibited at the same time, and it will not be possible to perform checks such as sum check and parity check by reading the entire contents of the EEPROM. Therefore, determine whether the EEPROM is normal or abnormal. There is a drawback that you can not do it.

Also, the chip enable terminal is generally enabled at a low level, and the chip enable terminal is not always fixed at a high level when the power is off, so there is a risk of writing to the EEPROM. There are drawbacks.

On the other hand, it is conceivable that writing is prohibited by controlling the write enable terminal. However, with this method, writing to the EEPROM can be prohibited without prohibiting reading from or writing to the EEPROM by controlling the write enable pin when the power is turned on, but the write enable pin is at the low level like the chip enable pin. Since it is generally enabled at, and it is not always fixed at the high level when the power is off, there is a disadvantage that writing to the EEPROM is risky.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional one. Even if writing to the EEPROM is prohibited when the power is turned on, reading from the EEPROM is performed to judge whether the EEPROM is normal or abnormal. It is an object of the present invention to provide a write inhibit circuit that can be performed and that can prevent erroneous data writing to the EEPROM by putting the EEPROM in a write inhibit state when the power is turned off.

The write-inhibit circuit according to the present invention is capable of electrically writing and erasing data, and writing in a read-on memory in which write-inhibition is performed by applying a signal of a predetermined level to the output enable terminal. A gate which outputs the read signal to the output enable terminal when a read signal of the data is input and a control signal of the ground potential is input, and one terminal is the output enable terminal. A switch which is connected to the control signal input terminal of the gate and which supplies a signal of ground potential to the output enable terminal when write is prohibited; and the other terminal of the switch is other than ground potential. And a circuit for applying a signal of earth potential to the output enable terminal It is characterized by

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the address bus 4 from the microprocessor 1 is EE
The data bus 5 from the microprocessor 1 is connected to the address terminal AB of the PROM2 and the data terminal DB of the EEPROM2. The write signal 6 output from the microprocessor 1 is input to the write enable terminal ▲ ▼ of the EEPROM 2 via the buffer 9 whose control terminal is fixed to the ground potential.

A higher-order address signal of the address signals output from the microprocessor 1 via the address bus 4 is decoded by the decoder 3 and input to the chip enable terminal ▲ ▼ of the EEPROM 2, and the EEPROM 2 is read by the decoded address signal. It is configured to be accessible.

The read signal 7 output from the microprocessor 1 is
It is input to the output enable terminal ▲ ▼ of the EEPROM 2 via the buffer 10 of 3-state output. buffer
Reference numeral 10 is controlled by a signal from the write terminal a of the write inhibit selection switch 8.

The write terminal a and the write inhibit terminal b of the write inhibit selection switch 8 are connected to the power supply (+5
Connected to V). In the write inhibit selection switch 8, when the write terminal a is selected and becomes writable, the write terminal a is fixed to the ground potential, and when the write inhibit terminal b is selected and the write is prohibited, write inhibit is performed. The terminal b is fixed to the ground potential.

The signal from the write terminal a controls the output of the buffer 10 and is input to the output enable terminal ▲ ▼ of the EEPROM 2 via the inverter 11 having an open collector output. Also, the signal from the write inhibit terminal b is EEPR
It is input to the output enable terminal ▲ ▼ of OM2.

In this circuit, the output enable terminal ▲ ▼ is fixed to the ground potential in the write-protected state when the power is turned on.
EEPROM2 can be read, and writing is fixed to the prohibited state.

Further, even when the contacts of the write-protect selection switch 8 are floating when the write-protect selection switch 8 is switched,
Since the output of the inverter 11 becomes the ground potential, the readable state and the write-protected state are maintained.

When the write-protect selection switch 8 is in the write-enabled state,
Since the buffer 10 is enabled and the read signal 7 is input to the output enable terminal ▲ ▼, EEPR
Writing to OM2 is possible.

Further, when the write-prohibit selection switch 8 is set to the write-prohibited state and the power is turned off, the power is turned off with the output enable terminal ▲ ▼ kept at the ground potential. Therefore, it is not written when the power is turned on. Absent.

As described above, when the write-prohibited state is selected by the write-prohibit selection switch 8, by fixing the output enable terminal ▲ ▼ of the EEPROM2 to the ground potential, writing to the EEPROM2 is prohibited when the power is turned on, but reading is performed. Even if writing to EEPROM2 is prohibited, it is possible to perform checks such as sum check and parity check by reading data from EEPROM2.
It is possible to judge whether PROM2 is normal or abnormal. Also,
Even if the power is turned off, erroneous data will not be written to EEPROM2 if the write-protection state is set.

As described above, according to the present invention, the output enable terminal is always fixed to the ground potential except when writing data, so that the EE is generated when the power is turned on.
Even if writing to the PROM is prohibited, it is possible to read from the EEPROM to judge whether the EEPROM is normal or abnormal. By writing the EEPROM to the write-disabled state when the power is off, you can write incorrect data to the EEPROM. The effect is that it can be prevented.

[Brief description of drawings]

 FIG. 1 is a circuit diagram showing an embodiment of the present invention. Explanation of main part code 2 …… EEPROM 3 …… Decoder 7 …… Read signal 8 …… Write prohibition selection switch 9 …… Buffer 10 …… Inverter ▲ ▼ …… Output enable terminal a …… Write terminal b …… Write protect terminal

Claims (1)

[Claims] 1. A write-inhibit circuit for a read-only memory, which is capable of electrically writing and erasing data and which is write-inhibited by applying a signal of a predetermined level to an output enable terminal, A gate for inputting the data read signal and outputting the read signal to the output enable terminal when a ground potential control signal is input, and one terminal connected to the output enable terminal and the other terminal A switch whose terminal is connected to the control signal input terminal of the gate and which gives a signal of the ground potential to the output enable terminal when write is prohibited; and the output enable terminal when the other terminal of the switch is other than the ground potential. Write-protection characterized by being configured with a circuit for applying a signal of ground potential to Road.