JPH0789551B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0789551B2 JPH0789551B2 JP61030023A JP3002386A JPH0789551B2 JP H0789551 B2 JPH0789551 B2 JP H0789551B2 JP 61030023 A JP61030023 A JP 61030023A JP 3002386 A JP3002386 A JP 3002386A JP H0789551 B2 JPH0789551 B2 JP H0789551B2
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- semiconductor device
- active layer
- insulating film
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000002184 metal Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 239000010410 layer Substances 0.000 description 9
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止型半導体装置
に関する。The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
従来、技術封止型半導体装置の耐温度サイクル性の向上
は、封止樹脂材料の改良で対処されて来ていた。Conventionally, the improvement of the temperature cycle resistance of the technically sealed semiconductor device has been dealt with by the improvement of the sealing resin material.
従来の樹脂封止型半導体装置においては、第３図に示す
ように、酸化シリコン膜３上に形成されたAlからなる金
属配線４は、温度サイクルにより酸化シリコン膜３との
接触部4Aからはがされた断線を生じる場合があり、又多
層配線構造の場合は層間絶縁膜に亀裂を生じ、上下の金
属配線が短絡するという問題点があった。尚、第３図に
おいて、１はシリコン基板、２は活性層、５は開孔部、
６はパッシベーション膜である。In the conventional resin-encapsulated semiconductor device, as shown in FIG. 3, the metal wiring 4 made of Al formed on the silicon oxide film 3 is separated from the contact portion 4A with the silicon oxide film 3 by the temperature cycle. There is a problem in that a broken wire may occur, and in the case of a multilayer wiring structure, a crack is generated in the interlayer insulating film and the upper and lower metal wirings are short-circuited. In FIG. 3, 1 is a silicon substrate, 2 is an active layer, 5 is an opening,
6 is a passivation film.
耐温度サイクル性を向上させる為に改良された樹脂材料
を用いて諷刺された半導体装置は、樹脂材料の価格が高
くなる為に製造コストが上昇する。又、耐温度サイクル
性を向上させた樹脂を用いると熱伝導率が下り、高電力
損失のLSIの冷却に支障が出たりする等の別の問題点を
生じる。A semiconductor device stabbed using a resin material improved to improve temperature cycle resistance has a high manufacturing cost because the price of the resin material increases. In addition, if a resin having improved temperature cycle resistance is used, the thermal conductivity is lowered, and another problem such as a hindrance to cooling of a high power loss LSI occurs.
本発明の目的は、改良された樹脂を用いる事なく耐温度
サイクル性の向上した半導体装置を提供することにあ
る。An object of the present invention is to provide a semiconductor device having improved temperature cycle resistance without using an improved resin.
本発明の半導体装置は、半導体基板表面に設けられた活
性層と、この活性層上に設けられた絶縁膜と、この絶縁
膜上に設けられかつ絶縁膜に設けられた開孔部を通して
前記活性層に接続する金属配線とを有する半導体装置で
あって、前記金属配線は、この金属配線の幅又は長さ方
向でかつ所定の幅及び所定の深さで前記絶縁膜に設けら
れた断面形状がＵ字形でかつストライプ状の浅い溝上に
形成されているものである。The semiconductor device of the present invention is characterized in that the active layer is provided through the active layer provided on the surface of the semiconductor substrate, the insulating film provided on the active layer, and the opening provided on the insulating film. A semiconductor device having a metal wiring connected to a layer, wherein the metal wiring has a cross-sectional shape provided in the insulating film in a width or length direction of the metal wiring and having a predetermined width and predetermined depth. It is formed on a U-shaped and stripe-shaped shallow groove.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ′線断面図である。1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention.
第１図（ａ），（ｂ）において、シリコン基板１の表面
にはトランジスタや抵抗等が設けられた活性層２とその
上に酸化シリコン膜３が形成されている。そして、この
酸化シリコン膜３には開孔部５と複数の浅い溝７が形成
されているが、特にこの浅い溝７は、金属配線の幅方向
に所定の幅及び所定の深さで、かつ断面形状がＵ字形で
ストライプ状に形成されている。更に酸化シリコン膜３
上には、溝７上に設けられかつ開孔部５を通して活性層
２に接続するAl等からなる金属配線４が形成されてい
る。尚、６はパッシベーション膜である。In FIGS. 1A and 1B, an active layer 2 provided with transistors, resistors and the like is formed on the surface of a silicon substrate 1, and a silicon oxide film 3 is formed thereon. The silicon oxide film 3 has an opening 5 and a plurality of shallow grooves 7. The shallow groove 7 has a predetermined width and a predetermined depth in the width direction of the metal wiring, and The U-shaped cross section is formed in a stripe shape. Furthermore, silicon oxide film 3
A metal wiring 4 made of Al or the like, which is provided on the groove 7 and is connected to the active layer 2 through the opening 5, is formed thereover. Incidentally, 6 is a passivation film.
このように構成された本実施例においては、酸化シリコ
ン膜３上に形成された溝７に金属配線４が埋込まれて形
成されている為、金属配線４と酸化シリコン膜３との密
着強度が強くなり、温度サイクルが加わっても金属配線
がはかれて断線を生じる事はなくなる。In this embodiment having such a configuration, the metal wiring 4 is embedded in the groove 7 formed on the silicon oxide film 3, so that the adhesion strength between the metal wiring 4 and the silicon oxide film 3 is high. Becomes stronger, and even if a temperature cycle is applied, the metal wiring will not be peeled off to cause disconnection.
第２図（ａ），（ｂ）は本発明の第２の実施例の平面図
及びＢ−Ｂ′線断面図であり、第１の実施例と異る所は
酸化シリコン膜上の溝が金属配線の長手方向に形成され
ていることである。2 (a) and 2 (b) are a plan view and a sectional view taken along the line BB 'of the second embodiment of the present invention. The difference from the first embodiment is that the groove on the silicon oxide film is That is, it is formed in the longitudinal direction of the metal wiring.
すなわち、第２図（ａ），（ｂ）において、シリコン基
板１上に形成された酸化シリコン膜３には、開孔部５と
浅に溝7Aが形成されているが、この溝7Aは金属細線４の
長手方向に形成されている。そして、この溝7Aを埋めて
活性層２に接続する金属配線４が形成されている。That is, in FIGS. 2A and 2B, the silicon oxide film 3 formed on the silicon substrate 1 has a hole 7A and a shallow groove 7A. The groove 7A is made of metal. It is formed in the longitudinal direction of the thin wire 4. Then, the metal wiring 4 which fills the groove 7A and is connected to the active layer 2 is formed.
この第２の実施例においても、金属配線４と酸化シリコ
ン膜３との密着強度は強く、第１の実施例の場合と同様
に、温度サイクルによっても金属配線４がはがれて断線
を生じることはない。Also in the second embodiment, the adhesion strength between the metal wiring 4 and the silicon oxide film 3 is strong, and as in the case of the first embodiment, the metal wiring 4 is peeled off due to the temperature cycle to cause a disconnection. Absent.
以上説明したように本発明は、絶縁膜上に形成された浅
い溝を埋めて金属配線を形成し、金属配線と絶縁膜との
密着性を高めることにより、改良された樹脂材料を用い
ることなく耐温度サイクル性の向上した半導体装置が得
られる効果がある。INDUSTRIAL APPLICABILITY As described above, the present invention fills the shallow groove formed on the insulating film to form the metal wiring, and enhances the adhesion between the metal wiring and the insulating film, without using the improved resin material. There is an effect that a semiconductor device with improved temperature cycle resistance can be obtained.
第１図（ａ），（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ′線断面図、第２図（ａ），（ｂ）は本発明
の第２の実施例の平面図及びＢ−Ｂ′線断面図、第３図
は従来の半導体装置の一例の断面図である。 １……シリコン基板、２……活性層、３……酸化シリコ
ン膜、４……金属配線、4A……接触部、５……開孔部、
６……パッシベーション膜、7,7A……溝。1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are the second embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional semiconductor device, and FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. 1 ... Silicon substrate, 2 ... Active layer, 3 ... Silicon oxide film, 4 ... Metal wiring, 4A ... Contact part, 5 ... Open hole part,
6 ... passivation film, 7,7A ... groove.
Claims (1)
活性層上に設けられた絶縁膜と、該絶縁膜上に設けられ
かつ絶縁膜に設けられた開孔部を通して前記活性層に接
続する金属配線とを有する半導体装置において、前記金
属配線は、この金属配線の幅又は長さ方向でかつ所定の
幅及び所定の深さで前記絶縁膜に設けられた断面形状が
Ｕ字形でかつストライプ状の浅い溝上に形成されている
事を特徴とする半導体装置。1. An active layer provided on the surface of a semiconductor substrate, an insulating film provided on the active layer, and an opening provided on the insulating film and provided in the insulating film to the active layer. In a semiconductor device having a metal wiring to be connected, the metal wiring has a U-shaped cross section provided in the width or length direction of the metal wiring and having a predetermined width and predetermined depth. A semiconductor device characterized by being formed on a stripe-shaped shallow groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030023A JPH0789551B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030023A JPH0789551B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62188246A JPS62188246A (en) | 1987-08-17 |
| JPH0789551B2 true JPH0789551B2 (en) | 1995-09-27 |
Family
ID=12292233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61030023A Expired - Fee Related JPH0789551B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0789551B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1153991B (en) * | 1980-10-29 | 1987-01-21 | Rca Corp | METHOD TO CREATE A DIELECTRIC METALLIZATION STRUCTURE |
| JPS60180144A (en) * | 1984-02-27 | 1985-09-13 | Nec Kansai Ltd | Manufacture of semiconductor element |
-
1986
- 1986-02-13 JP JP61030023A patent/JPH0789551B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62188246A (en) | 1987-08-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |