JPH0789653B2 - Horizontal sync signal processing circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to noise removal and horizontal sync signal loss (dropout) from a composite sync signal including a horizontal sync signal component such as a television signal. The present invention relates to a horizontal synchronizing signal processing circuit for compensation.

(Structure of Conventional Example and Problems Thereof) Conventionally, a horizontal sync signal processing circuit for removing noise from a composite sync signal such as a television signal and compensating for loss (dropout) of the horizontal sync signal is a multivibrator. Many of them are composed of analog circuits such as and differentiators.

However, if the horizontal synchronizing signal processing circuit is to be configured by a semiconductor integrated circuit, a relatively large capacity capacitor becomes an essential component, and thus it is not suitable for semiconductor integration of the horizontal synchronizing signal processing circuit.

(Object of the Invention) It is an object of the present invention to provide a horizontal synchronizing signal processing circuit which can be integrated into a semiconductor by removing noise and compensating dropout by a digital circuit, thereby eliminating the need for a capacitor. It is what

(Structure of the Invention) According to the present invention, when a composite sync signal including a horizontal sync signal component is input, noise having a cycle shorter than a predetermined basic clock cycle is removed from the horizontal sync signal component, and the horizontal sync signal component rises. A noise removal / falling edge detection circuit that outputs a falling edge pulse when a falling portion is detected, and a signal that is generated at the timing of one cycle of the horizontal synchronization signal generation signal output by the control circuit and the horizontal synchronization signal component output by itself. Is received as a reset signal, and 1 of the horizontal sync signal component
A first counter that outputs a pulse slightly before the cycle, a timing of one cycle of the horizontal synchronization signal component, and a timing slightly after one cycle of the horizontal synchronization signal component, and noise removal / falling edge When the detection circuit and the first counter output a signal, the horizontal synchronization signal component 1
A first logic gate group for extracting a falling edge pulse existing in the determination period, with a period from a timing slightly earlier than the period to a timing slightly later than one period of the horizontal synchronization signal component as a determination period. And 1 of the falling edge pulse and the horizontal sync signal component existing outside the discrimination period.
The normal mode switching is performed when the second logic gate group that extracts a pulse at a timing slightly after the cycle and the first logic gate group continuously output the falling edge pulse within the determination period a certain number of times or more. A pulse is output, and either the falling edge pulse other than the discrimination period or the pulse at a timing slightly after one cycle of the horizontal synchronizing signal component is continuously output from the second logic gate group a certain number of times or more. And a second counter that outputs an abnormal mode switching pulse,
A third logic gate group that outputs a normal mode signal when the normal mode switching pulse is output from the second counter and outputs an abnormal mode signal when the abnormal mode switching pulse is output from the second counter; , A falling edge pulse is output from the first logic gate group while the normal mode signal is output from the third logic gate group, or
While the abnormal gate mode signal is being output from the second logic gate group, the second logic gate group outputs a falling edge pulse or a pulse at a timing slightly later than one cycle of the horizontal synchronizing signal component, A fourth logic gate group that outputs a reset signal to the second counter, and a falling edge pulse or horizontal synchronization signal from the second logic gate group while the normal mode signal is being output from the third logic gate group. A pulse with a timing slightly later than one cycle of the component is output, or a falling edge pulse is output from the first logic gate group while the abnormal mode signal is output from the third logic gate group. When the normal mode signal is output from the fifth logic gate group that outputs a count signal to the second counter and the third logic gate group when the normal mode signal is output, A sixth falling edge pulse that is present is used as a horizontal synchronizing signal generation signal, and a falling edge pulse that is present when the abnormal mode signal is being output from the third logic gate group is output as a horizontal synchronizing signal generation signal. A horizontal synchronizing signal generation signal is output from the control circuit including a group of logic gates, or the first counter outputs a pulse at a timing slightly later than one cycle of the horizontal synchronizing signal component. Then, a horizontal synchronizing signal generating circuit for outputting a pulse having a constant width as a horizontal synchronizing signal is provided.

(Description of Embodiments) FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. 1 is an input terminal, 2 is a noise removing circuit, 3 is a falling edge detection circuit, and 4 is a falling edge. A pulse supply line, 5 is a control circuit, 6 is a counter, 7 is a horizontal synchronizing signal generating circuit, and 8 is a horizontal synchronizing signal output terminal.

First, the outline of the operation of the present embodiment configured as described above will be described.

When the composite sync signal is input to the noise removal circuit 2 via the input terminal 1, the noise removal circuit 2 removes part of the noise included in the composite sync signal and then removes part of the noise. Is output to the falling edge detection circuit 3.

When the falling edge detection circuit 3 detects the falling portion of the composite synchronizing signal input from the noise removal circuit 2, it outputs a falling edge pulse to the control circuit 5 via the falling edge pulse supply line 4 [third See FIG. (B)].

The control circuit 5 measures the position of the falling edge pulse and detects the horizontal sync signal component of the composite sync signal to remove noise and compensate dropout of the horizontal sync signal all at once. It consists of a counter reset signal output via line 9, a falling edge pulse in abnormal mode output via signal line 10, and a falling edge pulse in normal mode output via signal line 11. A horizontal control circuit that outputs a counter control signal to the counter 6 and also outputs a falling edge pulse in a non-normal mode output via the signal line 10 and a falling edge pulse in a normal mode output via the signal line 11. The sync signal generation signal is output to the horizontal sync signal generation circuit 7.

The counter 6 is controlled by the counter control signal input from the control circuit 5, and outputs 0.95H pulse via the signal line 12 (where H is the period of the horizontal synchronizing signal,
(Hereinafter referred to as “H”) is output via the signal line 13 1.05
A timing signal composed of an H pulse and a 1H pulse output via the signal line 14 is output to the control circuit 5, and a timing signal composed of a 1.05H pulse output via the signal line 13 is output to the horizontal synchronization signal generation circuit 7. Output to.

Further, the horizontal synchronizing signal generating circuit 7 is
When the horizontal synchronizing signal generation signal is input from the counter and the timing signal is input from the counter 6, the horizontal synchronizing signal of a constant cycle is output from the horizontal synchronizing signal output terminal 8.

FIG. 2 shows a concrete example of a circuit having the functions of the noise removing circuit 2 and the falling edge detecting circuit 3 according to one embodiment of the present invention. In FIG. 2, the same reference numerals as those in FIG. The parts indicate the same part, 15 is a clock pulse input terminal for inputting a clock pulse of a frequency sufficiently higher than the composite synchronizing signal, for example, several MHz, 16, 17, 18 and 19 are D
Flip-flop 20 is an AND circuit.

FIG. 3 is a timing chart of the circuit shown in FIG.
FIG. 3A shows the waveform of the composite synchronizing signal, and the inverted signal of the composite synchronizing signal is input to the input terminal 1.
3B shows the waveform of the falling edge pulse output from the falling edge detection circuit 3 to the falling edge pulse supply line 4.

The operation of the circuit shown in FIG. 2 will be described below.

The four D flip-flops 16, 17, 18 and 19 are connected in series with each other and in parallel with the AND circuit 20. For this reason, four D flip-flops 16, 17, 18 and 19
When four signals are sequentially input from the input terminal 1, all of the D flip-flops 16, 17, 18 and 19 output signals, and the AND circuit 20 outputs four D flip-flops 16,
If the "H" level signal is input from all of 17, 18, and 19, the "H" level signal is input to the falling edge pulse supply line 4,
That is, the falling edge pulse is output. By the way, the input terminal of the AND circuit 20 is connected to the terminals of the D flip-flops 16 and 17 and the Q terminals of the D flip-flops 18 and 19. Therefore, four D flip-flops 16,1
If "L", "L", "H", and "H" signals are input to 7, 18 and 19, respectively, all of the D flip-flops 16, 17, 18 and 19 output "H" level signals. , AND circuit 20 outputs a falling edge pulse.

Clogged, a clock pulse as shown in FIG. 7 (a) is input from the clock pulse input terminal 15, and a signal as shown in FIG. 7 (b), that is, a period of four cycles (T _{1 to} T) of the clock pulse. a period of two cycles of the start of the _{3) (T 2 ~T 3)} "H"
The inverted signal of the composite synchronizing signal which becomes the level and becomes the "L" level during the next two cycle periods (T _{1 to} T ₂ ) is input from the input terminal 1 and is output from the D flip-flops 16, 17, 18 and 19. When all the signals output to the AND circuit 20 become “H” level, the AND circuit 20 recognizes that the falling part of the horizontal synchronizing signal has been detected, and changes the falling edge pulse to the falling edge pulse. Output to the supply line 4.

Here, a normal horizontal synchronizing signal component (a) and a noise signal component (b) less than two periods in the clock pulse period
And a composite sync signal as shown in FIG. 3 (a) including a noise signal component (c) of two or more periods in the clock pulse period and a loss (dropout) signal component (d) as shown by a broken line. Is input to the input terminal 1.

When the horizontal sync signal component (a) of the composite sync signal is input to the input terminal 1, the AND circuit 20 detects the falling portion of the horizontal sync signal component (a) of the composite sync signal, as described above. As shown in FIG. 3B, a normal falling edge pulse is output to the falling edge pulse supply line 4.

Further, when the noise signal component (b) of the composite synchronizing signal having a cycle of less than 2 in the cycle of the clock pulse is input to the input terminal 1, the four D flip-flops 16, 17, 18
Since the signals of "L", "L", "H", and "H" are not input to 19 and 19, respectively, the AND circuit 20 does not detect the falling part of the noise signal component (b) of the composite synchronization signal as the falling part. , The falling edge pulse is not output to the falling edge pulse supply line 4, as shown in FIG. That is, the noise signal component (b) of the composite sync signal having a cycle of less than 2 in the cycle of the clock pulse is removed by the circuit shown in FIG.

Further, when the noise signal component (c) of the composite synchronizing signal having a cycle of two or more cycles in the cycle of the clock pulse is input to the input terminal 1, the four D flip-flops 16, 17, 18
Since the signals of “L”, “L”, “H”, and “H” are input to 19 and 19, respectively, the AND circuit 20 detects the falling portion of the noise signal component (C) of the horizontal synchronization signal, and As shown in FIG. 3B, the falling edge pulse is output to the falling edge pulse supply line 4. That is, the noise signal component (C) of the composite sync signal having a cycle of two or more cycles in the cycle of the clock pulse is not removed by the circuit shown in FIG.

Further, when the missing signal component (d) of the composite synchronizing signal having a period of one or more periods in the period of the horizontal synchronizing signal is input to the input terminal 1, the four D flip-flops 16, 17, 18 and 19 are respectively set to "L". Since "L", "H", and "H" signals are not input, the AND circuit 20 causes the missing signal component (d) of the composite sync signal that should originally exist at the portion indicated by the broken line in FIG. 3 (a).
The falling edge pulse (e) as shown by the broken line in FIG. 3 (b) is not output to the falling edge pulse supply line 4.

That is, the circuit shown in FIG. 2 detects the trailing edge of the composite sync signal from which the noise signal component (b) of the composite sync signal having a cycle of less than two cycles has been removed.

FIG. 4 shows a specific example of the control circuit 5 according to one embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 1 denote the same parts.

21 and 34 are RS flip-flops, 22,23,25,26,28,29,
32, 33, 35 and 36 are AND circuits, 24, 27, 30 and 37 are OR circuits, 3
1 is a 4-bit counter.

When the falling edge pulse is input from the falling edge detection circuit 3 through the falling edge pulse supply line 4, the control circuit 5 configured as described above outputs the falling edge pulse as a horizontal synchronization signal component (a). It is determined whether there is a noise signal component (c), a reset signal for resetting the counter 6 is output, and the falling signal component (d) falls based on the output signal of the counter 6. After the edge pulse loss compensation is performed, the horizontal synchronization signal generation signal is output to the horizontal synchronization signal generation circuit 7.

Next, the operation of the control circuit 5 will be specifically described.

The counter 6 is provided at the set terminal of the RS flip-flop 21.
Signal line 12 from is connected to 0.
95H pulse is input as a set signal. The signal line 13 from the counter 6 is connected to the reset terminal of the RS flip-flop 21, and the 1.05H pulse from the counter 6 is input as a reset signal.

By the way, in the present embodiment, the 0.95H pulse as the set signal, the 1.05H pulse as the reset signal, as described later, occurs in the periodic variation in the composite synchronization signal, the position of the 1H pulse is the original 1H position. In consideration of the case where there is a slight deviation from before and after, within a period of ± 0.05H of 1H of the composite sync signal, that is, within a period of 0.95 to 1.05H (hereinafter referred to as "within the discrimination period").
By discriminating the pulse input to the horizontal sync signal component (a) as the falling edge pulse, the rise of the composite sync signal existing near the original 1H pulse position of the composite sync signal as shown in FIG. Extract the falling edge pulse to 0.95
This is because the falling edge pulse (N) of the composite synchronizing signal existing at a position deviating from the period of 1.05H (hereinafter referred to as "outside the discrimination period") is determined as noise and removed.

The AND circuit 22 outputs a signal when the falling edge pulse from the falling edge pulse supply line 4 and the output signal from the Q terminal of the RS flip-flop 21 are input, in other words, to the RS flip-flop 21. Set signal input 0.
Within the discrimination period from 95H to 1.05H when the reset signal is input, only the falling edge pulse of the horizontal synchronizing signal component (a) input from the falling edge pulse supply line 4 is separated and output.

The AND circuit 23 outputs a signal when the falling edge pulse from the falling edge pulse supply line 4 and the output signal from the terminal of the RS flip-flop 21 are input, in other words, falling edge outside the discrimination period. Only the falling edge pulse of the noise signal component (C) input from the pulse supply line 4 is separated and output.

By the way, when the missing signal component (d) of the composite synchronizing signal as shown in FIG. 3 (a) is input to the input terminal 1, the falling edge pulse of the horizontal synchronizing signal component (a) or the noise signal component (c) is generated. Is not output to the falling edge pulse supply line 4, the outputs of the AND circuits 22 and 23 are "L".
Hold on to the level. Therefore, as will be described later, the counting operation of the counter 6 advances,
The RS flip-flop 21 is held in the set state until a pulse is output. In other words, the counter 6 is 1.05
Since the H pulse is output, the missing signal component (d) in which the composite sync signal and the noise are superimposed is input to the input terminal 1, and the horizontal sync signal component (ii) or noise is input within the determination period of the composite sync signal. This is only when the falling edge pulse of the signal component (C) is not output to the falling edge pulse supply line 4.

For this reason, the OR circuit 24 whose input terminals are connected to the output terminal of the AND circuit 23 and the signal line 13 from the counter 6 respectively.
Is input when the falling edge pulse of the noise signal component (C) separated and output by the AND circuit 23 or the 1.05H pulse output from the counter 6, that is, the falling edge pulse of the missing signal component (D) is input. Outputs H "level signal.

The RS flip-flop 34 is for judging whether or not the horizontal synchronizing signal processing circuit of the present invention is synchronized with the composite synchronizing signal, and the falling edge pulse input to the falling edge pulse supply line 4 is composited. When synchronized with the sync signal (hereinafter referred to as "normal mode"), the output of the Q terminal is "H".
Level, the output of the terminal becomes "L" level, and the falling edge pulse of the falling edge pulse supply line 4 is asynchronous with the composite synchronization signal (hereinafter referred to as "abnormal mode"),
The output of the Q terminal becomes "L" level and the output of the terminal becomes "H" level.

Therefore, the criteria for distinguishing between the “normal mode” and the “abnormal mode” will be described.

When a signal is output from the AND circuit 22 and the RS flip-flop 34, the AND circuit 25 outputs the falling edge pulse existing within the determination period in the normal mode.

When a signal is output from the OR circuit 24 and the terminal of the RS flip-flop 34, the AND circuit 26 generates a falling edge pulse existing outside the determination period in the abnormal mode or a falling edge pulse within the determination period. It outputs a 1.05H pulse indicating that it does not exist.

That is, the AND circuit 25 outputs if there is a falling edge pulse synchronized with the composite synchronizing signal in the normal mode, and the AND circuit 2
6 outputs if there is a falling edge pulse (noise) that is not synchronized with the composite sync signal in abnormal mode.

The OR circuit 27 outputs one of the falling edge pulses when the falling edge pulse is output from the AND circuit 25 or the AND circuit 26. In other words, the OR circuit 27 outputs the falling edge pulse of one of the falling edge pulses. These falling edge pulses are extracted when there is an edge pulse (a synchronized pulse) and when there is a falling edge pulse (a pulse which is not synchronized) suitable for this mode in the abnormal mode.

The AND circuit 28 is the Q of the OR circuit 24 and the RS flip-flop 34.
When a signal is output from the terminal, in the normal mode, a falling edge pulse existing outside the determination period or a 1.05H pulse indicating that there is no falling edge pulse within the determination period is output.

When a signal is output from the AND circuit 22 and the terminal of the RS flip-flop 34, the AND circuit 29 outputs the falling edge pulse existing within the determination period in the abnormal mode.

That is, the AND circuit 28 outputs if there is a falling edge pulse (noise) that is not synchronized in the normal mode, and the AND circuit 29
Outputs if there is a falling edge pulse synchronized in the abnormal mode.

The OR circuit 30 outputs one of the falling edge pulses when the AND circuit 28 or the AND circuit 29 outputs the falling edge pulse. In other words, the OR circuit 30 does not match the falling edge pulse in the normal mode. These falling edge pulses are extracted when there is an edge pulse (a pulse that is not synchronized) and when there is a falling edge pulse (a synchronized pulse) that does not match this mode in the abnormal mode.

The 4-bit counter 31 counts the number of falling edge pulses output from the OR circuit 30, and when eight falling edge pulses are continuously input from the OR circuit 30 to the clock terminal (CLK), the output is “ When the falling edge pulse is input from the OR circuit 27 to the reset terminal (R), it is reset and the output becomes the "L" level.

More specifically, if there is a falling edge pulse that does not match the current mode, the output signal of the OR circuit 30 goes to the “H” level each time, so the 4-bit counter
31 counts the number of falling edge pulses output from the OR circuit 30, that is, the number of falling edge pulses that do not match the mode, and when 8 consecutive falling edge pulses are input, Outputs a signal for mode switching.

For example, when there is a falling edge pulse that is not synchronized with the composite synchronizing signal in the normal mode, the “H” level signal output from the OR circuit 30 is input to the clock terminal (CLK) of the 4-bit counter 31, The bit counter 31 counts as "1". And the 4-bit counter 31
However, when such a counting operation is continuously performed eight times and overflows, the output signal of the 4-bit counter 31 becomes "H" level.

The clogged 4-bit counter 31 counts the output signal of the OR circuit 30 eight times in succession, which means that only eight falling edge pulses that are not synchronized with the composite synchronization signal are input even in the normal mode. Therefore, the signal for switching to the abnormal mode is output from the 4-bit counter 31.

On the contrary, even when eight falling edge pulses synchronized with the composite sync signal are continuously input in the abnormal mode, the 4-bit counter 31 similarly outputs a signal for switching to the normal mode.

If a falling edge pulse that is synchronized with the composite sync signal is input in the normal mode, or if a falling edge pulse that is not synchronized with the composite sync signal is input in the abnormal mode, the signal that matches the current mode is output. Since it is being input, there is no need to switch modes. At this time, the "H" level signal output from the OR circuit 27 is input to the reset terminal R of the 4-bit counter 31 to stop the counting operation of the 4-bit counter 31 and maintain the current mode.

These operations will be specifically described with reference to FIG.

When the output signal of the Q terminal of the RS flip-flop 34 is at the "H" level, that is, in the normal mode, the 4-bit counter 31 counts the falling edge pulse or 1.05H pulse outside the discrimination period, and rises within the discrimination period. It is reset by the falling edge pulse.

When the 4-bit counter 31 continuously detects eight falling edge pulses or the like outside the determination period, the output signal of the 4-bit counter 31 becomes "H" level, and two signals input to the AND circuit 33 are output. To "H" level, the RS flip-flop 34 is reset. As a result, the output signal of the Q terminal of the RS flip-flop 34 becomes "L" level,
The output signal of the pin becomes "H" level.

That is, in the normal mode, the RS flip-flop 34 is
It is reset when the horizontal synchronizing signal processing circuit does not synchronize with the composite synchronizing signal.

In the abnormal mode, the 4-bit counter 31 counts the falling edge pulse within the discrimination period and is reset by the falling edge pulse outside the discrimination period.

When the 4-bit counter 31 continuously detects eight falling edge pulses within the determination period, the 4-bit counter 31
Since the output signal of 31 goes to "H" level and the two signals input to the AND circuit 32 go to "H" level, RS flip
Flop 34 is set. As a result, the output signal of the Q terminal of the RS flip-flop 34 becomes "H" level and the output signal of the terminal becomes "L" level.

That is, the RS flip-flop 34 in the abnormal mode
Is set when the horizontal synchronizing signal processing circuit synchronizes with the composite synchronizing signal.

Next, operations of the AND circuits 35 and 36 and the OR circuit 37 will be described.

The output signals of the AND circuits 35 and 36 and the output signal of the OR circuit 37 are used as the reset signal of the counter 6 and the horizontal synchronization signal generation signal of the horizontal synchronization signal generation circuit 7, respectively.

The AND circuit 35 separates the falling edge pulse in the abnormal mode and outputs it to the signal line 10, and the AND circuit 36 separates the falling edge pulse in the determination period in the normal mode and outputs the signal line. Output to 11.

The OR circuit 37 uses the falling edge pulse in the abnormal mode, the falling edge pulse in the determination period in the normal mode, and the 1H pulse output from the counter 6 as the reset signal of the counter 6 as a signal line. Output to 9.

By the way, since the signal line 10 and the signal line 11 are connected to the OR circuit 42 (see FIG. 6) of the horizontal synchronizing signal generating circuit 7,
When the AND circuit 35 and the AND circuit 36 detect the falling edge in the abnormal mode in the horizontal synchronizing signal generation signal, or when the falling edge pulse within the determination period in the normal mode is detected, the horizontal synchronization is performed. The horizontal synchronizing signal generating signal is output to the signal generating circuit 7.

Thus, when the falling edge pulse within the discrimination period is input from the falling edge detection circuit 3, the control circuit 5 outputs a reset signal to the counter 6 via the signal line 9, and the counter 6 outputs 0.95H. Pulse, 1.05H pulse or 1
When the H pulse is output, the falling edge pulse is judged, and either the normal mode or the abnormal mode is set, and then the horizontal sync signal generation signal is sent through the signal lines 10 and 11 to the horizontal sync signal generation circuit. Output to 7.

FIG. 5 shows a concrete example of the counter 6 according to one embodiment of the present invention. In FIG. 5, the portions having the same reference numerals as those in FIG. 1 show the same portions, and 38 is a 0.95H pulse. And 1H counter that counts 1H pulse, 39 is an OR circuit, 40 is an RS flip-flop, and 41 is a 0.5H counter that counts 1H pulse to 1.05H pulse.

By the way, to count 1.05H, 1H counter 38 and 0.0
Even when counting up to 1.05H, the 5H counter 41 is used to output a reset signal at the time of 1H, and to make the counting start point of the next 1 cycle accurate 1H of the next cycle. Because you have to start counting.
That is, it is necessary to count 1.05H and 1H in parallel.

Further, the period of the horizontal synchronizing signal component of the composite synchronizing signal is usually 1H, but when there is fluctuation in the period, the horizontal synchronizing signal component is output before the horizontal synchronizing signal component of the composite synchronizing signal is separated. This is because the output cycle of the horizontal synchronizing signal needs to be larger than the maximum cycle.

Therefore, the horizontal synchronizing signal processing circuit of the present invention sets the allowable variation range of the period of the horizontal synchronizing signal component of the composite synchronizing signal to 0.95 to 1.
05H

Next, the operation of the counter 6 thus configured will be described.

The output terminal of the OR circuit 37 is connected to the reset terminal R of the 1H counter 38 via the signal line 9. Therefore, the 1H counter 38 is reset by the falling edge pulse existing in the determination period in the normal mode, reset by the falling edge pulse existing in the entire range in the abnormal mode, and further in the normal mode or the abnormal mode. At any time, it is reset by the 1H pulse output from the 1H counter 38 itself.

When the 1H pulse output from the 1H counter 38 is input to the RS flip-flop 40 as a reset signal, the RS flip-flop 40 is reset and the 0.05H counter 41
Since the reset state of is released, the 0.05H counter 41 starts counting. And 0.05H counter 41 is 0.05H
When the counter 6 counts 1.05H, in other words, the 0.05H counter 41 sends a 1.05H pulse to the signal line.
At the same time as outputting to 13, the RS flip-flop 40 is set via the OR circuit 39, so the 0.05H counter 41 itself is reset.

Further, the 0.05H counter 41 uses the OR circuit 39 from the signal lines 10 and 11.
It is also reset by a signal input via. That is, the 0.05H counter 41 is also reset by the falling edge pulse existing in the determination period in the normal mode and the falling edge pulse existing in the entire range in the abnormal mode.

As a result, there is no deviation in the generation of the missing signal component (d) of the composite sync signal and the horizontal sync signal output from the horizontal sync signal output terminal 8 as shown by the broken line in FIG.
You will be able to compensate for dropouts.

FIG. 6 shows a specific example of the horizontal synchronizing signal generating circuit 7 according to one embodiment of the present invention. In FIG. 6, the same reference numerals as those in FIG. 1 denote the same parts, and 42 Is OR
The circuit, 43RS flip-flop, 44 is a 0.05H counter that generates a 0.05H wide horizontal sync signal.

The OR circuit 42 receives an RS flip signal every time a horizontal synchronizing signal generation signal is input from the control circuit 5 via the signal lines 10 and 11 or a 1.05H pulse is input from the counter 6 via the signal line 13. The flop 43 is reset and the 0.05H counter 44 is operated.

When the 0.05H counter 44 counts the 0.05H pulse, the RS
Flip-flop 43 is set, 0.05H counter 4
4 reset itself. As a result, a horizontal synchronizing signal of 0.05H width is output from the horizontal synchronizing signal output terminal 8.

The 0.05H counter 44 outputs the horizontal sync signal
In the normal mode, the counter 6 outputs the 1.05H signal when the falling edge of the 0.95-1.05H composite sync signal corresponding to the 1H cycle horizontal sync signal component is detected and when the horizontal sync signal component is lost due to dropout. Is output, and the falling edge is detected in the entire range in the abnormal mode.

In the abnormal mode, the horizontal sync signal is generated based on all falling edges, not limited to the range, so that it is possible to accurately determine which signal is correct and which is noise in a non-synchronized state. This is because it cannot be determined, and it is better that noise is superimposed rather than the original horizontal synchronization signal component is removed.

As described above, in the normal mode in which the composite sync signal is synchronized with the horizontal sync signal processing circuit of the present invention, the horizontal sync signal is not generated by the falling edge pulse of the composite sync signal outside the determination period, and noise is removed. You can Even if the composite sync signal has a missing signal component, the first horizontal sync signal is
With 1.05H cycle, the second and subsequent horizontal sync signals can be compensated with 1H cycle.

(Effect of the Invention) As described above, according to the present invention, there is an effect that a horizontal synchronizing signal can be detected from a composite synchronizing signal by digital processing.

In addition, since noise can be removed, there is no malfunction, and
There is an effect that the horizontal synchronizing signal can be compensated for the missing signal component.

Further, since it can be configured by a digital circuit, there is an effect that a capacitor is unnecessary and it is suitable for semiconductor integration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, and FIG. 2 is a specific example of a circuit having the functions of a noise removal circuit and a falling edge detection circuit of an embodiment of the present invention. Three
2A and 2B are timing charts of the circuit shown in FIG. 2, FIG. 4 is a concrete example of a control circuit of an embodiment of the present invention, and FIG. 5 is a counter of an embodiment of the present invention. A specific example, FIG. 6 is a specific example of the horizontal synchronizing signal generating circuit according to one embodiment of the present invention, FIG. 7 (a) is a waveform diagram of a clock pulse input to a clock pulse input terminal, and FIG. 7 (b) is Waveform diagram of the inverted signal of the horizontal synchronizing signal input to the input terminal, 8th
The figure is a conceptual diagram when removing a noise signal component of a falling edge pulse outside the range of 0.95 to 1.05H. 1 ... Input terminal, 2 ... Noise elimination circuit, 3 ... Falling edge detection circuit, 4 ... Falling edge pulse supply line, 5
...... Control circuit, 6 ... Counter, 7 ... Horizontal sync signal generation circuit, 8 ... Horizontal sync signal output terminal, 9,10,1
1,12,13,14 …… Signal line, 15 …… Clock pulse input terminal, 16,17,18,19 …… D flip-flop, 20 …… 4
Input AND circuit, 21,34,40,43 …… RS flip-flop,
22,23,25,26,28,29,32,33,35,36 …… 2 input AND circuit, 2
4,27,30 …… 2-input OR circuit, 31 …… 4-bit counter, 3
7,39,42 …… 3 input OR circuit, 38 …… 1H counter, 41,44…
… 0.05H counter.

Claims (1)

[Claims] 1. When a composite synchronizing signal including a horizontal synchronizing signal component is input, noise of a period shorter than a predetermined basic clock period is removed from the horizontal synchronizing signal component, and the falling portion of the horizontal synchronizing signal component is removed. When a noise is detected, a noise removal / falling edge detection circuit that outputs a falling edge pulse, a horizontal synchronization signal generation signal output by the control circuit, and a signal generated at the timing of one cycle of the horizontal synchronization signal component output by itself. At a timing slightly earlier than one cycle of the horizontal synchronizing signal component, at a timing of one cycle of the horizontal synchronizing signal component, and at a timing slightly after one cycle of the horizontal synchronizing signal component. A first counter that outputs a pulse, the noise removal / falling edge detection circuit, and the first counter output signals The falling period existing in the discrimination period is defined as a period from a timing slightly earlier than one cycle of the horizontal synchronization signal component to a timing slightly later than one cycle of the horizontal synchronization signal component as a discrimination period. A first logic gate group for extracting edge pulses,
From the first logic gate group, a second logic gate group for extracting a pulse at a timing slightly later than one cycle of the falling edge pulse and the horizontal synchronization signal component existing outside the discrimination period. When the falling edge pulse within the determination period is continuously output a certain number of times or more, a normal mode switching pulse is output, and the falling edge pulse other than the determination period or the horizontal synchronization is output from the second logic gate group. A second counter that outputs an abnormal mode switching pulse when any of the pulses at timings slightly later than one cycle of the signal component are continuously output a certain number of times or more, and the normal counter is output from the second counter. A normal mode signal is output when the mode switching pulse is output, and an abnormal mode signal is output when the abnormal mode switching pulse is output from the second counter. A third logic gate group for outputting and the falling edge pulse is output from the first logic gate group while the normal mode signal is output from the third logic gate group, or While the abnormal mode signal is being output from the third logic gate group, a timing slightly later than one cycle of the falling edge pulse or the horizontal synchronizing signal component is output from the second logic gate group. When a pulse is output, a fourth logic gate group that outputs a reset signal to the second counter and the second logic gate while the normal mode signal is output from the third logic gate group The gate group outputs the falling edge pulse or a pulse with a timing slightly later than one cycle of the horizontal synchronizing signal component, or
When the falling edge pulse is output from the first logic gate group while the abnormal mode signal is output from the third logic gate group, a count signal is output to the second counter. In a state where the normal mode signal is being output from the fifth logic gate group and the third logic gate group, the falling edge pulse existing within the determination period is used as a horizontal synchronization signal generation signal, A control circuit including a sixth logic gate group that outputs the falling edge pulse existing as a horizontal synchronizing signal generation signal, which exists when the abnormal mode signal is being output from the logic gate group, The horizontal synchronization signal generation signal is output, or the timing is slightly delayed from the first counter after one cycle of the horizontal synchronization signal component. And a horizontal synchronizing signal generating circuit for outputting a pulse having a constant width as a horizontal synchronizing signal when the horizontal synchronizing signal is output.