JPH0789660B2 - Display device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a display device using a liquid crystal display panel or the like.

[Prior Art and Problems Thereof] In recent years, a liquid crystal display panel has been generally used for a display unit of a small portable television receiver. In this type of liquid crystal television receiver, for example, a small liquid crystal display panel of 160 × 210 dots, when sampling a video signal, sampling is performed twice every three times in the vertical direction. I'm doing it and thinning out 1/3 of the data. In the NTSC standard system, the effective video signal period is 480H in the vertical direction (H is one horizontal scanning period)
Therefore, half of that, 240H, is the entire vertical video period. However, in the prior art, 1/3 of the data is thinned out as described above, and therefore sufficient resolution cannot be obtained.

Further, in the PAL system, the number of scanning lines is 625, but when the number of scanning electrodes is small, data is thinned out as in the case of the NTSC system, so that sufficient resolution can be obtained. Can not.

Further, a method of displaying the data of two scanning lines on one scanning electrode of the liquid crystal display panel is also considered,
In this method, the number of scanning electrodes is half the number of scanning lines of the video signal.
However, it is not possible to deal with various numbers of scanning electrodes as described above.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a display device capable of obtaining a sufficient resolution regardless of the number of scanning electrodes.

[Means for Solving the Problem] In the present invention, in a display device in which scanning electrodes and signal electrodes are arranged in a matrix, scanning with a time width of a plurality of H (H is one horizontal scanning period) with reference to a vertical synchronization signal Scanning-side data generating means for generating side data, and the generated scanning-side data are alternately delayed at first and second time intervals set according to the number of horizontal scanning lines and the number of scanning electrodes, and sequentially determined. The scan electrode drive signal and the signal electrode drive signal are provided with a unit for generating scan electrode drive signals that overlap in time, and a unit for generating a signal electrode drive signal by sampling a video signal corresponding to a horizontal synchronizing signal. It is characterized in that it is driven based on.

[Operation] Therefore, irrespective of the number of scan electrodes of the display device, it is possible to sample the video signals of all effective scan lines and display them on the scan electrodes of the display device.

[First Embodiment of the Invention] A first embodiment of the present invention will be described below with reference to the drawings. First, a case where the present invention is applied to an NTSC television receiver will be described. FIG. 1 shows a schematic configuration of a display driving portion in a liquid crystal television receiver. In the figure, 1 is a display control unit, which is a scan electrode drive circuit.
Scanning side data SR and data shift clock φN2 in 2a and 2b
And the chip selection signals CE1 to CE3 and the data latch clock φN1 together with the video signal to the signal electrode drive circuits 3a to 3c. Then, the scan electrode driving circuits 2a and 2b and the signal electrode driving circuits 3a to 3c drive the liquid crystal display panel 4 of a simple matrix of 160 × 210 dots, for example.
In this case, the scan electrode drive circuits 2a and 2b drive the scan electrodes of the liquid crystal display panel 4 by dividing them into X1 to X80 and X81 to X160,
The signal electrode drive circuits 3a to 3c drive the signal electrodes of the liquid crystal display panel 4 by dividing them into Y1 to Y80, Y81 to Y160, and Y161 to Y210.

Next, details of each of the above parts will be described. FIG. 2 shows the details of the main part of the display control unit 1. The display control unit 1 includes a horizontal sync signal φ from a sync separation circuit (not shown).
H and the vertical synchronizing signal φV are given. The vertical sync signal φV is input to the vertical sync detection circuit 10, and the horizontal sync signal φH is sent to the basic clock generator A.

The horizontal synchronizing signal φ supplied to the basic clock generating section A
H is V.V. via the transfer detector 11 and the low pass filter 12.
It is input to CO (voltage controlled oscillator) 13. And this
The output signal of the VCO 13 is input to the clock terminal CK of the oscillator 14 and its oscillation frequency is controlled. The oscillator 14 generates, for example, a pulse signal of 8.056 MHz, and its oscillation output is divided by a 1/2 divider circuit 15 and output as clock pulses φ1 and φ2 having different phases of 4.028 MHz.
These clock pulses φ1 and φ2 are basic clocks,
It becomes a horizontal sampling clock.

Further, the output signal of the 1/2 frequency dividing circuit 15 is frequency divided by the 1/256 frequency dividing circuit 16 into a signal PH having the same frequency (15.734 kHz) as the horizontal synchronizing signal φH as shown in FIG. Sent to vessel 11. From the 1/256 divider 16 above, the signal PH
Timing signals φH1 and φH2 with the same frequency but different phases
Is output.

On the other hand, the vertical sync detection circuit 10 detects the vertical sync signal φV and outputs the vertical sampling position determination signal CS shown in FIG. The vertical sampling position determination signal CS becomes “0” (significant signal) in the effective video period 240H,
It is held at "1" level in other periods.

Then, the output signal CS of the vertical synchronization detecting circuit 10 is sent to the scanning side data generating section B. The vertical sampling position determination signal CS supplied to the scanning side data generator B
Is input to the input terminal I of the flip-flop 18 via the latch circuit 17. The flip-flop 18 reads the input signal in synchronization with the clock pulse φ2 and supplies it to the input terminal 1 of the flip-flop 19. This flip flop
Reference numeral 19 includes clock terminals CX and CY, which reads an input by a timing signal given to the clock terminal CY via the NOR circuit 20 and outputs a signal by a clock pulse φ2 given to the CY terminal.

The NOR circuit 20 receives the data shift clock φN2 and the clock pulse φ1 via the inverter 21. The output signal of the NOR circuit 20 is input to the flip-flop 19, the reset terminal of the latch circuit 17, and the clock terminals CX of the flip-flops 22 and 23. The output signal of the flip-flop 19 is input to the input terminal I of the flip-flop 22 and the AND circuit 24.

The flip-flop 22 reads the input signal in synchronization with the timing signal input to the clock terminal CX, and outputs the signal in synchronization with the clock pulse φ2 input to the clock terminal CY. The output signal of this flip-flop 22 is
Input terminal I of flip-flop 23 via AND circuit 24
Entered in. The flip-flop 23 reads the input signal in synchronization with the timing signal input to the clock terminal and outputs the clock pulse φ2 input to the clock terminal CY.
The signal is output in synchronization with. The output signal of the flip-flop 23 is sent to the scan electrode drive circuit 2a as the scan side data SR. That is, as shown in FIG. 3, the scanning side data generator B outputs the scanning side data SR having a time width of 3H in synchronization with the data shift clock φN2 when the vertical sampling position determination signal CS is given. .

Further, the vertical sampling position determination signal CS output from the vertical synchronization detection circuit 10 is sent to the φN1 and φN2 generating section C. It is sent to the φN1 and φN2 generating section C. This φN1, φN2
The vertical sampling position determination signal CS given to the generator C is input to the reset terminal R of the 2-bit counter 26 via the OR circuit 25. The counter 26 counts up according to the timing signal φH1, inputs the signal output from the output terminal X1 to the flip-flop 27, and inputs the signal output from the output terminal X2 to the flip-flop 28.

This flip-flop 28 receives the input signal at timing φH2.
It is read in synchronization with and output to the OR circuit 25. Further, the flip-flop 27 reads the input signal in synchronization with the timing signal φH1, and inputs the input terminal 1 of the flip-flop 29 and an exclusive NOR circuit (hereinafter abbreviated as EX NOR circuit).
Output to 30. The flip-flop 29 reads the input signal in response to the clock pulse φ1 and outputs the clock pulse φ2.
Output in synchronization with. And this flip-flop 29
And the output signal of the flip-flop 27 are output as the data shift clock φN2 via the EX NOR circuit 30. Further, the timing signal φH1 is output as the data latch clock φN1 via the inverter 31.

That is, the φN1 and φN2 generating section C configured as described above
As shown in FIG. 3, when the vertical sampling position determination signal CS is applied, the reset state of the 2-bit counter 26 is released during that period to start counting the timing signal φH1. Then, the counter 26 displays the timing signal φH1
When 2 times are counted and the output of the output terminal X2 becomes "1",
The "1" signal is read by the flip-flop 28 in synchronization with the timing signal φH2, and the output resets the counter 26. As a result, the output of the output terminal X2 of the counter 26 becomes “0” again, and this “0” signal becomes the timing signal φ.
The counter is read by the flip-flop 28 in synchronization with H2.
26 reset is released.

The same operation is repeated thereafter, and the counter 26 is reset every time the timing signal φH1 is counted twice. Therefore, when the data shift clock φN2 output from the EX NOR circuit 30 outputs two pulse signals synchronized with the timing signal φH1 as shown in FIG. 3, the next pulse output is prohibited. Therefore, the data shift clock φN2 is one obtained by removing one out of every three timing signals φH1.

Further, the vertical sampling position determination signal CS output from the vertical synchronization detection circuit 10 is a chip selection signal creation circuit.
Sent to 32. This chip selection signal generation circuit 32 is provided with a signal CS from the vertical synchronization detection circuit 10 and clock pulses φ1, φ.
Based on 2, the chip selection signals CE1 and CE2 having a time width of 80 bits and the chip selection signal CE3 having a time width of 50 bits are generated as shown in FIG.

FIG. 4 shows the configuration of the scan electrode drive circuit 2a.
In the figure, reference numeral 41 is a shift register, and the scanning side data SR from the display control unit 1 is set to the first bit of this shift register 41
Is entered. The shift register 41 reads the scan side data SR in synchronization with the data shift clock φN2 and sequentially shifts the data. Then, each bit output of the shift register 41 is passed through the level shifters 42a, 42b, ... To the multiplexers 43a, 43b,
It is input to ... The scanning electrodes X1, X2, ... Of the liquid crystal display panel 4 are sequentially driven by the multiplexers 43a, 43b ,.

Then, the output signal of the final bit of the shift register 41 is sent to the shift register in the scan electrode driving circuit 2b as the scan side data SR.
Be transferred as. This scan electrode drive circuit 2b has the same configuration as the scan electrode drive circuit 2a, and the scan electrode drive circuit 2a
Data transferred from the data shift clock φN2
Shifts in synchronism with and generate drive signals for the scan electrodes X81 to X160.

FIG. 5 shows a detailed configuration of the signal electrode drive circuits 3a to 3c. In the figure, reference numeral 51 denotes an AND circuit. The AND circuit 51 receives a clock pulse φ1 and
One of the chip selection signals CE1 to CE3 is given to the invert terminal. The output of the AND circuit 51 is sent as a shift clock to the shift register 52 having a 3-bit structure at each stage. The shift register 52 reads the 3-bit video signal sent from the display control unit 1 in synchronization with the output signal of the AND circuit 51 and sequentially shifts it, and outputs the output signal of each stage to the latch circuit 53. To do. This latch circuit 53 is
The output of each stage of the shift register 52 is latched in synchronization with the data latch clock φN1 and output to the brightness modulation circuit 54.

The brightness modulation circuit 54 creates a brightness modulation signal according to the video signal latched in each stage in the latch circuit 53 in units of 3 bits, and a multiplexer is provided via level shifters 55a, 55b ,.
Output to 56a, 56b, ... The multiplexers 56a, 56b, ...
The signal electrodes Y1, Y2, ... Of the liquid crystal display panel 4 are driven according to the brightness modulation signals sent via the level shifters 55a, 55b ,.

Next, the overall operation of the above embodiment will be described with reference to the third timing chart. The display control unit 1 generates the various timing signals shown in FIG. 3 as described in FIG. 2, scan electrode drive circuits 2a and 2b, and signal electrode drive circuit 3a.
Output to ~ 3c.

The scan electrode drive circuit 2a shown in FIG. 4 uses the data shift clock φ for the scan side data SR sent from the display controller 1.
The data is read into the shift register 41 in synchronization with N2 and sequentially shifted.

The data to be shifted in the shift register 41 is passed through the level shifters 42a, 42b, ...
, and the drive signals are output from the multiplexers 43a, 43b ,. In this case, the data shift clock φN2 is 3 with respect to the timing signal φH1.
Since one shot is removed from each shot, the scan side data SR read in the shift register 41 is alternately shifted at intervals of 1H and 2H.

Therefore, the drive signals of the scan electrodes X1, X2, ... Output from the multiplexers 43a, 43b, ... Have a time width of 3H as shown in FIG. 3, and are alternately shifted at intervals of 1H and 2H. Signal, and 160 shifts are performed during 240H.

On the other hand, in the signal electrode drive circuits 3a to 3b, the chip selection signals CE1 to CE3 sent from the display controller 1 are sequentially selected. The signal electrode drive circuits 3a to 3c selected by the chip selection signals CE1 to CE3 take in the video signal sent from the display control unit 1 to the shift register 52 in synchronization with the clock pulse φ1 and set it as the data latch clock φN1. The data is latched in the latch circuit 53 in synchronization. In this case, the data latch clock φN1 is always output in the same cycle in synchronization with the timing signal φH1.

Therefore, the video signal read in the shift register 52 is always transferred to the latch circuit 53 and further sent to the brightness modulation circuit 54. The brightness modulation circuit 54 performs brightness modulation according to the video signal latched by the latch circuit 53. Then, the signal whose brightness is modulated by the brightness modulation circuit 54 is level-shifted 55
sent to multiplexers 56a, 56b, ... via a, 55b ,.
The signal electrodes Y1, Y2, ... Of the liquid crystal display panel 4 are driven for display by the multiplexers 56a, 56b ,. As described above, all video signals are sampled in the vertical direction and displayed on the liquid crystal display panel 4.

[Second Embodiment of the Invention] Next, an example in which the present invention is applied to a PAL system television receiver will be described. This embodiment shows a case where the number of scanning electrodes of the liquid crystal display panel is 120. As shown in the timing charts of FIGS. 6 and 7, scanning side data having a time width of 5H is created and scanned. It is given to the electrode driving circuit, and the scanning side data is alternately shifted at intervals of 2H and 3H in this scanning electrode driving circuit to create a scanning electrode driving signal, and the video signal is sampled every time in correspondence with the horizontal synchronizing signal. Then, the signal electrode drive signal is generated.

That is, in this embodiment, as shown in FIG. 6, the chip selection signal CE is generated corresponding to each horizontal period of the video signal, and the data latch clock φN1 is generated in synchronization with the horizontal synchronizing signal. Then, the data shift clock φN2
Is one in two for the data latch clock φN1,
Alternately output once every three shots. That is, the data shift clock φN2 is alternately output at intervals of 2H and 3H, and the generation means thereof will be described in detail later.

Further, as shown in FIG. 7, the drive signals of the one scanning electrodes X1, X2, ... Set the time width to 5H and are sequentially shifted in synchronization with the data shift clock φN2. As a result,
The drive signals for the scan electrodes X1, X2, ... Are signals having a time width of 5H and being alternately shifted in the time widths of 2H and 3H. As described above, by setting the time width of the drive signal of the scan electrodes X1, X2, ... And the shift time width thereof, the video signal can be sampled every time and can correspond to 120 scan electrodes. That is, all the video signals for 5H can be sampled and displayed while one scan electrode is selected for 5H, and high resolution can be obtained.

Therefore, the data shift clock φN2 can be generated by the circuit shown in FIG. In FIG. 8, 61 is a timing signal generation circuit, which is a horizontal synchronization signal φH.
The chip select signal CE and the data latch clock φN1 are generated in synchronism with. Reference numeral 62 denotes a quinary counter which counts up in response to the horizontal synchronizing signal φH and outputs 3-bit count data from the output terminals A, B and C according to the count value.

The signal output from the output terminal A of the quinary counter 62 is input to the AND circuits 63 and 64, and the signal output from the output terminal B is input to the AND circuits 63 and 64 via the inverter 65. The signal output from the output terminal C of the quinary counter 62 is input to the AND circuit 63, and the output signal becomes the reset signal of the quinary counter 62. Further, the signal output from the output terminal C of the quinary cowter 62 is input to the NOR circuit 66 together with the output signal of the AND circuit 64.
The output signal D of the NOR circuit 66 is input to the OR circuit 67 together with the data latch clock φN1 output from the timing signal generating circuit 61, and its output becomes the data shift clock φN2.

In the above configuration, the timing signal generating circuit 61 outputs the data latch clock φN1 (low level) after a certain time delay when the horizontal synchronizing signal φH is input as shown in FIG.

On the other hand, in the quinary counter 62, in the initial state, that is, in the reset state, the signals output from the terminals A, B, and C are at a low level as shown in FIG. 9, and as a result, the OR circuit 67
Output signal D of is at a high level. Therefore, even if the data latch clock φN1 is output from the timing signal generating circuit 61 in this state, the output level of the OR circuit 67 does not change and the data shift clock φN2 is not output.

When the quinary counter 62 is counted up to "1" by the horizontal synchronizing signal φH, the output signal of the terminal A changes to high level and the output of the NOR circuit 66 changes from high level to low level. In this state, the timing signal generation circuit 61
When the data latch clock φN1 (low level) is output from, the data latch clock φN1 is output from the OR circuit 67 as the data shift clock φN2 (low level).

Next, the quinary counter 62 is counted up by the horizontal synchronizing signal φH, but when the count value is "2" and "3", the output of the terminal B is held at a high level,
The output of the inverter 65 goes low and the AND circuit 64
Is prohibited and the output D of the NOR circuit 66 is held at the high level. Therefore, even if the timing signal generating circuit 61 outputs the data latch clock φN1 to the OR circuit 67 in this state, the output of the OR circuit 67 is held at the high level and the data shift clock φN2 is not output.

When the quinary counter 62 is counted up to "4" by the next horizontal synchronizing signal φH, the output of the output terminal C becomes high level and the output D of the NOR circuit 66 becomes low level. Therefore, in this state, the timing signal generation circuit
When the data latch clock φN1 is output from 61, it is output from the OR circuit 67 as the data shift clock φN2.

After that, when the quinary counter 62 is counted up to "5" by the horizontal synchronizing signal φH, the output of the AND circuit 63 becomes high level and the quinary counter 62 is immediately reset. As a result, the signals output from the terminals A, B, and C of the quinary counter 62 are all at the low level, that is, the initial state is restored.

Hereinafter, the above-described operation is repeated to create the data shift clock φN2 which is alternately output at intervals of 2H and 3H.
Then, by the data shift clock φN2, the above-described shift operation of the scan electrode drive signal is performed.

As described above in detail, according to the present invention, scanning side data for generating scanning side data having a time width of a plurality of H (H is one horizontal scanning period) with reference to a vertical synchronization signal is generated, The scanning side data is alternately delayed at first and second time intervals set according to the number of horizontal scanning lines and the number of scanning electrodes to generate scanning electrode drive signals which sequentially overlap for a predetermined time, and at the same time, a video signal is generated. Since the signal electrode drive signal is sampled in response to the horizontal sync signal, the video signals of all effective scanning lines are sampled regardless of the number of scan electrodes of the display device, and the scan electrode of the display device is sampled. It is possible to obtain a display device for displaying on.

[Brief description of drawings]

1 to 5 show a first embodiment of the present invention. FIG. 1 is a block diagram showing a schematic configuration of the entire liquid crystal display device, and FIG. 2 is a block diagram showing details of a display control unit. FIG. 3 is a timing chart for explaining the operation, and FIG.
FIG. 6 is a block diagram showing details of the scan electrode driving circuit, FIG. 5 is a block diagram showing details of the signal electrode driving circuit, and FIGS. 6 to 9 show a second embodiment of the present invention. FIG. 7 and FIG. 7 are timing charts for explaining the operation, FIG. 8 is a diagram showing the configuration of the timing signal generation circuit,
FIG. 9 is a timing chart for explaining the operation of generating the data shift clock φN2 in the timing signal generating circuit. 1 ... Display control unit, 2a, 2b ... Scan electrode driving circuit, 3a to 3
b ... Signal electrode drive circuit, 4 ... Liquid crystal display panel, 10 ...
... Vertical sync detection circuit, A ... Basic clock generator, B ...
… Scan side data generator, C… φN1, φN2… Generator, 41
...... Shift register, 42a, 42b ...... Level shifter, 43a, 4
3b …… Multiplexer, 52 …… Shift register, 53 ……
Latch circuit, 54 ... Luminance modulation circuit, 55a, 55b ... Level shifter, 56a, 56b ... Multiplexer, 61 ... Timing signal generating circuit, 62 ... Quintary counter.

Claims (1)

[Claims] 1. A display device in which scan electrodes and signal electrodes are arranged in a matrix, and scan side data for creating scan side data with a time width of a plurality of H (H is one horizontal scan period) with reference to a vertical synchronization signal. Generating means and a scanning electrode drive signal which alternately delays the generated scanning side data at first and second time intervals set according to the number of horizontal scanning lines and the number of scanning electrodes and sequentially overlaps for a predetermined time. And a means for generating a signal electrode drive signal by sampling the video signal corresponding to the horizontal synchronizing signal, and driving based on the scan electrode drive signal and the signal electrode drive signal. Characteristic display device.