JPH0792982B2 - PCM data generation circuit and reproduction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording / reproducing or transmitting / receiving a PCM signal, and particularly to a PCM data generation circuit for performing multi-mode setting by switching a recording rate and a transmission rate. And a reproducing circuit.

[Conventional technology]

An example of a device for recording or reproducing a PCM audio signal on a magnetic tape is a digital audio tape recorder (DAT). S-DA using a fixed head for DAT
There are T and R-DAT using a rotating head. For the R-DAT standard, refer to "Digital Audio Tape Recorder System" of the DAT conference; issued by the Japan Electronics Manufacturers' Association 19
June 1987 (The DAT Conference; DIGITAL AUDIO TAPEREC
ORDER SYSTEM; c / o Electronic Industries Associati
on of Japan (June 1987). here,
The sampling frequency of PCM audio in DAT is basically 48 kHz, and in addition to the 48k mode, there are 44k mode with a sampling frequency of 44.1kHz and 32k mode with a sampling frequency of 32kHz. The frame format of the recording signal is also based on the 48k mode, and the other 44k mode and 32k mode follow the 48k mode. When comparing the 48k mode and the 32k mode, although the 32k mode has a smaller amount of information than the 48k mode, the data area in the 48k mode is filled with the data in the 32k mode, so an empty area is generated. . The data area of the frame format is 0-data addresses.
There are up to 1455, and the data address is 0 to 143 in 48k mode.
Uses up to 9 efficiently. However, in the 32k mode, the data address is used only from 0 to 959. (Page 47 of the above-mentioned document) Comparing by redundancy, 48k mode is 37.5%, while 32k mode is 58.3%.

In the DAT, the same 48 kHz sampling 2-channel 16-bit linear recording and 16-12 companding non-linear recording were not specified for different modes of information.

[Problems to be Solved by the Invention]

In the above-mentioned conventional technique, since the signal format for recording is common even in the modes having different amounts of information, there is a problem that redundancy is increased in the mode having small amounts of information.

An object of the present invention is to optimize the redundancy at the time of recording (at the time of transmission) and reduce the recording rate (transmission rate) while keeping the signal format common depending on the mode.

Another object of the present invention is to provide a signal format that is free from error propagation in a compressed signal format at the time of recording (transmission).

[Means for Solving the Problems]

The first sample data of n bits 1 word is 1 bit m
A first symbol data generating circuit for dividing the first sample data into n pieces of 1-word second sample data; and a second bit of the second sample data for 1 bit. When dividing into m pieces of symbol data, it is divided into symbol data containing only sample data and symbol data containing only fixed data.
The above object is achieved by providing the symbol generating circuit, the common signal processing circuit, and the data deleting circuit for deleting the fixed data symbol in the data frame generated by the signal processing circuit.

[Action]

Basically, the uncompressed sample data is converted to symbol data for signal processing, and a data frame is generated by signal processing such as interleaving and error correction code addition. The signal processing circuit can be shared by adding the fixed data so that the number of bits is the same as that of the data and then generating the symbol data. Then, by deleting the added fixed data after the signal processing, the recording or transmission rate can be lowered.

Further, by adding fixed data in symbol units, it is possible to eliminate error propagation between symbols even when group code modulation is performed in symbol units.

〔Example〕

Examples of the present invention will be described below. FIG. 1 is a block diagram showing the basic circuit of the present invention. 1 is a data input terminal, 2 is a digital compression circuit, 3 is a data addition circuit, 4 is a switch, 5a is a first symbol generation circuit, 5b is a second symbol generation circuit, 6 is a signal processing circuit, and 7 is data deletion. Circuit, 8
Is a switch, 9 is a mode control circuit, 52 is a modulation circuit, and 10 is a data output terminal.

The operation of the circuit will be described below. This circuit converts analog signals such as voice into digital signals and generates PCM signals for recording on magnetic tape. The generated PCM signal is a data frame A corresponding to mode A and a mode B.
In the switch 4 and the switch 8, the data frame A is generated when the side a is selected, and the data frame B is generated when the side b is selected. The mode A in which the switch 4 and the switch 8 are selected on the side a will be described. The data input to the data input terminal 1 is sample data in which one word is 16 bits in which analog voice is sampled at a sampling frequency F _S (for example, 48 kHz). This sample data is input to the symbol data generation circuit 5. The symbol data generation circuit 5a converts 16-bit sample data into 8-bit unit symbol data. That is, 1 sample data is 2
It becomes symbol data. This symbol data is input to the signal processing circuit 6 via the switch 4. The signal processing circuit 6 performs distributed (interleave) processing on the input symbol data, generates an error correction code from the data, and adds the error correction code. Next, a data frame is formed by adding a synchronization signal and a control signal (identification data of data content, etc.). The generated data frame is output as a mode A data frame A from the output terminal 10 and guided to the recording circuit. The symbol data generation method in the symbol data generation circuit 5a will be described with reference to the schematic diagram of FIG. FIG. 7A shows input 16-bit 1-word sample data. The upper 8 bits and the lower 8 bits are assigned to one symbol, respectively, and the symbol data of (b) is generated. here,
"L" is the left sound data, "R" is the right sound data, numbers are numbers in time series, "u" is the upper bit, and "l" is the lower bit. The 8-bit symbol data is a basic unit of signal processing. The error correction code, the synchronizing signal, etc. generated in the signal processing circuit 6 are all performed in units of 8 bits and 1 symbol. Next, the data frame generated by the signal processing circuit 6 will be described. FIG. 3 is a block diagram showing a data frame. 11 is a data frame (entire), 12
Is a header, 13 is symbol data corresponding to even-numbered data in the time-series order of the sample data, and 14 is symbol data corresponding to odd-numbered data. 15
Is the C2 outer code, and 16 is the C1 inner code. In the drawings, "S" is a unit that means a symbol. In the drawing, "B" is a unit that means a block. Blocks consisting of 48 symbols in the vertical direction are arranged 102 blocks in the horizontal direction to form one data frame. The relationship between the C1 inner code and the C2 outer code of the interleave and error correction code is a so-called cross-completion type that is completed within the data frame. As the error correction code, for example, Reed Solomon code is applied. The method of generating the C2 outer code 15 uses 32 symbols of symbol data as information, and generates a code of 6 symbols. The code structure is RS (38,32,7). The C1 inner code generation method uses a total of 38 symbols of 32 symbols of symbol data and 6 symbols of C2 outer code as information to generate a code of 4 symbols. The code structure is RS (42,38,5). Or, if the block address 1 symbol in the header is added to the information, the code structure of the C1 internal code is RS (43,39,5)
Is. Here, the internal structure of the block will be described in detail. FIG. 4 is a block diagram showing a block. Reference numeral 17 is a block (whole), 18 is a sync signal indicating the beginning of the block, 19 is an identification signal indicating the contents of voice, 20 is a block address indicating the order of the blocks, 21 is an identification signal 19 and a block address 20.
This is a parity signal that checks the error (during reproduction) of. 22 is the symbol data in the block, 23 is the C2 outer code, 24
Is the inner code of C1. The symbol data consists of 32 symbols, and the block consists of 46 symbols in total.

Mode A data frame generated by the signal processing circuit 6
11 is output from the data output terminal 10 in the order of block 0, block 1, ..., Block 101.

Here, the arrangement of the symbol data in the data frame will be described in detail. FIG. 5 is a data layout diagram for explaining a part of the data frame. As described above, the even-numbered data are alternately arranged on the left side and the odd-numbered data are arranged on the right side, and the upper symbol data and the lower symbol data are arranged in pairs. C1 code generation is vertical (in block)
To do. The C2 outer code is in the diagonal direction, for example, L ₀ u, L ₆ l, R ₁₂
Generate u, L ₁₈ l, and so on. Here, the interleaving for generating the C2 outer code is completed in one data frame when it is performed in the room of 3B, 3B, 2B, 3B, 3B, 2B, ... .

The data output from the switch 8 is sent to the modulation circuit 52 on a symbol-by-symbol basis, and the modulation circuit 52 performs 8-10 modulation for converting, for example, 8 bits into a 10-bit code. This is also convenient because processing can be performed in symbol units.

Next, the operation when the mode B is set will be described.
Mode B is provided to lower the recording rate than mode A.

In the circuit block diagram of FIG. 1, the sample data input to the data input terminal 1 is input to the symbol data generation circuit 5b via the digital compression circuit 2 and the data addition circuit 3. The symbol data output from the symbol data generation circuit 5b through the switch 4 is processed by the signal processing circuit 6 as in the mode A. The output is sent to the data output terminal 10 via the data deleting circuit, the switch 8 and the modulating circuit 52. The operation of the digital compression circuit 2 is to convert 16-bit sample data into 12-bit sample data, and this method makes good use of the characteristics of voice and hardly deteriorates the sound quality.

Next, the operations of the digital compression circuit 2, the data addition circuit 3 and the symbol data generation circuit 5b will be described with reference to FIG. (A) is sample data in which the input 16 bits are 1 word. The sample data is digitally compressed into 12-bit data, which is the data shown in (b). The compressed data is subjected to data recombination and fixed data addition processing in the data addition circuit 3.
As shown in FIG. 7C, the lower 4 bits of the data of the R channel are left as they are, and the lower 4 bits of the data of the R channel move between the data of the L channel and the upper 8 bits of the R channel.
Then, fixed data (for example, "0" is 8 bits) is added after the upper 8 bits of the R channel. This data string (c)
Is the same number of bits as in (a). Subsequently, in the symbol data generation circuit 5b, the data string (c) is converted into symbol data in units of 8 bits. The obtained data string (d) is input to the signal processing circuit 6 as in the mode A. The overall configuration diagram of the data frame B generated in the signal processing circuit 6 is the same as the data frame 11 in FIG.
However, the internal data arrangement is as shown in FIG. Comparing this data layout diagram with the data layout diagram of FIG.
It can be seen that fixed data of "0" is added in symbol units. Fixed data is used as a symbol unit
This is to eliminate error propagation that occurs between symbol data during recording / reproduction when group code modulation is performed on a symbol-by-symbol basis independently of other data. FIG. 8 shows one block of the data frame of this embodiment. (A) is a block corresponding to mode A, and (b) is a block corresponding to mode B. (C) is a block when fixed data is deleted in mode B. Fixed data can be easily deleted on a symbol-by-symbol basis.

Next, an example of a circuit that actually performs symbol generation in mode B will be described. FIG. 9 is a circuit example in which the data addition circuit 3 and the symbol generation circuit 5b are put together. FIG. 10 shows a time chart for explaining the operation of FIG. Digitally compressed 12-bit sample data Sφ is
Input to the digital input terminal 25 and
It is latched by the clock CK1 shown in FIG. 10 and divided into the signal S1u of the higher 8 bits and the lower 4 bits. The lower 4 bits are re-latched with the same clock CK1 in the latch 27 to become the signal S2l. This signal S2l and a signal that does not latch, that is, the lower 4 bit signal S1 of the next sample data generates an 8 bit symbol. To do. The signal S2c, in which the lower 4 bits are each 2 bits and 8 bits, and the fixed data (in this case, "0") are switched by using the switch signal SW1.
When the switch is performed at 8, a fixed data is obtained, and a signal S3 is obtained in which 8 bits of data including the lower 4 bits of each R channel are alternated. By switching the signal S3 and the signal S1u with the switch signal SW2 in the switch 29, it is possible to obtain the signal S4 in the same arrangement as in (d) of FIG. In addition, the signal S4 at the latch 30,
The effect of the circuit delay, which is good for latching with the clock CK2, is eliminated and the signal is inputted from the output terminal 31 to the signal processing circuit 6 in the same manner as in the A mode.

Here, the switch 29 sends the switch signal to the SW of FIG.
When the phase is reversed as in 2 ', the data is fixed like the signal S4' and the position of the lower data of the R channel can be changed. In this way, the signal processing circuit can be shared by generating the same number of symbols in mode B as in mode A in a pair of L and R channel sample data, and the recording or transmission rate in mode B can be increased. Can be lowered. Further, by separating the fixed data into symbol units and generating a code, it is possible to eliminate error propagation during reproduction even when group code modulation (for example, 8-10 modulation) is used as a modulation method.

Next, a circuit example in which the symbol generation circuit is commonly used in the modes A and B will be described. FIG. 11 shows that the symbol generation circuits 5a and 5b are shared between the mode A and the mode B. The input terminal 25a is an input terminal in mode A that is directly connected to the input terminal 1 in FIG.
An input terminal 25b in mode B is connected to the digital compression circuit 2 in FIG. The symbol generation in mode B is exactly the same as the operation of the symbol generation circuit in mode B shown in FIG. FIG. 12 shows a time chart showing the operation of symbol generation in mode A. The input signal Sφ is latched by the latch 83 with the lower 8 bits by the clock CK1 and becomes the signal S1al. The upper 8 bits of the signal S.phi. Are input to the switch 82 together with the signal S1 together with the signal S.phi.au and are switched to generate the 8-bit symbol of mode A. The output of the symbol data of the mode A of the switch 82 and the output of the symbol data of the mode B of the switch 29 are selected by the switch 80 controlled by the mode control circuit and are latched by the latch 30 and output from the output terminal 31. The signal is output and input to the signal processing circuit 6.

Next, FIG. 13 shows an example of a circuit in which the symbol generation circuits 5a and 5b of mode A and mode B are shared and the bus line is shared in mode A and mode B. In the circuit example of FIG. 9 as well, the symbol generation in mode B is exactly the same as that of FIG. FIG. 14 shows a time chart showing the operation in the mode A.

Next, a PCM data reproducing circuit for reproducing the original signal from the magnetic tape on which the signal generated by the PCM data generating circuit of the present invention is recorded will be described. FIG. 15 is a block diagram showing an embodiment of the above PCM data reproducing circuit. 40 is a data input terminal, 61 is a demodulation circuit, 41 is a data addition circuit, 42 and 47 are switches, 43 is a signal processing circuit, 44a is a symbol data synthesis circuit in mode A, 44b is a symbol data synthesis circuit in mode B, 45 Is a data deletion circuit, 46 is a digital expansion circuit, 49 is a mode control circuit, and 48 is a data output terminal. This circuit basically operates in reverse to the operation of the PCM data generation circuit shown in FIG. In mode A, the switches 42 and 43 are connected to the a side, and in mode B, they are connected to the b side. The input data is demodulated by the demodulation circuit 61, and in mode A, the input data (data frame A) is input to the signal processing circuit 43 and subjected to deinterleave processing, error correction processing, etc. Data is reproduced. This symbol data is converted into 16-bit sample data in the symbol data synthesis circuit 44a. The sample data is output from the data output terminal 48 via the switch 47. In mode B, the input data (data frame B) is added with the fixed data deleted on the recording side in the data adding circuit 41. Next, the output data of the data addition circuit 41 is input to the signal processing circuit 43 via the switch 42. In the signal processing circuit 43, the deinterleave processing, the error correction processing, and the like are performed as in the mode A, and the symbol data is reproduced. The symbol data is converted into 16-bit sample data by the symbol data synthesizing circuit. The fixed data included in the sample data is removed from the sample data in the data deletion circuit 45. The output signal of the data deletion circuit 45 is digitally expanded by the digital expansion circuit 46 to obtain 16-bit sample data. The sample data is output from the data output terminal via the switch 47.

Next, an example of a circuit that actually performs symbol data combination and data deletion in mode B will be described. FIG. 16 shows a symbol data synthesis circuit 44b and a data deletion circuit 45.
Is a circuit example in which FIG. 17 is a time chart showing the operation of FIG.

In mode B, the output from the signal processing circuit 43 is arranged like the signal S11 in FIG. 13, that is, L ₁ u, L ₁ lR ₁ l, R ₁ u, “0”, L
_{In the case of 2} u, ..., The signal S11 input to the input terminal 32 is latched by the clock CK11 in the latch 33 and becomes the signal S14u. The signal S11 is latched by the clock CK12 in the latch 34 and becomes the signal S13. For this signal S13, the MSB4 bit is the L channel LSB4 bit, and the LSB4 bit is the R channel L channel.
The switch S4l is composed of SB4 bits, and the switch 35 can be switched to the switch signal SW11 having the same signal as the clock CK12 to obtain the signal S14l. This signal S1
Put the 4l4 bit and the signal S14u8 bit together to make the latch 36
By latching with the clock CK13 at, a 12-bit sample data signal S15 can be obtained. This signal S15 is input from the output terminal 37 to the digital expansion circuit 46.

Next, the arrangement of the outputs from the signal processing circuit 43 is S16 in FIG.
FIG. 18 shows a circuit example in the case where L ₁ u, “0”, R ₁ u, L ₁ lR ₁ l, L ₂ u, “0”, ... The circuit of FIG. 18 can perform symbol combination and data deletion only by adding the latch 38 to FIG. A time chart showing the operation of the circuit example of FIG. 18 is shown in FIG.

In this way, the number of symbols in mode A (4 in the embodiment) generated by the two sample data of the L and R channels is changed to the mode B.
Even in the case where the same number of symbols as those in the mode A are generated, the scale of the symbol synthesizing and data deleting circuit on the reproducing side is arbitrary even if the arrangement of the data of the symbols generated by the two sample data of the L and R channels in the mode B is arbitrary. It can be realized without much difference.

As described above, P generated by the PCM data generation circuit of FIG.
For the CM data, the original signal can be obtained by the PCM data reproducing circuit shown in FIG.

Next, FIG. 20 shows a circuit example in which the symbol data synthesis circuit 44a in mode A, the symbol data synthesis circuit 44b in mode B and the data deletion circuit 45 are shared. The operation in mode B is exactly the same as that in FIG.
As for the operation in mode A, as shown in FIG. 21 for the time chart, the 8-bit symbol data input to the input terminal 32 in FIG. 20 is input by inputting the data latched by the clock CK11 in the latch 84 to the upper 8 bits. Input the symbol data as the lower 8 bits to the latch 81 and click
By latching with CK13, 16-bit sample data can be reproduced. The output terminal 38 is an output terminal in mode A, and the output is output as it is from the output 48 in FIG. The output terminal 37 is an output terminal in mode B and is input to the data expansion circuit 46. FIG. 22 shows the latch of FIG.
In the circuit example in which 84 is replaced with latch 33, an 8-bit latch is 1
Can be omitted. The operation is exactly the same as the circuit example of FIG. When the mode A and mode B bus lines are shared, the latch 81 of FIG. 22 is shared by the latch 36 and the lower bit of the latch 36 is input as shown in the circuit example of FIG. It can be shared by adding a switch 85 controlled by the mode control circuit 49. The operation is not so different from the circuit examples shown in FIGS.

Next, the PCM data generation circuit and the application of the PCM data generation circuit according to the present invention will be described. Fig. 16 shows the invention of 8 mm VTR
3 is a circuit block diagram when used in the PCM voice recording / reproducing circuit of FIG. The 8mm VTR is a PC on the extension of the video track on the tape.
M voice track is provided. This part is used to record or reproduce PCM audio data.
The circuit block diagram of FIG. 16 uses the circuits of FIGS. 1 and 11 and additionally includes a video signal recording / reproducing circuit. Circuits having the same number operate in the same manner. Regarding the newly provided part, 51 is an analog audio input terminal, 51 is an analog digital converter, 52 is a modulation circuit, 53 is a recording amplifier, 54 is a video signal input terminal, 55 is a video signal processing circuit for recording, 56 Is a mode control circuit, 57 is a system controller, 58 is a cylinder having a rotating head, 59 is a magnetic tape, 60 is a reproduction amplifier 61 is a demodulation circuit, 62 is a video signal processing circuit for reproduction, 63 is a video signal output terminal, 64 Is a digital-to-analog converter, and 65 is an analog audio output terminal. Although the operation will not be described in detail, this circuit is for recording / reproducing a video signal and a PCM audio signal by dividing the area on the tape, and is characterized by using the present invention for the recording / reproducing portion of the PCM audio signal. is there. The features of the present invention when used in an 8 mm VTR will be described below.

In PCM voice recording of 8mm VTR, the sampling frequency of voice is 4
When this information is recorded on a tape in stereo with 8 kHz and 16 quantization bits, the number of sample data per track is about 1600 data, and the number of symbols is about 3200 symbols. By the way, since the number of symbol data of the data frame 11 shown in FIG. 3 is 3264 symbols, this is appropriate. And if you try to record this data frame in the PCM data recording area (26.32 °) of 8mm VTR, the linear recording density will be about 104kBPI, which is not a practical level from the viewpoint of tape performance. Therefore, the PCM data recording area is 5
If it is increased to 31.32 °, it will fall to about 87kBIP, and it is at a practical level by using ME tape. However, the current MP tape is not at a practical level. Therefore,
When the sample data quantized with 16 bits is digitally compressed with 12 bits, it corresponds to the mode B described above. In this mode B, the linear recording density is about 72 kBPI, which is close to the practical level for MP tape. Yotsute
Mode A can be associated with ME tape and mode B with MP tape. Further, the PCM data generation circuit of the present invention has the effect that the signal processing circuit is common regardless of the mode, and the system is not so complicated even if the mode is switched. Also, it is advisable to automatically switch the mode by the identification hole of the cassette that distinguishes between ME and MP tapes.

〔The invention's effect〕

According to the present invention, in the mode setting in which the amount of information to be recorded or transmitted is different, the data amount is controlled before and after the signal processing circuit, so that the data arrangement in the data frame can be the same, and the signal between the modes can be changed. You can do the same. Further, after the signal processing, unnecessary information can be deleted to reduce the recording rate or the transmission rate. Further, there is an effect that the basic capabilities of PCM such as interleaving and correction code length are not changed and the circuit is not complicated.

Further, according to the present invention, the amount of information is adjusted before and after the signal processing circuit in units of symbols, which is a basic unit of correction processing and group code modulation, thereby eliminating the propagation of errors occurring during recording and transmission. You can

Further, according to the present invention, in the PCM signal reproducing circuit, a signal can be generated by supplementing the deleted fixed data, and the signal processing circuit at the time of reproduction can be shared between modes.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG.
Figure is a schematic diagram showing symbol data generation. Figure 3 is a block diagram of a data frame. Figure 4 is a block diagram showing a block of data. Figures 5, 7, and 8 are data arrangements in the data frame. 6 and 6 are explanatory diagrams for symbol data generation, FIG. 9 is a circuit diagram of a symbol data generation circuit, FIG. 10 is a timing chart of FIG. 9, and FIGS. 11 and 13 are shared symbols. FIG. 12 is a timing chart of FIG. 11, FIG. 14 is a timing chart of FIG. 13, and FIG. 15 is a circuit block diagram for reproducing the embodiment of FIG. , FIG. 18 is a symbol data synthesizing circuit diagram, FIGS. 17 and 19 are timing charts of symbol data synthesizing circuit, FIG. 20, FIG. 22 and FIG. 23 are common symbol data synthesizing circuit diagram, FIG. Figure is the timing chart of Figure 20, Figure 24 is the application of the present invention. It is a circuit block diagram showing a. 1 ... Data input terminal, 2 ... Digital compression circuit 3 ... Data addition circuit 5a, 5b ... Symbol data generation circuit 6 ... Signal processing circuit, 7 ... Data deletion circuit 9 ... Mode control circuit, 10 ... … Data output terminal 11 …… Data frame 44 …… Symbol data synthesis circuit 46 …… Digital expansion circuit 52 …… Modulation circuit, 53 …… Recording amplifier 58 …… Cylinder, 59 …… Tape 61 …… Demodulation circuit

Claims (8)

[Claims] 1. A PCM signal is processed in 1-bit symbol units, group code modulation is performed in the symbol units, and a PC
In a PCM signal generator for recording or transmitting an M signal, first symbol data for dividing n bit 1-word first sample data input at sampling synchronization T _S into l bit m symbol data A generation circuit, a compression circuit for digitally compressing the first sample data into second sample data of n'bit 1 word, k second sample data of 1 bit h symbol data, (m-
h) a second symbol data generating circuit for generating fixed symbol data of the symbol, and a first switch for selecting the output of the first symbol generating circuit or the output of the second symbol data generating circuit and outputting the symbol data. Circuit,
Using the input symbol data as information, adding signals such as interleave processing, error correction code generation, and synchronization signals,
A signal processing circuit for generating a first data frame; a data deletion circuit for deleting fixed data in the first data frame generated by the signal processing circuit to generate a second data frame; A second switch circuit for selecting the data frame or the second data frame and outputting the data frame, and a mode control circuit for controlling the first and second switch circuits.
PCM data generation circuit. 2. A PCM signal generating device for recording or transmitting a PCM signal, wherein fixed data is added to a first data group having first information and second information obtained by digitally compressing the first information. And a second data group that has the same amount of information as the first information, and selects the first data group or the second data group to interleave the same data and correct the error. The signal processing such as code addition is performed, and the second
A PCM data generation circuit, wherein the fixed data is deleted after the signal processing to reduce the recording rate or the transmission rate when the data group is selected. 3. A second symbol data generation circuit according to claim 1, wherein a first latch for latching the second sample data of n'bits and an output (n 'for the first latches.
-L) A second latch for latching the bit, a signal (l'-l) bit output of the first latch and an output of the second latch are combined into one bit, and A third switch for selecting fixed data, a fourth switch for selecting the output of the third switch, and a fourth switch for selecting the 1-bit output of the first latch, and an output of the fourth switch. A PC characterized by comprising a third latch for latching, and generating 1-bit symbol data and 1-bit fixed symbol data from the second sample data.
Generation circuit for M data. 4. A circuit in which the first symbol data generation circuit and the second symbol data generation circuit according to claim 1 are used in common so as to latch 1 bit out of the n-bit first sample data. Of the second sample data of n'bits, the fifth latch of n'bits, the remaining 1 bit of the first sample data, and the output of 1 bit of the fourth latch. A fifth switch to be selected, a sixth latch for latching the output of the (n'-l) bit of the fifth latch, an output of the (n'-l) bit of the fifth latch and the output of the fifth latch. 6 of the latch (n '
-L) A signal that is obtained by synthesizing the output of the bit into 1 bit and l
A sixth switch for selecting the fixed data of the bit, a seventh switch for selecting the output of the sixth switch and an output of the 1-bit of the fifth latch, and an output of the fifth switch. An eighth switch for selecting the output of the seventh switch by a control signal from the mode control circuit;
The 7th of the 1 bit for latching the output of the 8th switch
Of 1 bit symbol data is generated for the first sample data, and 1 bit symbol data and 1 bit fixed symbol data is generated for the second sample data. A PCM data generation circuit characterized by generating. 5. A method for recording or transmitting a data frame generated by the PCM data generating circuit according to claim 1, and reproducing or receiving the data frame to obtain original sample data. A data adding circuit for adding fixed data to a predetermined location, a fifth switch circuit for selecting output data of the input data frame or the data adding circuit, and a reproduction signal processing circuit for receiving output data of the switch circuit A first symbol data synthesis circuit that synthesizes symbol data to generate sample data; a second symbol data synthesis circuit that synthesizes symbol data to generate compressed sample data; A data deletion circuit for deleting data and an expansion circuit for digitally expanding the compressed sample data output from the data deletion circuit. And a sixth switch circuit for selecting and outputting sample data output from the first symbol data combining circuit output or decompressing circuit output, and a mode control circuit controlled by the ninth and tenth switch circuits. Playback circuit for PCM data. 6. A second symbol data synthesizing circuit and a data deleting circuit according to claim 5, wherein an eighth latch for latching 1-bit symbol data from the reproduction signal processing circuit and the symbol data A ninth latch that latches on a clock different from the eighth latch; an eleventh switch that divides and selects the output of the ninth latch;
The output of the (n'-l) bit of the switch and the output of the l bit of the eighth latch are combined to obtain the second output of the n'bit.
Consisting of the 10th latch that latches the sample data of
A reproduction circuit for PCM data, which reproduces the second sample data of n'bits from the symbol data of 1 bit. 7. A circuit in which a data deleting circuit is shared with the first symbol data synthesizing circuit and the second symbol data synthesizing circuit according to claim 5, latches 1-bit symbol data from the signal processing circuit. Eleventh latch, a twelfth latch that latches the symbol data with a clock different from the eleventh latch, a twelfth switch that divides and selects the output of the twelfth latch, and the eleventh latch. An n'bit for combining and latching the output of the latch and the n-bit for combining and latching the symbol data, the output of the twelfth switch and the output of the eleventh latch. Which consists of the 14th latch of, and from the 1-bit symbol data to the n-bit first sample data,
A reproducing circuit for PCM data, which reproduces the second sample data of n'bits. 8. The PCM data generating circuit according to claim 1 and the PCM data reproducing circuit according to claim 5 are provided with a PCM audio 8 m.
PCM data recording / playback device characterized by being used for mVTR.