JPH0793320B2 - Method for manufacturing field effect transistor - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor using a semi-insulating compound semiconductor substrate.

[Technical background of the invention and its problems]

The Schottky gate field-effect transistor (MESFET) using a semi-insulating GaAs substrate is capable of ultra-high-speed operation not possible with current Si devices due to the high electron mobility of GaAs, due to its high electron mobility. As a basic element of GaAs ICs, it is drawing attention.

In order to improve the performance of this MESFET, it is essential to reduce the series resistance Rs and the gate length. In order to reduce this Rs, in recent years, MESFETs having a structure as shown in FIG. 3 have been generally used. In the figure, 31 is a semi-insulating GaAs substrate, an n-type operating layer 32 is formed on the surface portion thereof, and a gate electrode 33 forming a Schottky junction with this operating layer 32 is formed. The n ⁺ type source / drain regions 34 and 35 are formed in self-alignment with the gate electrode 33 by ion implantation, and the source electrode 36 and the drain electrode 37 are formed on the respective surfaces.
Are formed.

When such a GaAs-MESFET is miniaturized, the distance between the source electrode 36 and the drain electrode 37 becomes narrower, and the effect of applying a high electric field between them and the effect that the source region 34 and the drain region 35 are extremely close to each other combine to form a channel. In addition to the current flowing through the operating layer 32, the current flowing through the substrate 31 increases. In particular, MESFETs that use semi-insulating substrates are
Unlike MOSFETs, etc., the potential barrier between the source / drain regions and the substrate is low, so the above problems associated with the shortening of the channel become prominent. Another problem with the miniaturization of MESFETs is that the electric field distribution inside the operating layer differs from that of long gates. In the case of a long gate, the electric field inside the operating layer is mainly due to the gate voltage, but when the gate length becomes shorter and the ratio of the lateral and vertical dimensions becomes smaller, the electric field inside the operating layer becomes only the gate voltage. Instead, it is also modulated by the drain voltage.

Due to the above two causes, the threshold voltage of MESFET decreases, the drain conductance increases, as the gate becomes shorter,
Further, there is a problem that the mutual conductance is lowered.

In order to suppress the short channel effect due to the change in the electric field distribution, it has been proposed to apply a so-called scaling rule in which the operating layer is thinned and the concentration thereof is increased according to the miniaturization of the gate electrode. However, the operating layer in the GaAs MESFET is generally formed by ion implantation. Especially when trying to obtain a normally-off type FET, even with the most commonly used impurity Si, the acceleration voltage of 50 ~
Low energy injection of about 60 keV is performed. Ion implantation at a lower accelerating voltage is required to make the operating layer thinner, but this is close to the limit of the ion implantation apparatus and has problems in controllability and reproducibility. Another problem is the annealing method for activating the impurities that are thin and are implanted at a high concentration.

On the other hand, it has been reported that the short channel effect can be suppressed by changing the properties of the operating layer of the MESFET in the current path direction (channel direction). As an example, it is assumed that a high transconductance and a low drain conductance can be obtained by embedding a part of the gate electrode in the operation layer by a solid-state reaction by heat treatment and changing the shape of the operation layer and the shape of the gate electrode. There is a report (Showa 58 Spring Society of Applied Physics, 7p-D.3, p-457).

However, in this method, since the gate metal for solid-phase reaction is formed by vapor deposition from an oblique direction, there is a problem in controllability and reproducibility, and the junction area of the gate is increased.
Furthermore, the method of causing the gate metal to dig into the operating layer by a solid-state reaction also has problems in controllability and reproducibility, and causes thermal instability, which requires precise control of the threshold value, and also in many high temperature processes. It is difficult to apply to the manufacturing of integrated circuits that require cost.

[Object of the Invention]

In view of the above points, an object of the present invention is to provide a method for manufacturing a field effect transistor using a semi-insulating compound semiconductor substrate, which solves the problem of characteristic deterioration due to miniaturization.

[Outline of Invention]

A field effect transistor according to the present invention has a structure in which a first conductivity type operation layer is formed on a surface portion of a semi-insulating compound semiconductor substrate and a gate electrode is formed on the surface thereof.
It is characterized in that a second conductivity type layer which is in contact with the operating layer is partially provided at least at the drain side end below the operating layer.

In the method of the present invention for manufacturing such a field effect transistor, an operating layer of the first conductivity type is formed, a gate electrode is formed on the surface thereof, and then ion implantation is performed using this gate electrode as a mask to perform the operating layer. A second conductivity type layer is partially formed on at least a drain side end portion of the lower portion so as to contact the operation layer. The ion implantation step of the high concentration layer of the first conductivity type in the source and drain regions is performed before or after the ion implantation step of forming the second conductivity type layer by using the gate electrode as a mask.

〔The invention's effect〕

In the field effect transistor according to the present invention, the second conductivity type layer is partially formed under the drain side end of the operation layer that determines the pinch-off of the FET. The depletion layer extends under the operating layer due to the junction potential between them. As a result, even if the ion implantation for forming the operating layer is performed with the same acceleration energy as the conventional one, an electrically thinner operating layer can be obtained. Therefore, the electric field distribution at the pinch-off point is maintained as in the case of the long gate structure. The second conductivity type layer is formed only on the drain side end portion that determines the pinch-off or a part of the drain side end portion and the source side end portion, and the other portions are the same as the conventional one because the operation layer is electrically thick. Even at the threshold voltage, the conductance of the channel can be kept higher than before. Furthermore, when the source and drain regions are formed in a self-aligned manner with respect to the gate electrode, since the opposite conductivity type layer exists on the side wall or the periphery of the drain side high concentration layer, the current leaking from the drain region to the substrate is prevented. Can be suppressed.

Further, according to the method of the present invention, excellent MESFET characteristics can be realized by adding only one ion implantation step to the conventional steps. Further, for the ion implantation for forming the second conductivity type layer, the mask used for forming the source and drain regions can be used as it is. When ion implantation from an oblique direction is used to form the second conductivity type layer only on the drain side end, for example, the wafer may be tilted at the time of ion implantation, and this can also be performed easily and with good controllability. it can. Moreover, the ion implantation step of the second conductivity type layer can be performed at an appropriate time before or after the source / drain region forming step.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a GaAs-MESFET of one embodiment. 11 is resistivity 10
^An n-type (first conductivity type) operating layer 12 which is a semi-insulating GaAs substrate of about ⁷ to 10 ⁸ Ω · cm and has a channel region on the surface thereof.
Is formed, and the Schottky gate electrode 13 made of, for example, a WN film of about 4000 Å is formed on the surface thereof. An n ⁺ type source region 15 and a drain region 16 having a higher concentration and a deeper concentration than the operating layer 12 are formed by ion implantation on both sides of the substrate with the gate electrode 13 interposed therebetween. A p-type (second conductivity type) layer 14 is partially formed on the drain side end of the lower portion of the operating layer 12 so as to be in contact with the operating layer. This is the gate electrode
It can be formed by ion implantation from an oblique direction using 13 as a mask. 17 and 18 are ohmic electrodes for the source and drain, respectively.

An embodiment for manufacturing such a MESFET is shown in FIG.
Next, description will be given with reference to (d).

First, Si ions are applied to the semi-insulating GaAs substrate 11 at 50 KeV, 3.0 × 10.
Ions are implanted under the condition of ¹² / cm ² to form the n-type operating layer 12. Next, a WN film of 4000 Å is formed on this substrate, and the well-known photolithography technology and dry etching technology are used.
A Schottky gate electrode 13 having a width of 1.0 μm is formed (FIG. 2 (a)).

After that, Si ion implantation is performed using the gate electrode 13 as a mask. At this time, the ion implantation conditions are, for example, 100 KeV, 1.0 ×
Higher concentration and deeper than the operating layer 12 by selecting 10 ¹⁴ / cm ²
An n ⁺ type source region 15 and a drain region 16 are formed on the gate electrode 13 in a self-aligned manner (FIG. 2 (b)).

Then, with the wafer tilted at an angle of 45 ° with respect to the ion beam, Be is used as a p-type impurity from the direction that becomes the drain of the FET, and the gate electrode 13 is used as a mask under the conditions of 90 KeV and 6.0 × 10 ¹¹ / cm ^2. By doing so, the p-type layer 14 is partially formed at the drain side end of the lower part of the operating layer 12 (FIG. 2 (c)).

After this, anneal for activation of implanted impurities at 800 ° C.
Conducting at ~ 850 ℃, source and drain ohmic electrodes 17 and 18 are formed by AuGe alloy, and self-aligned GaAs
-MESFET is completed (Fig. 2 (d)).

In this embodiment, the ion implantation amount of the operating layer 12 is 3.0 × 1.
Since the concentration is set as high as 0 ¹³ / cm ² , the FET of the conventional structure should be a normally-on type. However, in the present embodiment, the operating layer 12 at the drain side end that determines pinch-off is used.
Since the p-type layer 14 is formed below in contact with the operating layer 12, the lower portion of the operating layer 12 is depleted by the junction potential between the p-type layer 14 and the operating layer 12, and the operating layer is substantially The same effect was obtained as the thickness was reduced, and a normally-off type characteristic was exhibited.
Therefore, the operating layer according to the present embodiment is substantially thinner and has a higher concentration than the operating layer in which the same threshold voltage is obtained in the conventional MESFET in which ions are implanted with the same acceleration energy of 50 KeV. As a result, the electric field distribution on the drain side that determines the pinch-off is similar to that in the case of a long gate. Moreover, the portion of the operating layer other than the drain side region exhibits normally-on type characteristics. Therefore, compared with the conventional MESFET having a uniform operation layer in the current path direction,
The channel conductance becomes large, and when compared with the same gate length, the MESFET of this embodiment has a larger current drive capability.

Further, in the MESFET of this embodiment, since the p-type layer 14 is formed on the drain region side below the operating layer 12, this acts as a potential barrier for electrons, and the current flowing through the substrate can be suppressed. . This effect, combined with the effect that the shape of the electric field described above does not change, makes the MESFET of the present embodiment shift the threshold voltage to the negative side, increase the drain conductance, and the transconductance as compared with the MESFET of the conventional structure. The short-channel effect, such as the decrease in power consumption, was greatly improved.

In addition, the method of the present embodiment requires only a slight increase in the ion implantation step as compared with the method in which the gate metal is vapor-deposited obliquely and the gate metal is diffused into the operating layer by solid phase diffusion to change the operating layer shape. It is extremely simple and has excellent controllability and reproducibility.

In this example, as a method for forming the p-type layer only on the drain side, ion implantation from an oblique direction was used.
It is also possible to obtain the same structure by masking the source side with a photoresist or the like and performing normal vertical ion implantation. Further, the angle when the ion beam is tilted with respect to the wafer is not limited to 45 °, and can be set as necessary depending on how wide the high-concentration layer is formed on the drain side.

The present invention is not limited to the above embodiments, but can be modified in various ways.

For example, in the embodiment shown in FIG. 2, the ion implantation process for forming the source / drain regions and the ion implantation process for forming the p-type layer can be reversed.

Also, various materials and substances can be selected. For example, the gate electrode may be any one that forms a good Schottky barrier with n-type GaAs and retains its characteristics even after heat treatment, such as WN, W, WSi, W-Al, Mo, MoAi. Etc. can be used. As the implanted impurities, in addition to Si in the case of n-type, Se, S or the like can be used, and in the case of p-type, Mg or the like can be used besides Be.

Further, in the embodiments, the case of n-channel has been explained exclusively, but the present invention can be applied to p-channel. In addition to MESFET, the present invention can be similarly applied to the junction type FET.
The present invention can be similarly applied when a semi-insulating compound semiconductor substrate other than aAs is used.

[Brief description of drawings]

FIG. 1 is a diagram showing an MESFET according to an embodiment of the present invention, FIGS. 2 (a) to 2 (d) are diagrams showing a manufacturing process thereof, and FIG. 3 is a diagram showing a conventional MESFET. 11 ... Semi-insulating GaAs substrate, 12 ... N-type operating layer, 13 ... Schottky gate electrode, 14 ... P-type layer, 15 ... N ⁺ type source region, 16 ... N ⁺ type drain region, 17,18 ... Ohmic electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 61-23366 (JP, A) JP 61-152078 (JP, A) JP 61-222176 (JP, A)

Claims (4)

[Claims] 1. A step of forming an operating layer of the first conductivity type on the surface of a semi-insulating compound semiconductor substrate, a step of forming a gate electrode on the surface of the operating layer, and an oblique direction using the gate electrode as a mask. A step of partially forming a second conductivity type layer in contact with the operation layer at the drain side end of the lower part of the operation layer by ion implantation; and ion implantation using the gate electrode as a mask to perform high concentration source of the first conductivity type A method of manufacturing a field effect transistor, comprising: a step of forming a drain region; and a step of forming an ohmic electrode on the surface of the source / drain region. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the second-conductivity-type layer is formed after forming the high-concentration source / drain regions of the first-conductivity type. 3. The first conductive layer is formed after the second conductive type layer is formed.
The method for manufacturing a field effect transistor according to claim 1, wherein the conductive high-concentration source and drain regions are formed. 4. The method for manufacturing a field effect transistor according to claim 1, wherein the semi-insulating compound semiconductor substrate is a GaAs substrate, and the gate electrode forms a Schottky junction with the operating layer.