JPH0793377B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly to a one-transistor dynamic memory.

[Conventional technology]

In the one-transistor type memory, the memory cell is composed of one transfer gate of one capacitor, information is stored depending on the presence or absence of charges accumulated in the capacitor, and for reading, the transfer gate of the selected memory cell is conductive. Therefore, a small signal (usually 100 to 200 mV) is amplified on the data line generated by the transfer of electric charge with the data line by a sense amplifier composed of a differential amplifier. At this time, a reference potential for determining whether the minute signal by the memory cell is "H" or "L" is required on the data line which is paired with the data line where the minute signal by the memory cell appears. Is input to the sense amplifier. Several methods have been used to obtain a desired potential as the reference potential, but one of them is to obtain the reference potential by changing the potential of the dummy word line capacitively coupled to the data line. There was a way. This is composed of only one capacitive element, and has a characteristic that it is simple and suitable for high density. FIG. 4 shows a circuit diagram as a conventional example using this method.
This figure shows the operation waveform diagram. In this conventional example, a so-called 1/2 Vcc precharge system for precharging to an intermediate potential between "H" and "L" on the data line pair generated by the operation of the sense amplifier in the previous cycle will be described. Data line
D, form a pair and are input to a known CMOS type sense amplifier driven by a sense amplifier activation signal SAN and SAP. A plurality of memory cells each composed of one memory cell capacitor C _S and transfer gate Q _C are connected to the data line, and the transfer Q _C is connected to the word line WL1,
Controlled by WL2. Data line precharge signal PDL
The N-type MOS transistor Q _B controlled by is provided between the data line pair D, and Q _P is 1 / with the data line D, respectively.
It is connected between the 2Vcc power line HV. Dummy word line
A capacitive element C _DW is provided between DWL1 and DWL2 and the data line D. Data line pair D, is connected to the I / O bus by the N-type MOS transistor Q _Y which is controlled by a column selection signal YSW. The signal SE in FIG. 5 is a sense amplifier activation trigger signal. When SE rises, the sense amplifier activation signals SAN and SAP shown in FIG. 4 fall,
It goes up and drives the sense amplifier. The dummy word lines DWL1 and DWL2 and the sense amplifier activation signals SAN and SAP are shared by only three data line pairs in FIG. 4, but actually there are 1024 or 4096 pairs. Is.

When the row address stroke ▲ ▼ falls, the row address signal given to the input pin of the memory is fetched (not shown) and the data line precharge signal PDL falls,
Transistors Q _P and Q _B become non-conductive, and data lines D and
Becomes a floating state with the almost intermediate potential as described above. At this time, the word lines WL1 and WL2 are “L” dummy word lines DWL1 and DWL2 are “H” sense amplifier activation signals SAN and SAP.
Are "H" and "L", respectively, and the column selection signal YSW is "L". After that, 1 selected by the row address signal described above
A word line of the book, for example, WL1 rises, charges are transferred between the memory cell capacitor C _S and the data line, and a minute signal appears on the data line. In principle, the 1/2 Vcc precharge method is used as it is as the reference potential because the precharge potential of the data line is an intermediate potential of the potential of the data line potential memory “L” when the memory cell “H” is read. Therefore, it may be directly input to the sense amplifier, but in reality, in many cases, the desired reference potential is preferably a potential slightly lower than the data line precharge potential.
Therefore, the dummy word line DWL1 is lowered and the capacitive element C
By giving an appropriate value of _DW, a desired reference potential can be obtained on the data line D. After that, the sense amplifier activation trigger signal SE rises and the sense amplifier activation signal SA
N and SAP respectively fall and rise, the difference voltage of the data line pair D, is amplified, and, for example, the potential of the data line D becomes the power supply potential and the potential of the data line becomes the ground potential. At this time, the charge in the memory cell capacitor C _S also returns to the state before reading, that is, is refreshed. After that, the column selection signal YS selected by the column address signal (not shown) fetched by the column address stroke ▲ ▼
W1 rises, and the signal of the data line pair D, is transferred to the I / O bus. When the row address stroke ▲ ▼ rises, the column selection signal YSW1 falls, the word line WL1 falls, the sense amplifier activation trigger signal SE falls, the data line precharge signal PDL rises, and the data lines and sense amplifiers are activated. Signal S
AN and SAP are short-circuited (not shown), the sense amplifier is reset, and the data line is precharged to almost the intermediate potential.

Further, as a conventional structure of the dummy word line, a polycrystalline silicon layer or metal wiring formed through an impurity diffusion layer having a conductivity type opposite to that of the substrate formed on the surface of the semiconductor substrate and an insulating film such as a silicon oxide film or metal wiring is used. It was common to use a capacitive element formed between the layers. First, the plan view of the conventional example
A sectional view taken along the line XX 'in FIG. 1 is shown in FIG. A capacitive element was formed by the dummy word line DWL1 made of the N ⁺ impurity diffusion layer 15 and the polycrystalline silicon layer, and formed as an insulating film at the same time as the gate insulating film of another MOS transistor arranged in the periphery (not shown). I am using one. In this example, the polycrystalline silicon layer forming the electrode of the capacitive element extends as it is in the direction perpendicular to the data line D, and becomes the dummy word lines DWL1 and DWL2 as it is. A region of the N ⁺ impurity diffusion layer 12 connected to the N ⁺ impurity diffusion layer region 15 is connected to a data line formed of aluminum through a contact opening.

[Problems to be solved by the invention]

Since the conventional dummy word system described above provides capacitive coupling between the dummy word line and the data line, the result is that capacitive coupling is provided between the data lines via the dummy word lines. Sometimes it has a drawback that it becomes a transmission path of noise.

Generally, in sense amplifiers, the determination speeds of memory cells “H” and “L” are not equal due to layout reasons, manufacturing reasons, etc., and the input differential voltage of the sense amplifiers at the time of memory cells “H” and “L”. Are not necessarily equivalent. Therefore, for example, as described above, when the word line WL1 is selected, only the memory cell connected to the data line is "L" and all the other memory cells are "H", and the sense for the memory cell "L" is detected. When the judgment speed of the amplifier is slow, the difference potential of the other data line pair is amplified by the sense amplifier before the potential difference of the data line pair D, becomes sufficiently large, and among the capacitance elements connected to DWL1 of the dummy word line. The counter electrodes other than those connected to the data line D fall sharply, so that the dummy word DWL1 falls due to capacitive coupling, but as a result, the potential of the data line D which has not yet sufficiently amplified the difference voltage should rise. However, it is pulled down and receives noise. In addition, the dummy word line DWL2 rises just in the opposite way, raising the potential of the data line and giving noise. These noise voltages cause a malfunction of the sense amplifier, which not only lowers the yield but also increases the inspection and measurement time due to the data pattern dependency of the operation margin, which becomes a problem. This problem becomes more serious as the storage capacity of the memory increases and the number of data line pairs sharing the dummy word line increases and the wiring resistance of the dummy word line increases.

[Means for solving problems]

In the semiconductor memory of the present invention, a first data line group and a second data line group to which a plurality of memory cells are connected form a pair, and each data line belonging to the first data line group and the first data line group In a semiconductor memory having a first dummy word line coupled by a first capacitance element, a second dummy word line coupled by a second capacitance element with each data line belonging to a second data line group, The first and second capacitive elements are composed of enhancement type MOS capacitors, the gate electrodes are connected to the first and second dummy word lines, and the substrate formed in the semiconductor substrate surface region adjacent to the MOS capacitors is a substrate. The impurity diffusion layers of opposite conductivity type are connected to the data lines.

〔Example〕

Next, the present invention will be described with reference to the drawings. The plan view is the same as that of the conventional example and is as shown in FIG. 1, but the cross-sectional view taken along the line XX 'in FIG. 1 is shown in FIG. The operation of the circuit itself is exactly the same as the waveform diagram of FIG. 5, and is as described in the conventional example. The point different from the conventional example is that the capacitive element between the dummy word line DWL1 and the data line is an enhancement type MOS capacitor, and one electrode of the capacitive element to be connected to the data line depends on the potential of the dummy word. It is the inversion layer 13 on the surface of the formed semiconductor substrate. In the case of this embodiment, the gate insulating film 14 and the dummy word line DWL1 can be formed simultaneously with the peripheral MOS transistors (not shown), and the N ⁺ impurity diffusion layers 11 and 12 are completely formed at the time of forming the source / drain of the peripheral MOS transistors. The same applies to the control of the dummy word potential that can form the inversion layer if it is formed at the same time (such as ion implantation into the channel region). For example, if the power supply voltage is 5V, the potential of the data line D, is 2.5V in the standby state, and the reference potential of the sense amplifier requires 2.4V, the stray capacitance of the data line is 20V.
Assuming that 0fF and the voltage (threshold value) that forms the inversion layer 13 are 1.0V, the capacitance value of one capacitive element is approximately 13fF.

First, in the standby state, the inversion layer 13 is formed below the dummy word line in the state where the data line D, is 2.5 V and the dummy word lines DWL1, DWL2 are 5 V, and this inversion layer is the N ⁺ impurity diffusion layer 12 In this state, the dummy word line DWL1 and the data line are capacitively coupled to each other because they are connected to the data line via. Then dummy word line DWL1
When the voltage drops to about 3.4 V, the inversion layer 13 disappears, and the capacitance between the dummy word line DWL1 and the data line is equal to the capacitance existing through the thick interlayer film between the dummy word line and the data line and N ^+.
The sum of the capacities between the impurity diffusion layer 12 and the dummy word line DWL1 is the sum of the capacities between the inversion layer 13 and the dummy word line DWL1 and can be suppressed to 20% or less. Moreover, the capacitance existing through the thick interlayer film between the dummy word line DWL1 and the data line also exists between the data line D and the dummy word line DWL1 which are paired with the data line. Therefore, it does not contribute to the noise transmission described as the problem of the conventional example. Because the dummy word line DW
This is because the change in L1 is transmitted similarly to the data line D, and the input differential voltage of the sense amplifier is not changed at all. Inversion layer
When 13 disappears, the potential of the data line is around the desired value 2.4V, and then the dummy word line DWL1 further drops, and even if it reaches 0V, the coupling capacitance between the dummy word line DWL and the data line becomes small. Therefore, the change in the level of the data line is very small. Then, as in the conventional example, the information of the selected memory cell is read onto the data line D and the sense amplifier is driven. The operation is the same as that of the conventional example.

〔The invention's effect〕

As described above, according to the present invention, the enhancement type MOS is used as the coupling capacitance element between the dummy word line and the data line.
By using a capacitor, it functions as a capacitive element when correcting the potential of the data line, and the inversion layer disappears after correction, so that the coupling capacitance between the data line and the dummy word line during activation of the sense amplifier is increased. The value decreases, and most of the remaining capacitance component is a component common to the data line pair, and it cannot become noise with respect to the sense amplifier input differential voltage. The decline can be reduced.

Another effect is to improve the accuracy of correcting the potential of the data line. That is, as described in the embodiment section, when the enhancement type MOS capacitor is used, the desired correction value can be obtained with the capacitance value of about 13 fF, whereas in the conventional example, the potential amplitude of the dummy word line is 5 V. Since the coupling capacitance between the dummy word line and the data line does not disappear midway as in the embodiment of the present invention, the calculated capacitance value is 4fF.
And have to achieve very small values. In this case, in FIG. 3, the area of the region forming the capacitive element of the dummy word line DWL1 and the N ⁺ impurity diffusion layer 15 becomes small, and the side surface of the dummy word line DWL1 and the N ⁺ impurity diffusion layer are actually formed.
Since the ratio of the capacitive components of 11 and 12 becomes large, there is a problem that the accuracy is deteriorated due to the influence of manufacturing variations, but according to the present invention, a relatively large capacitance value can be used. Therefore, the accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of the vicinity of a capacitive element belonging to a dummy word line, FIG. 2 is a sectional view of a capacitive element portion of an embodiment of the present invention (FIG. 1 XX ′), and FIG. 3 is a conventional example. 4 and 5 are respectively a circuit diagram and a waveform diagram for explaining the circuit operation. In FIG. 1, a solid line indicates a field region and a contact opening, a chain line indicates a dummy word line made of polycrystalline silicon, and a chain line indicates a data line made of aluminum. 21 is a P type semiconductor substrate, 22 is a P ⁺ channel stopper, 31 is a field oxide film, 32 is a cover film, 11, 12, 15 are N ⁺ impurity diffusion layers, 13
Is an inversion layer, 14 is a gate insulating film, ▲ ▼ is a row address strobe signal, WL1 and WL2 are word lines, DWL1 and DWL2 are dummy word lines, SE, SAN, and SAP are sense amplifier activation signals, and D,
Is the data line, PDL is the data line precharge signal, YSW, Y
SW ′ is a column selection signal, Q _P and Q _B are data line precharge balance transistors, C _S is a memory cell capacitance element, Q _C is a memory cell transfer transistor, C _DW is a dummy word capacitance element, and Q _Y is a column selection transistor. Are shown respectively.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 11/34 352 E

Claims (1)

[Claims] 1. A first data line group and a second data line group, to which a plurality of memory cells are connected, form a pair, respectively.
First dummy word line coupled with each data line belonging to the data line group of the first capacitance element, and each data line belonging to the second data line group coupled with the second capacitance element. 2 dummy word lines, both of the first and second dummy word lines are at a high level during a precharge operation, and a read operation of the data line pair is performed according to a row address input thereafter. Semiconductor memory in which the potential of one of the first dummy word line and the second dummy word line connected to the first data line group or the second data line group on the reference potential side drops In the above, the first and second capacitance elements are constituted by enhancement type MOS capacitors, and the gate electrodes of the MOS capacitors are the first electrodes.
Alternatively, an impurity diffusion layer having a conductivity type opposite to that of the substrate, which is connected to the second dummy word and is formed in a surface region of the semiconductor substrate adjacent to the MOS capacitor, is connected to the first and second data lines. A semiconductor memory characterized by being processed.