JPH0795399B2 - Read-only storage device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS LSI memory device, and more particularly to a static read-only memory device (hereinafter referred to as ROM).

[Prior Art] Conventionally, in this type of static ROM, as shown in FIG. 3, the source of the P-channel MOS transistor 14 is connected to the high voltage power source 6, and the drain is connected to the ROM output 13.
On the other hand, the source of the N-channel MOS transistor 15 for ROM cell is connected to the low-voltage power supply 7, and the drain is arbitrarily connected or not connected to the ROM 13.

When the address line 10 connected to the gate of the N-channel MOS transistor 15 for the ROM cell is selected, the drain is connected to the ROM output 13, so a voltage determined by the voltage division ratio with the P-channel MOS transistor is output. To be done. Also,
When address line 11 is selected, the drain is the ROM output 1
Since it is not connected to 3, the ROM output 13 outputs the same potential as the high-voltage power supply 6. A read signal is input to the gate of the P-channel MOS transistor 14, and the P-channel MOS transistor 14 turns on when operating as a ROM.

[Problems to be Solved by the Invention] In the conventional static ROM described above, when the P-channel MOS transistor and the N-channel MOS transistor are turned on at the same time, a current flows from the high-voltage power supply to the low-voltage power supply. However, there was a problem that

Further, even if the ROM cell is composed of a P-channel MOS transistor and an N-channel MOS transistor, there is a problem that it is not possible to meet the demand for reducing the wiring occupation area as much as possible in order to manufacture an LSI.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, and to provide a ROM that contributes to downsizing of an LSI by reducing the wiring occupation area while reducing the power consumption.

[Means for Solving the Problems] In the read-only memory device of the present invention, a ROM cell is composed of a P-channel MOS transistor and an N-channel MOS transistor, and the source of the P-channel MOS transistor is connected to a high voltage power supply. The source of the N-channel MOS transistor is connected to a low voltage power supply, and only one of the drain of the P-channel MOS transistor and the data line or the drain of the N-channel MOS transistor and the data line is connected. And the P channel
An inverter is inserted in the address line of the gate input of the P-channel MOS transistor so that addresses of different logic levels are input to the gate of the MOS transistor and the gate of the N-channel MOS transistor.
The M cells are connected to the same address line in a plurality of stages, and the data lines of the ROM cells in each stage are connected to the drain of the P channel MOS transistor and a first node and the output stage P channel MOS transistor and the output stage P channel MOS transistor. A gate circuit composed of an output stage N-channel MOS transistor connected between the drain of an N-channel transistor and the first node, wherein the output stage P-channel transistor and the output stage N-channel transistor are provided in response to a read signal. To turn on the output of the specified data line.
It is characterized in that it is connected to a gate circuit for outputting as a ROM output. [Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a circuit configuration which is an improvement of the conventional static ROM and which is a premise of the present invention.

The P-channel MOS transistor 1 and the N-channel MOS transistor 2 are transistors forming a ROM cell, and the source of the P-channel MOS transistor 1 is connected to the high voltage power supply 6. The source of the N-channel MOS transistor 2 is connected to the low voltage power supply 7. P-channel MOS transistor 1
Address signals having different logic levels are to be input to the gate of the N-channel transistor and the gate of the N-channel transistor 2 by the inverter 5. The drain of the P-channel MOS transistor 1 and the data line 3 are not connected, and the drain of the N-channel MOS transistor 2 and the data line 4 are not connected.
Are connected. Then, the data line 3 and the data line 4 are connected to form the ROM output 13.

The read operation in this ROM cell will be described. Since the N-channel MOS transistor 2 and the data line 4 are connected when the address line 10 is selected, the data line 4
Becomes the same voltage as the low voltage power supply 7, and the low voltage is output to the ROM output 13. Similarly, when address line 11 is selected,
The same potential as the high-voltage power supply 6 is output to the ROM output 13.

That is, in the circuit shown in FIG.
Current does not flow from the low voltage power supply 7 to the low voltage power supply 7, and power consumption can be reduced. Further, in the circuit of FIG. 1, the data line 3 is processed to the level of the high voltage power supply 6 in the case of high level output, and the data line 4 is processed to the level of the low voltage power supply 7 in the case of low level output.
The amplitude of the ROM output 13 can be increased. However, when a memory device is constructed using a plurality of circuits shown in FIG. 1, means for selecting the plurality of ROM outputs 13 is required.
If the source / drain paths of the OS transistor are connected and conduction control is selectively performed by the gate potential, the high level output will drop by the threshold voltage of the transistor or the low level depending on the conductivity type of this MOS transistor. There is a problem that the level output rises by the threshold value of the transistor and the amplitude of the output signal becomes small.

Therefore, FIG. 2 shows an embodiment of the present invention which solves the problem by using the ROM cell structure described above.

In this embodiment, the ROM cells are connected in two stages, and the ROM output on the upper side and the ROM output on the lower side are selected.
The output stage P-channel MOS transistor 8 and the output stage N-channel MOS transistor 9 are connected between the data line 3 and the data line 4. Upper output P-channel MOS
Transistor and output stage N-channel MOS transistors 8 and 9 have a read signal 16 at the gate of the lower output stage P.
The read signal 12 is input to the gates of the channel MOS transistor and the output stage N-channel MOS transistors 8 and 9. When the upper stage is selected, the read signal 16 is turned on, and when the lower stage is selected, the read signal 12 is turned on. Here, 2
Although the stepped configuration has been described, it is clear that the force side may be similarly connected in a configuration having three or more steps.

As described above, in the present embodiment, even when the memory device is configured by using a plurality of columns having the pair of data lines 3 and 4, the high level and low level of the ROM output are respectively set to the high voltage power source. , And can be made equal to the potential of the low-voltage power supply, and the amplitude of the output signal can be made large.

[Effects of the Invention] As described above, in the operation of the present invention, P
The power consumption can be extremely reduced by the configuration in which either the channel or N-channel MOS transistor is turned on. Since the address line and the data line can be shared by the ROM cells of a plurality of stages, the area occupied by the wiring in the LSI wiring can be reduced, which greatly contributes to the miniaturization of the LSI and the improvement in reliability. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic circuit configuration on which the present invention is based. FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional general ROM. 1 ... P-channel MOS transistor of ROM cell 2 ... N-channel MOS transistor of ROM cell 3, 4 ... Data line 5 ... Inverter 6 ... High-voltage power supply 7 ... Low-voltage power supply 8 ... Output stage P-channel MOS transistor 9 …… Output stage N channel MOS transistor 10,11 …… Address line 12,16 …… Read signal 13 …… ROM output 14 …… Bias P channel MOS transistor 15 …… ROM cell N channel MOS transistor

Claims (1)

[Claims] 1. A P-channel MOS transistor and an N-channel M
A ROM cell is formed by the OS transistor, the source of the P-channel MOS transistor is connected to a high voltage power source,
The source of the N-channel MOS transistor is connected to a low voltage power supply, and only one of the drain of the P-channel MOS transistor and the data line or the drain of the N-channel MOS transistor and the data line is connected. , So that the gates of the P-channel MOS transistor and the gate of the N-channel MOS transistor have different logic level addresses.
An inverter is inserted in the address line of the gate input of the channel MOS transistor, the ROM cells are connected to the same address line in a plurality of stages, and the data lines of the ROM cells in each stage are connected to the drain of the P-channel MOS transistor and the first line. Output stage P-channel MO connected between
A gate circuit composed of an S-transistor and an output-stage N-channel MOS transistor connected between the drain of the N-channel transistor and the first node, wherein the output-stage P-channel transistor and the output are provided by a read signal. A read-only memory device connected to a gate circuit for turning on a stage N-channel transistor and outputting an output of the designated data line as a ROM output.