JPH0795625B2 - Digital device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for efficiently realizing a large-scale digital system, and in particular, internal logic circuits, input / output circuits, and internal connections can be changed by external information. When a large number of integrated circuits (hereinafter referred to as programmable logic ICs) are used to realize desired functions, programmable
The present invention relates to a digital device including a method of transferring circuit definition information of a logic IC and a method of supplying a clock pulse to a programmable logic IC.

2. Description of the Related Art In recent digital systems, the tendency toward large-scale and high-speed operation is remarkable, and a method for embodying a target system has become a major issue.

For example, IDTV (Im
proved Definition Television) systems and field memory application systems for realizing special playback functions of video tape recorders include so-called digital signal processing such as digital filters and modulation / demodulation, and the scale of these systems is tens of thousands of gates. To 100,000 gates.

When implementing such a system, conventional general-purpose SSI (S
mall Scale Integrated Circuit) and MSI (Middle Sca
Le Integrated Circuit) is a huge scale and cannot be stored in a TV or VTR case, so it is usually a gate array, standard cell, or custom LS.
It is integrated in I (Large Scale Integrated Circuit) etc. to achieve miniaturization.

However, at the stage of developing the above LSI, a functional model that operates in real time is usually required.

In LSI development, it is not necessary to prototype a functional model, but in the field where it is necessary to judge the image quality with a large amount of input data such as an interface with a mechanism part such as a servo or video signal processing. It can be said that it is indispensable.

In such a case, one or two prototypes of SSI or MSI are used and used as a so-called breadboard circuit for determining the specifications of the LSI and checking the circuits of the LSI.

Even with these breadboard circuits, it is desirable that their scale be as small as possible, so PLD (Programab
A device called le Logic Device) is also used, but PLD is also SS
Only a few I's or MSI's can be accommodated, and an extremely small scale cannot be expected.

Problems to be Solved by the Invention When embodying a large-scale digital system as described above, if the conventional SSI, MSI, and PLD are used for configuration, the following problems occur.

First, the scale is extremely large. For example
In order to realize a digital system equivalent to 100,000 gates with SSI or MSI, if one IC has a function equivalent to 20 gates, 5,000 ICs are required. 50 I on one board
If C is to be mounted, 100 printed boards will be needed, and the scale will be such that it can be stored in a rack with a height of about 2 m. In this way, space is a direct problem, but there is also a problem that as the size increases, the wiring distance becomes longer and there are many prototype problems such as noise jumping in and common resistance of the earth line, making prototype difficult. is there.

Secondly, there is a problem that the circuit composed of SSI and MSI lacks flexibility for system changes and circuit changes.

Since wirings or patterns are designed so that each board has a different function, it is extremely difficult to change it once it is manufactured as a prototype.

In general, when used as a functional model, the specifications and circuits are usually changed, so this flexibility is extremely important in terms of development efficiency.

Third, there is a problem of labor required for circuit design and trial manufacture.

As described above, there are a great many types of boards whether they are wired or patterned, so the number of design and prototype steps becomes enormous, and it takes a long time to complete a digital system such as a functional model. Become.

Fourth is the economics of using it as a functional model.

After checking the operation with a functional model, designing the LSI, and when the development is completed, in most cases, the functional model will be discarded together with the board on which the IC is mounted, and the large amount of cost required for component cost and board design The problem is that it is wasted only once and is not economical.

As described above, when implementing a large-scale digital system or constructing a functional model of LSI by the conventional method, there are many problems.

In view of the above points, the present invention is to provide a digital device that can be combined into a large-scale digital system in a small size and that can flexibly cope with circuit changes.

Means for Solving the Problems According to the present invention, when embodying a digital system, a plurality of programmable logic ICs connected to each other by a wiring pattern fixed to a substrate are arranged, and the programmable logic ICs described above are used to realize a desired function.・ Internal logic circuit of logic IC,
The input / output circuit and internal connections are configured to match the fixed wiring pattern.

Further, a plurality of the boards are used, mounted on a rack to realize a digital system, and the circuit definition information of the programmable logic IC is transferred from a commonly connected circuit definition information line.

Further, the clock line for supplying the clock pulse to the programmable logic IC is configured to be fixed wiring in consideration of impedance matching and clock skew between adjacent programmable logic ICs.

Operation The present invention can realize a substrate on which many highly programmable programmable logic ICs are mounted by the above configuration.
A large-scale digital system can be integrated into a small size, and the internal circuit definition information of the programmable logic IC can be changed within a range that is compatible with the fixed wiring on the board, which is highly flexible.

Furthermore, since all the functions can be realized with one type of board, development efficiency is high.

In addition, the programmable logic IC and board can be reused, resulting in excellent economical efficiency.

Embodiment One embodiment of the digital apparatus of the present invention will be described with reference to the drawings.

1 and 2 are block diagrams showing an embodiment of a substrate forming a basic part of a digital device according to the present invention. 1
Is a substrate, 2 is an input line, and an n-bit digital signal is normally input to the substrate 1.

Reference numeral 3 denotes an output line, which normally outputs an m-bit digital signal from the substrate 1.

Reference numeral 4 is a circuit definition information line to which information for realizing the function of the substrate 1 is input.

Reference numerals 5 and 6 are input / output interface circuits. In the case of FIG. 1, 5 is selected as the input buffer 5'and 6 is selected as the output buffer 6 '.

Reference numeral 7 is a decoder circuit which serves to supply the circuit information of the programmable logic ICs 8 to 16 to each programmable logic IC based on the information from the circuit definition information line 4.

Reference numeral 17 is a mutual wiring between the programmable logic ICs 8 and 9.

18 and 19 shown in FIG. 2 are exactly the same as the substrate 1 shown in FIG. 1 (however, only the decoder 7 is different).
Circuit definition information line 4 with unique address code attached to 18,19
The decoder 7 decodes the address information out of the address information and the circuit information sent from the decoder 7, and transfers the circuit definition information only to the programmable logic IC on the substrate of the designated address.

Reference numeral 20 is a mother board fixed to the back of the rack on which the boards 1, 18 and 19 are mounted. On the motherboard 20, each board 1,
The bus lines connected in parallel to 18 and 19 are wired.

In FIG. 2, three substrates are used, but of course, any number of substrates can be used as long as a unique address is attached.

Further, the fixed route definition information of the programmable logic IC is input from the terminal on the dedicated software of the personal computer 21.

The circuit definition information is connected to the circuit definition information line 4 via the interface 22, and the circuit information is transferred as described above.

Here, the function of the programmable logic IC will be described.

The programmable logic IC itself can arbitrarily realize a small-scale digital function.

That is, the internal block has a logic circuit and an input / output circuit as a basic block, and wiring between the internal blocks can be freely set.

Therefore, the designer can realize a desired circuit operation by selecting and combining circuit specifications and mutual wiring.

Next, a digital device according to another embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is an embodiment of the substrate of the digital device according to the present invention.

Reference numeral 23 is a substrate, and 24-35 are programmable logic ICs arranged on the substrate.

36 and 37 are clock drivers, 38 is a supply line of a clock pulse for operating the programmable logic IC from the outside of the board, 39 is a clock line that supplies a clock to the programmable logic ICs 24 to 29, and 40 is a programmable logic IC 30. This is the clock line that supplies ~ 35.

Here, when trying to operate the programmable logic IC with high-speed clock pulses, the higher the clock frequency, the more the impedance matching of the clock lines and the clock skew between the programmable logic ICs become more problems.

First of all, regarding impedance matching, the clock line is not branched and only one line is programmable logic.
This can be solved by supplying it to the IC and adding terminating resistors 41 to 44.

Next, regarding clock skew, it is necessary to perform wiring in consideration of the physical length of the clock line.

This will be described with reference to the drawings.

In FIG. 3, the wiring delay per unit length of the clock line 39 is 1 nsec. Clock driver with time reference
36 outputs put at A point, 1n sec at B point, 2n s at C point
It has a delay of 3 ns at ec and D points, and similarly 9 ns at point J with respect to point A.

The same can be considered for the clock line 40.

Here, taking the programmable logic IC 27 as an example, the adjacent programmable logic ICs are the programmable logic ICs 24-26, 28-30, 32, and 34.

Of these, the clock skew is programmable at best
3n sec for logic IC29.

All others are 1n sec or 2n sec.

Also, if multiple clock pulses are required, they can be selected using a multiplexer.

In FIG. 3, reference numeral 45 denotes a multiplexer, which selects one (of course, a plurality of clock pulses can be provided by increasing the number of clock drivers and clock lines) from the plurality of clock pulses supplied from the bus line through the clock pulse supply line 38. .

Reference numeral 46 is a control signal for the multiplexer 45, which is a signal indicating which clock pulse is selected.

As is apparent from the above description, the present invention arranges a plurality of programmable logic ICs connected to each other on a substrate,
A large-scale digital system for configuring the internal logic circuit, input / output circuit, and internal connection of the programmable logic IC to realize desired functions so that the circuit definition information can be transferred and used so as to match the wiring pattern. Can be made compact and can be flexibly changed.

Also, regarding the clock line, the board has solved the items that are always problematic when embodying the digital signal processing circuit, such as impedance matching and clock skew. You can do it without considering it.

In addition to large-scale digital logic circuits, audio-related and video-related digital signal processing systems, LSIs, etc.
All digital systems such as functional models for development can be realized on the same board, so not only is development and prototyping efficiency high, but when the board is no longer needed, it can be used as it is for other systems including programmable logic ICs. Because it is possible, it is very economically excellent and has an extremely high industrial value.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a substrate which is a basic part of a digital device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a digital device according to the present invention, and FIG. It is a block diagram which shows the other Example of the board | substrate of a digital device. 1,18,19,23 …… Board, 4 …… Circuit definition information line, 7 …… Decoder circuit, 8 to 16,24 to 35 …… Programmable logic IC, 17 …… Interconnection, 39,40 …… Clock line, 4
1 to 44 ... Termination resistance.

Claims (5)

[Claims] 1. A substrate on which a plurality of programmable logic ICs connected to each other are arranged, a connection line connecting the substrates to each other, and an internal logic for realizing a desired function in the programmable logic IC. A digital device comprising: a circuit, an input / output circuit, and circuit definition information lines that send circuit definition information indicating a state of internal connection and are connected in parallel to each of the substrates. 2. A digital apparatus according to claim 1, wherein an address decoder is mounted on the substrate, and the circuit definition information is sent only to the programmable logic IC designated by the address information. 3. A plurality of programmable logics on a substrate
ICs are arranged, clock pulses are supplied from clock lines connected in parallel to each of the programmable logic ICs, the plurality of programmable logic ICs are divided into blocks by a predetermined number, and the divided clock lines are divided into blocks. A digital device characterized in that it is arranged to supply clock pulses. 4. The digital device according to claim 3, wherein the clock line is formed in consideration of a wiring route on the substrate in order to minimize clock skew between adjacent programmable logic ICs on the substrate. . 5. A configuration comprising a plurality of clock pulse supply lines for supplying clock pulses from outside the substrate and a multiplexer connected to the clock pulse supply lines, wherein a desired clock pulse is selected from the clock pulses. The digital device according to claim 3, wherein the digital device is provided.