JPH079568B2 - Common drive circuit for liquid crystal display - Google Patents

Description

The present invention relates to a liquid crystal display device drive circuit, and more particularly to an output display data phase control circuit in a common drive circuit for driving a common electrode of a liquid crystal display device. Regarding

(Prior Art) Liquid crystal display drive circuits include a common drive circuit that drives a common electrode of a liquid crystal display device and a segment drive circuit that drives a segment electrode, and these two drive circuits are used simultaneously. The common drive circuit LSI (large-scale integrated circuit) includes a shift register circuit 91 and a level conversion / output circuit 92, as shown in FIG. The common signal FP and the latch pulse LP are input to the shift register circuit 91, the common signal FP is sequentially shifted using the latch pulse LP as a data transfer clock, and the final shift output D
_Out is output to the data output terminal, and parallel common data C _{1 to} C ₁₀₀ are supplied to the level conversion / output circuit 92. This level conversion / output circuit 92 is provided with the common data C _{1 to} C ₁₀₀ , the liquid crystal drive power supply voltage VLCD, and the frame signal.
And a FR type, the frame signal and converts the common data C ₁ -C ₁₀₀ to a common drive output display data COM1~COM100
Output to the output terminal according to FR. The power supply voltage VLCD for driving the liquid crystal has four levels (from higher to lower).
VLCD 0, VLCD 2, VLCD 3), VLCD 0, VLCD 3 are the levels required to drive the liquid crystal to the lighting state (liquid crystal lighting level), and VLCD 1, VLCD 2 make the liquid crystal non-lighting state. Levels required for driving (liquid crystal non-lighting level), and these power supply voltage levels are selected by the level conversion / output circuit 92 according to the levels of the common data C _{1 to} C ₁₀₀ .

The waveforms of the signals of the common drive LSI are shown in FIG. 10, and the output display data COM 1 to COM 100 are synchronized with the trailing edge (falling edge in this example) of the latch pulse LP. This is because the 1-bit register circuit of the shift register circuit 91 reads the data at the rising edge of the latch pulse LP as shown in FIG.
And the clocked inverter 102 that outputs data at the rising edge of the inverted latch pulse ▲ ▼, that is, at the falling edge of the latch pulse LP are connected in series.

On the other hand, the LSI for the segment drive circuit has a shift register circuit 121, a latch circuit 122, and a level conversion / output circuit 123, as shown in FIG. The segment display data DIN and the system clock pulse SCP are input to the shift register circuit 121, the input data DIN is sequentially shifted using the clock pulse SCP as a data transfer clock, and the final shift output D _out is output to the data output terminal. At the same time, parallel segment display data D _{1 to} D ₁₀₀ are supplied to the latch circuit 122. The latch circuit 122, the segmented display data D ₁ to D ₁₀₀ and the latch pulse LP is input, latches the segment display data D ₁ to D ₁₀₀ in synchronism with the latch pulse LP. The level conversion / output circuit 123 receives the latch outputs S _{1 to} S _{100 of the} latch circuit 122, the liquid crystal driving power supply voltage VLCD (having four-value levels VLCD 0 to VLCD 3) and the frame signal FR, and Latch output S ₁
Select the power voltage level depending on the level of to S _100, and outputs to the output terminal as the segment driving output display data SEG 1~SEG 100 according to the frame signal FR.

A leading edge synchronous segment driving LSI using a leading edge synchronous latch circuit that latches in synchronization with the leading edge (rising edge in this example) of the latch pulse LP as the latch circuit 122 of the segment driving LSI, and the above latch circuit. As the 122, there are two types, that is, a trailing edge synchronous segment drive LSI using a trailing edge synchronous latch circuit that latches in synchronization with the trailing edge (falling edge in this example) of the latch pulse LP. In the leading edge synchronous latch circuit, a 1-bit latch circuit for each bit is, as shown in FIG. 12, a clocked inverter 131 driven by a latch pulse LP, and an output side of the clocked inverter 131. Connected to the inverter 132 and the clocked inverter 13 connected between the input and output ends of the inverter 132 and driven by the inverted latch pulse ▲ ▼.
3 and the latch outputs S _{1 to} S ₁₀₀ change in synchronization with the rising edge of the latch pulse LP.

Further, in the trailing edge synchronous latch circuit, a 1-bit latch circuit for each bit is driven by a latch pulse LP as shown in FIG.
And the clocked inverters 143, 144 driven by the inverted latch pulse ▲ ▼ and the inverters 145, 146 are connected, data is read at the rising edge of the latch pulse LP, and the rising edge of the inverted latch pulse ▲ ▼ (that is, the latch pulse LP Output data at the falling edge).

The waveforms of the above signals of the segment driving LSI as described above are shown in FIG. 14, and some signals are shown for the leading edge synchronous segment driving LSI and the trailing edge synchronous segment driving LSI, respectively. ing.

By the way, in the actual usage of the above-mentioned two types of segment drive LSIs, the leading edge synchronous type has a higher usage rate.
The latch circuit of the leading edge synchronous segment drive LSI (see Fig. 12) is the trailing edge synchronous segment drive LSI.
This is because the number of elements used is half that of the latch circuit (see FIG. 13) and the area occupied on the chip is half, which is advantageous in terms of the area and cost of the entire chip.

FIG. 15 shows operation waveforms when a liquid crystal display device is driven by simultaneously using the leading edge synchronous segment driving LSI and the common driving LSI. In this case, the output display data COM 1 to COM 100 of the common drive LSI changes in synchronization with the trailing edge (falling edge) of the latch pulse LP, and the output display data SEG1 to SEG100 of the segment drive LSI changes to the latch pulse LP. Since it changes in synchronization with the leading edge (rising edge), erroneous display occurs during the period when the latch pulse LP is at "1" level. Due to the existence of this period (erroneous display period), bleeding appears on the display surface of the liquid crystal display device, leading to a reduction in display quality and a shortened life of the liquid crystal.

In order to solve this problem, it is necessary to use common drive LSI and segment drive LSI whose output display data are in phase with each other. It is complicated to secure the required quantity in the required quantity.

(Problem to be Solved by the Invention) As described above, according to the present invention, when the phase of the output display data of the segment drive circuit and the phase of the output display data of the common drive circuit are deviated, the display bleeding phenomenon occurs. This problem was solved in order to solve the problem and the trouble of ensuring that the above two phases are synchronized, so that it can be synchronized with the phase of the output display data of the segment drive circuit used at the same time. In addition, the phase of the common output display data can be easily switched and controlled, the bleeding phenomenon of the display on the liquid crystal display surface can be eliminated, the display quality can be improved and the life of the liquid crystal display element can be prolonged. It is possible to provide a common drive circuit for a liquid crystal display, which can be used in combination with any one of two types of segment drive circuits having different phases of display data, and which is highly versatile. To aim.

[Structure of the Invention] (Means for Solving the Problems) A liquid crystal display common drive circuit according to the present invention has a data input circuit for latching a common data input by a clock pulse, and a data output of the data input circuit. A shift register circuit that sequentially shifts by a clock pulse,
The data output of the data input circuit and the parallel bit data output of the shift register circuit are input, and a level conversion / output circuit for level-converting and outputting to a common drive signal for liquid crystal display and a latch pulse and a phase switching signal are input. Then, a predetermined clock pulse is generated from the latch pulse according to the phase switching signal and is supplied to the data input circuit and the shift register circuit, and the data output of the data input circuit and the shift register circuit is set to the rising or falling edge of the latch pulse. And a clock control circuit for controlling so as to change in synchronism with.

(Operation) The phase of the common drive signal output can be synchronized with any one of the rising edge and the falling edge of the latch pulse according to the logic level of the phase switching signal input. Therefore, it becomes possible to switch and control the phase of the common drive signal output so as to be synchronized with the phase of the output display data of the segment drive circuits used at the same time.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a common drive LSI, in which a data input circuit (latch circuit) 2 is inserted between the common data input terminal and the data input terminal of the shift register circuit 1. A data output circuit (latch circuit) 3 is inserted between the last bit data output terminal and the data output terminal. The latch pulse LP input of the latch pulse input terminal is supplied to the data output circuit 3 and the clock control circuit 4. The clock control circuit 4 is also supplied with the phase switching signal TSW input to the phase switching signal input terminal, supplies two types of clock pulses φ ₁ and φ to the data input circuit 2, and supplies the clock pulse φ to the shift register circuit. 1 to the shift clock input terminal. The shift register circuit 1 sequentially shifts the data input with a shift clock. The output CD ₁ of the data input circuit 2 and the parallel bit data CD _{2 to} CD ₁₀₀ of the shift register circuit 1 are input to the level conversion / output circuit 5. The level conversion / output circuit 5 is supplied with the liquid crystal drive power supply voltage VLCD input from the liquid crystal drive power supply terminal and the frame signal FR input from the frame signal input terminal,
The bit data input from the data input circuit 2 and the shift register circuit 1 are level-converted, and common drive output display data COM 1 to COM 100 are output to output terminals.

FIG. 2 shows an example of a 1-bit circuit for each bit in the shift register circuit 1. The clocked inverter 21 is driven by an inverted clock pulse which is the clock pulse φ inverted, and is driven by the clock pulse φ. The clocked inverter 22 is connected in series. As a result, the data is read at the falling edge of the clock pulse φ and the data is read at the rising edge of the clock pulse φ.

FIG. 3 shows an example of the clock control circuit 4.
An OR gate 31 and a NAND gate 32 to which the phase switching signal TSW and the latch pulse LP are respectively input, and a NAND gate to which respective outputs of the OR gate 31 and the NAND gate 32 are input
33, an inverter 34 that inverts the output of the NAND gate 33 and outputs a clock pulse φ, and a NAND gate 35 that receives the output φ of the inverter 34 and the phase switching signal TSW and outputs a clock pulse φ _1. . here,
OR gate 31, NAND gates 32 and 33, inverter 34
Forms a matching circuit 36 that outputs a clock pulse φ having the same phase or an opposite phase as the latch pulse LP in accordance with the logic level of the phase switching signal TSW.

FIG. 4 shows an example of the data input circuit 2, in which a clocked inverter 41 driven by a clock pulse φ ₁ and a clocked inverter 42 driven by a clock pulse φ are connected in series. This allows
The common data input is latched at the rising edge of the clock φ ₁ and the data is output at the rising edge of the clock φ.

FIG. 5 shows an example of the data output circuit 3, which includes a clocked inverter 51 driven by an inverted latch pulse ▲ ▼ which is an inverted latch pulse LP, and an output data obtained by inverting the output of the clocked inverter 51. It consists of an inverter 52 which is D _out . As a result, the data input (the final bit output CD ₁₀₀ of the shift register circuit 1) is latched at the rising edge of the inverted latch pulse ().

Next, the phase switching signal TSW is added to the common drive LSI shown in FIG.
The operation when the "0" level is given and the operation when the "1" level is given are respectively described with reference to the signal waveforms shown in FIGS. 6 and 7. Clock control circuit 4 when TSW signal is “0”
Is clock pulse φ and “1” in phase with latch pulse LP
The level clock pulse φ ₁ is output. In the data input circuit 2, the clocked inverter 41 is always in operation by the "1" level clock pulse φ ₁ , and the clocked inverter 42 operates at the rising edge of the clock pulse φ, resulting in the output CD ₁ Changes in synchronization with the rising edge of the latch pulse LP. Shift register circuit 1
Is read at the rising edge of the inverted clock pulse and is output at the rising edge of the clock pulse φ, the outputs CD _{2 to} CD ₁₀₀ change in synchronization with the rising edge of the latch pulse LP. The data output circuit 3 rises the inverted latch pulse ▲ ▼ (falls the latch pulse LP)
Since it is read in synchronism with and is output after being inverted, the input data is output after being delayed by the period when the latch pulse LP is at "1" level. The level conversion / output circuit 5 level-converts the output bit CD ₁ of the data input circuit 2 and the parallel bit data CD _{2 to} CD ₁₀₀ of the shift register circuit 1 in the same manner as in the prior art, and outputs the common drive output display data COM. Outputs 1 to COM 100. In this case, the output display data COM1 to COM100 are output in synchronization with the rising edge of the latch pulse LP.

Contrary to the above, when the TSW signal is at "1" level, the clock control circuit 4 outputs the clock pulse φ having a phase opposite to the latch pulse LP and the clock pulse φ ₁ having the same phase as the latch pulse LP. The data input circuit 2 uses the clock pulse φ
_Since it is read at the rising edge of _{1 and} is output at the rising edge of the clock pulse φ, the output CD ₁ changes in synchronization with the falling edge of the latch pulse LP. The shift register circuit 1 is
The latch pulse is read at the rising edge of the inverted clock pulse and output at the rising edge of clock pulse φ.
Outputs CD _{2 to} CD ₁₀₀ change in synchronization with the falling edge of LP. The data output circuit 3 has an inverted latch pulse ▲
The data is read in synchronism with the rising edge of ▼ (falling edge of the latch pulse LP) and is inverted and output. Therefore, the input data is output as it is. The level conversion / output circuit 5 level-converts the output data of the data input circuit 2 and the parallel bit data of the shift register circuit 1, and outputs the common drive output display data COM 1
~ Outputs COM 100. In this case, output display data COM 1
~ COM 100 is output in synchronization with the falling edge of the latch pulse LP.

That is, according to the common drive LSI of the above embodiment, the output display data is the latch pulse LP when the TSW signal is "0".
The output display data of the segment driving LSI used at the same time is synchronized with the rising edge of the latch pulse LP when the TSW signal is “1”. By properly setting the logic level of the TSW signal depending on whether it is the down synchronization, an appropriate combination can be used.

It should be noted that in order to input the TSW signal from the outside, it is only necessary to add one dedicated external input terminal.

Further, the specific configuration of the clock control circuit is not limited to the above embodiment, and various modifications can be made.

[Effects of the Invention] As described above, according to the common drive circuit for liquid crystal display of the present invention, the phase of the common output display data can be easily adjusted so as to be synchronized with the phase of the output display data of the segment drive circuits used at the same time. Switching control is possible. Therefore,
It is possible to eliminate the display bleeding phenomenon on the liquid crystal display surface, improve the display quality and prolong the life of the liquid crystal display element, and combine it with any one of two types of segment drive circuits with different output display data phases. It can be used, and the versatility of the common drive circuit is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a common drive LSI for liquid crystal display according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing one bit of the shift register circuit in FIG. 1, and FIG. 1 is a circuit diagram showing an example of a clock control circuit in FIG. 1, FIG. 4 is a circuit diagram showing an example of a data input circuit in FIG. 1, and FIG. 5 is a circuit showing an example of a data output circuit in FIG. Figures 6, 6 and 7 show the operation waveforms when the TSW signal of the common drive LSI of Figure 1 is at "0" level and "1" level, and Fig. 8 is the conventional common drive. 9 is a block diagram showing an LSI for use in the circuit, FIG. 9 is a circuit diagram showing one bit of the shift register circuit in FIG. 8, and FIG. 10 is a diagram showing operation waveforms of the common drive LSI shown in FIG. Is the conventional segment drive LS
Block diagrams showing I, FIGS. 12 and 13 are circuit diagrams showing one bit of the latch circuit of the leading edge synchronous segment driving LSI and one bit of the latch circuit of the trailing edge synchronous segment driving LSI, FIG. 14 is a diagram showing operation waveforms of a leading edge synchronous segment driving LSI and a trailing edge synchronous segment driving LSI, and FIG. 15 shows a conventional common driving LSI and a leading edge synchronous segment driving LSI simultaneously. It is a figure which shows the operation waveform at the time of using. 1 ... Shift register circuit, 2 ... Data input circuit, 3
...... Data output circuit, 4 …… Clock control circuit, 5 ……
Level conversion / output circuit.

Claims (2)

[Claims] 1. A data input circuit for latching a common data input by a clock pulse, a shift register circuit for receiving a data output of the data input circuit and sequentially shifting by a clock pulse, a data output of the data input circuit, and the above. The parallel bit data output of the shift register circuit is input, the level conversion / output circuit that level-converts and outputs the common drive signal for liquid crystal display, the latch pulse and the phase switching signal are input, and the latch is performed according to the phase switching signal. Generate a predetermined clock pulse from the pulse and supply to the data input circuit and shift register circuit,
A common drive circuit for driving liquid crystal, comprising: a clock control circuit for controlling the data output of the data input circuit and the shift register circuit so as to change in synchronization with rising or falling of a latch pulse. 2. A coincidence circuit for detecting coincidence / disagreement of logic levels between a latch pulse input and a phase switching signal input, and outputting a clock pulse φ whose logic level is inverted according to the coincidence / mismatch. And a gate circuit which receives the output of the coincidence circuit and the phase switching signal input and outputs a clock pulse φ ₁ , and supplies the clock pulses φ and φ ₁ to the data input circuit, The common drive circuit for liquid crystal display according to claim 1, wherein the pulse φ is supplied to the shift register circuit.