JPH0795691B2 - Run length 1 / n compression floating encoder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code compression device used for high-quality recording and transmission of image data, and particularly to a run-length 1 / n compression floating system having a good instantaneous S / N ratio characteristic over a wide input range. The present invention relates to a coding device.

[0002]

2. Description of the Related Art In conventional satellite PCM broadcasting and digital audio tape recorders (hereinafter abbreviated as DAT), a comparatively light compression rate is taken into consideration in consideration of a trade-off with the amount of hardware while suppressing quality deterioration due to compression. Has been adopted. An example of these is the line code, DAT
In, a 12-bit 13-line code is used. For detailed technical standards, refer to "EI
AJ CP-2305 DAT Cassette Sy
system Part1: Dimension and
Characteristics ".

FIG. 19 (b) is a block diagram of 1 used in DAT.
It is a figure explaining the conversion method of 3 polygonal line code (12 bits), and shows a positive range. In the frame in the figure, the numbers in parentheses are decimal numbers, and the other numbers are binary numbers. The most significant bit of the binary number (hereinafter referred to as MSB) is the polarity bit P
And is "0" in the positive range and "1" in the negative range. "ABCDEFGH" in the figure is "0000000".
It is a value from "0" to "11111111", and "*"
Is an arbitrary binary number. Further, L0 is the run length of continuous data Q0 in which “0” continues, excluding the polarity bit of the original data.

With respect to the above coding method, the procedure will be described below. FIG. 19B is a diagram specifically showing conversion between encoding and decoding.

First, a method and apparatus for encoding 13 polygonal line codes (12 bits) will be described. The 16-bit area is divided into seven in the positive range, and the shift amount is manipulated according to each area. As is clear from the figure, the area division can be performed at a position where "1" is initially present when viewed from the MSB side. In other words, it can be determined by the run length L0 of continuous data of "0" excluding the polarity bit. Run length L
There are 8 types of 0 from “0” to “7 or more”, and the complement of L0 is expressed exponentially as range data. For example, the original data is “1216 (decimal)”, that is, “0000010”.
01000000 (binary) ", continuous data Q0
The run length L0 is “4”. Range data Q2
Is “011” which is the inverse of “100”. Also, "A
"BCDEFGH" is "00110000". Therefore, the output data is "001100110000". FIG. 19A is a diagram schematically showing the above concept. The output data is made up of 12 bits by synthesizing the polarity bit P, the range data Q2 representing the area, and the shifted mantissa data D2. Range data Q2 has a fixed word length of 3 bits. When the original data is 2'S (Tooth) complementary, the negative range can be encoded in exactly the same way as the positive range by inverting all the bits of P or less. The code in which the bit is inverted in the negative range is called a folded binary code. In the following description, a folded binary code will be used unless otherwise specified, but conversion with the 2'S complementary is mutually possible.

Next, a method and an apparatus for decoding a 13-line line code (12 bits) will be described.

For decoding, the range data Q2 of the polygonal line code is used.
Since the position of is known, the exponent part, that is, the range is reproduced by looking at the 3 bits after the polarity bit P. Since the position of the mantissa data D2 is also known, the run length L0 of the linear code (16 bits) is restored by the range data Q2, and the inversion bit T0 and the mantissa data D2 are added after that. When the code length W0 of the original data is less than, a fixed value is used. Decoding processing is performed according to such a procedure.

When the encoding and decoding described above are performed, the precision of expression is changed by rounding the information. Rounding of information occurs due to shift operations. Since the run length L0 is the same for "6" and "7 or more", there are seven types of shifts. Therefore, there are 14 types of positive and negative, but the same shift operation is performed in the central region with positive and negative, so the input / output characteristics of the entire region can be represented by 13 types of broken lines.

In each region of FIG. 19 (b),
The expression accuracy, that is, the resolution changes depending on the run length L0. When the run length L0 is "0" or "6",
The resolution is 10 to 16 bits in terms of bit length conversion.

The contents described above are summarized in (Table 1).

[0011]

[Table 1]

FIG. 20 is a characteristic diagram of a decompressed code obtained by decoding and decompressing a compression code of a conventional coding device using a polygonal line code with a decoding device. In the figure, the horizontal axis is the input level and the vertical axis is the instantaneous S.
/ N ratio is shown. However, the instantaneous S / N ratio is the square wave S / N.
About 2 dB of the ratio improvement is omitted for simplicity. In the figure, Z1 shows the characteristic of 13 polygonal line code (12 bits). Z1 will be described. The input level of 0 dB is based on the maximum amplitude of a sine wave that can be represented by a code. The straight line code "P11111111111111
1 ”corresponds to this. Input level 0dB to -6d
In the range of B, the linear code is "P1 *** ...",
From Table 1, the run length L0 is "0", so the resolution is 10 bits. The quantization noise of 10-bit data is -60 dB, with -6 dB per bit. Therefore, the instantaneous S / N ratio of the input level 0 dB to -6 dB is 60 dB to 54 dB.

Next, the input level is -6 dB to -12d.
In the range of B, the linear code is "P01 *** ...", and since the run length L0 is "1" from (Table 1), the resolution is 11 bits. The quantization noise of 11-bit data is -66 dB. Therefore, the instantaneous S / N ratio is 6
It becomes 0 dB to 54 dB. Similarly in the following, -96 dB
Z1 is the characteristic curve obtained by obtaining the instantaneous S / N ratio in the region up to. Here, at an input level of −36 dB or less, the characteristic curve is the same as that of a linear code (16 bits).

[0014]

However, in the above-mentioned conventional apparatus, the instantaneous S / N ratio is only 60 dB at the best, and at a finer input level, the instantaneous S / N ratio is the same as that of the linear code (16 bits). descend. In a digital recording / reproducing apparatus for business use that requires a margin (headroom) for excessive input, the average input level is set low and recording is performed, so the dynamic range that is actually used is narrowed, and the input level is Since the instantaneous S / N ratio becomes insufficient in a considerable range of, there is a problem that deterioration is increased in the editing that repeats amplification and attenuation. As described above, this problem also applies to linear codes (16 bits).

Preferably, it is required to satisfy the instantaneous S / N ratio characteristic of the hearing detection limit of about 48 dB or more in a wide range of the input level 0 to -96 dB.

As an improved method therefor, it is possible to easily consider a method of expanding the conventional 13-line-code (12 bits) to 16 bits. (Table 2) is a linear code (20 bits)
It shows a method of converting from to a polygonal line code (16 bits). In Table 2, since the word length of the mantissa data D2 is 12, the resolution is increased by 4 bits as a whole.

[0017]

[Table 2]

Line code (16 bits) shown in (Table 2)
The characteristic diagram of the decompression code that decodes and decompresses the compression code using is as shown by Z2 in FIG. In the device according to this improved method, the instantaneous S / N ratio is improved by 24 dB in the entire region, but in the input level range of -72 dB to -96 dB, the instantaneous S / N ratio is 48 dB or less, which is insufficient.
Therefore, if this signal is amplified by an amplifier, there is a problem that the quantization noise is auditorily detected.

The present invention solves the above-mentioned conventional problems, and an object thereof is to secure a hearing detection limit of about 48 dB or more of an instantaneous S / N ratio in a wide range of input level 0 to -96 dB. .

[0020]

In order to achieve this object, a run-length 1 / n compression floating encoder according to the present invention has a continuous data Q in which bits of a predetermined logic are consecutive in a high order.
An input unit for inputting a linear code composed of inverted bits T0 and lower data D0 after T0 that breaks the continuity of 0 and Q0, and stores Q1 in which the run length of Q0 is compressed to 1 / n and Compression means for storing inversion bit T1 that breaks continuity and mantissa data D1 obtained by rounding D0, and C1 memory for storing compression residue data C1 representing residue F1 generated when the run length of Q0 is compressed to 1 / n An output unit for reading the compressed continuous data Q1 and the inversion bit T1 from the compression means, the compression remainder data C1 from the C1 memory, the mantissa data D1 from the compression means, and outputting the compressed data.

However, when the run length of the continuous data Q0 is L0, the run length of the compressed continuous data Q1 is L1, and n is an integer of 2 or more, L1 = int (L0 / n) F1 = L0 mod n.

[0022]

According to the present invention, the redundant run length L0 of the original data fetched from the input section is compressed to about 1 / n and stored in the compression means by the above-mentioned device. At the same time, the C1 memory stores the compression residue data C1 representing the residue F1 generated during compression. The output unit reads the data compressed by the compression means and the compression residue data C1 from the compression residue data C1 memory and outputs the compressed data.

In the compressed data, the exponential part, that is, the range is constituted by the compressed continuous data, the inversion bit and the compressed remainder data. The exponent part or range changes according to the run length of the original data. That is, when the run length of the original data is small, the exponent part or range is specified with a small number of bits, and when the run length is large, the bit number is further allocated to specify the exponent part or range. When the word length of the entire code is finite and has a predetermined value, the number of bits assigned to the mantissa is changed according to the run length. By these actions, the space expressed by the compression code output from the output unit is expanded, and the expression accuracy can be maximized.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of a run length 1/2 compression floating encoder according to the first embodiment of the present invention. The operation will be described with reference to the drawings.

MSB represented by 2'S complement
First serial data is input to the input unit 1.
The input unit 1 converts the 2'S complement into a folded binary code. The conversion to the folded binary code is because the subsequent processing is simplified. In the input unit 1, the MSB which is a polarity bit is stored in the MSB memory 2, and the bits below the MSB are inverted and converted by the stored MSB. The folded binary code is supplied to the compression means 3 and also to the C1 memory 4. The compression means 3 is composed of a shift register having a shift enable function. That is, with respect to the run length portion of the input data, the run length is compressed to 2 / n and stored in the compression means 3 by setting the shift enable to every other shift. The C1 memory 4 obtains the surplus when thinning out every other by the compression means 3 by decoding the counter value of the timing generation unit 6 and stores it in the memory. These data are multiplexed by the output unit 5 and then output as output data of the inversely converted 2'S complement. The timing generation unit 6 supplies each timing signal to each unit.

FIG. 2 is a schematic operation timing chart in the first embodiment. The format of the input data is MSB first serial data represented by the 2'S complement as described above, and 28-bit data is input justified. SFCK is the bit clock and a clock 64 times the sampling frequency. Since the L channel and the R channel are multiplexed, the time for 32 clocks is allocated only to the L channel. LRC
K is a clock for identifying the L channel and the R channel. The last 4 bits are filled with zero data. The L channel portion of such input data is output at the input timing of the next R channel. Compressed to 16 bits
The output data set to 1 outputs 1 bit in two cycles of SFCK. As another method, one bit may be output in one cycle of SFCK and left-justified as in the case of the input data. In order to compress the R channel data, two encoders 8 in FIG. 1 are arranged and processed in parallel. FIG. 3 is a block diagram of an encoder for compressing the L channel and the R channel. In FIG. 3, the encoding device 8A and the encoding device 8B are the same device,
Input 802B to operate on the front and back of LRCK respectively
Insert the inverter 90 in front of. The output data 804A and the output data 804B are multiplexed by the multiplexer 91 and the multiplexed output data 904 is output as the output data CMPD.

Further details will be described below. FIG. 4 is a specific circuit diagram of the compression means 3. The compression means is composed of 14 shift registers of two types. The shift register 301 is a synchronous enable type shift register with an asynchronous set, and the shift registers 302 to 314 are synchronous enable type shift registers with an asynchronous reset. These are serially connected in series, and the common clock SFCK and
The common enable signal SFEN and the common asynchronous load signal NL0T are supplied. In the figure, input data S
When the enable signal SFEN is logic "H", the IDT is latched in the shift register 301 at the rising edge of the clock SFCK, and at the same time, the internal data is sequentially shifted to the right.
When the asynchronous load signal NL0T is supplied, the data “100 ... 0” is directly loaded internally. Figure 5
5A and 5B respectively show the shift register 30.
1 is an internal circuit diagram of shift registers 302 to 314. FIG. Since it is a basic circuit, its explanation is omitted.

FIG. 6 is a specific circuit diagram of the MSB memory 2. Input data ADDAT is input from a terminal 201, and a MSB is provided by a DFF with a synchronization enable configured by a selector 21 and a D-type flip-flop (hereinafter referred to as DFF) 22.
Latch. L as it is MSB first data
Enable on NL0T which goes to logic "L" on the first bit slot of the channel. The latched data is held until the next L channel data comes.

FIG. 7 is a specific circuit diagram of the C1 memory 4.
Reference numeral 41 is a JK type flip-flop (hereinafter referred to as JKFF). Input data SID converted to binary code
Data excluding the MSB of T is supplied to the input terminal K, and the output terminal Q is held at the logic "H" at the logic "H" that appears first. Also, since it is ORed with L27T, the output terminal Q is always used at the timing after the 27th bit of the L channel.
Are held at logic "H". The data at the output terminal Q is LDAT0. BITA is used as input data of the DFF with synchronization enable, which is composed of the selector 42 and the DFF 43.
Supply D0. BITAD0 is the LSB whose address data is the bit slot number of the L channel. Therefore, it represents the oddness of the bit slot number. Enable data supplies LDAT0. However, when the enable data is logic "L", the data is latched, and when the enable data is logic "H", the data is held. Therefore,
BITAD0 at that time when LDAT0 becomes logic "H"
That is, the odd number of the bit slot number is latched and held thereafter. The held data is output as LC1. Note that JKFF41 has N channels at the beginning of the L channel.
Initialized at L0T.

FIG. 8 is a specific circuit diagram of the timing generator 6. The description of the internal operation will be omitted, and the output signal will be described.

LSREND is set to the logic "L" at the beginning of the L channel, and the logic "H" is held by the logic "H" of the ESR 14 of the L channel. That is, when the "10000 ... 0" data loaded in the compression means 3 is sequentially shifted and the "1" of the shift register 301 reaches the ESR 14, LSREND holds the logic "H".

Since SFEN is used to control the shift enable of the compression means 3, switching is performed by shift-in of SIDT and shift-out of compressed data.

When SIDT is shifted in, if NL0T is logic "H", LSREND is logic, and LDAT0 is logic "H", logic "H" is output. Further, NL0T is logic “H”, LSREND is logic “L”, and LDAT is
If 0 is a logic "L", a logic "H" is output when BITAD0 is a logic "L".

When the compressed data is shifted out, ESR is performed.
The inverted bit T0 immediately after the compressed run length from 14 is detected and RSRT0 is held at logic "H".
This RSRT0 is delayed by SFCK and RSRT0D, R
SRT0DD and RSRT0RDDD are generated. From these, when outputting compressed data, LC1MSK for masking shift enable at the position of the compression residue data C1 and the switching signal LC1T for selecting the compression residue data C1 at the output unit 5 are respectively generated. S using these
FEN outputs logic "H" when BITAD0 is logic "H" and LC1MSK is logic "L".

As described above, LC1T is a switching signal for selecting the compression remainder data C1 at the output section 5.

Similarly, LMSBT is a switching signal for selecting the MSB data at the output section 5.

FIGS. 9A and 9B are concrete circuit diagrams of the input section 1 and the output section 5, respectively. Although detailed description is omitted, the reason why the output section 5 outputs the DFF through two stages is to shape the selector output because it causes a hazard, and to adjust the output timing of the compression means 3. is there.

The operation of the first embodiment described above will be described with reference to the timing chart. 10 to 13 are diagrams for explaining the input / output data of the compression means 3 and the timing processing of the timing generation unit 6. FIG. 10 shows a case where the run length is 0, FIG. 11 shows a case where the run length is 1, FIG. 12 shows a case where the run length is 20, and FIG. 13 shows a case where the run length is 26 according to the run length of the input data. It is a timing chart. The input data SIDT is a folded binary code, and data "0" is continuous in the run length L0 portion except for the polarity bit. Input data is sequentially shift-input to the shift registers 301 to 314. ESR1 to ESR14 are internal output data of the shift registers 301 to 314. In the input process to the compression means 3, after initialization with the initialization pulse NL0T, the LDAT generated by the timing generator 6 according to the run length.
The shift operation is controlled based on 0. When the inverted bit T0 and the remaining data D0 are shift-inputted and a total of 14 bits of data are fetched, the timing generation unit 6 outputs LSREN.
Set D and stop shift input based on this. SFEN directly controls the shift operation.

For example, in FIG. 12, the input data is MS
B, 20 "0" s, "1" of the inversion bit T0, and the remaining data D0 "ABC ...". Since LDAT0 is logic "L" during "0" of the run length 20, SFEN is set to logic "H" for every even number except 0, and shift enable is performed. In FIG. 12, run length 2
Since LDAT0 is logic "L" while "0" of 0,
For every even number except 0, SFEN is set to logic "H" to enable shift. Therefore, every other run length is thinned out to 10 and shift input. afterwards,
After the inversion bit T0, SFEN is set to logic "H" to continuously enable shift. When the inverted bit T0 and the remaining data D0, that is, "1ABC", are shift-input, and 14 bits are shift-input as a whole, LSREND is input.
And SFEN is set to logic "L" to stop the shift operation.

The compressed remainder data C1 is stored in the C1 memory 4 at the rising timing of LDAT0 as B
It is obtained by latching ITAD0. At the rising timing of LDAT0, BITAD0, which indicates the oddness of the bit slot, is 1 for the MSB and 20 for the run length of 21.
Therefore, it is “1”. That is, run length 20
Is a C1 memory 4 that is the complement “1” of the remainder “0”
It is latched and stored in.

In this way, compressed data is generated. Next, a process of extracting the compressed data of the L channel input data at the R channel input data timing will be described.

In FIG. 12, when the LRCK rises, the compression means 3 is prepared with the compressed data excluding the MSB data and the compression remainder data C1. The extraction of the compressed data is performed at twice the cycle of SFCK in order to match the output data timing. Therefore, the shift enable SFEN
Every other to logic "H". Run length L1 is 1
Since it is 0, when 10 "0" s are shifted and output, and then the inverted bit T0 "1" is output, RSRT0 of the timing generation unit 6 becomes logic "H". SFEN is masked by LC1MSK generated from RSRT0D, RSRT0DD, and RSRT0DDD, which are delayed RSRT0, and the logic is set to "L" only during that period. Therefore, the inversion bit T0 extends during that time. This is to create a slot for outputting the compressed remainder data C1. After that, the remaining data D
0 "ABC" is sequentially output. In this way, the compressed data is extracted.

Next, FIG. 13 shows the case where the run length is 26, but the operation differs from FIG. 12 in the following points. When the run length is large, the LDAT0 is set to the logic "H" at a fixed timing in order to stop the run length. Therefore, the timing generation unit 6 generates L27T to generate LDAT.
Reflect to 0. Therefore, LDAT0 is set to logic "H" at the timing of L27T regardless of the presence or absence of the inversion bit T0. Further, RSRT0 is forcibly set to logic "H" at the timing of R24T to create a slot for outputting the compressed remainder data C1. 10 and 11 show the case where the run lengths are 0 and 1, however, the operation is the same as that described above, and will be omitted.

With respect to the compressed data obtained in this way, some examples of the code configuration and the characteristics of the code will be described.

FIG. 14A is a conceptual diagram showing the structure of the run length 1/2 compression floating code in the embodiment of the present invention, and FIG. 14B is the linear code (30 bits).
FIG. 3 is a diagram for explaining code conversion for compressing a run length 1/2 compression floating code (16 bits).
In the figure, the same parts as those in the conventional example are given the same symbols.

The procedure of compression (encoding) will be described below with reference to the drawings. The compressed continuous data Q1 is continuous data having a length of the run length L1 which is an integer obtained by dividing the run length L0 of the continuous data Q0 by 2. That is, L1 = int (L0 / 2). If the remainder term of the integer division is the compression remainder F1, then F1 = L0 mod 2.

The inversion bit T1 is an inversion bit that breaks the run of the compressed continuous data Q1. Compressed residue data C
1 is the complement of the compression residue F1. In addition, the mantissa data D1 is higher-order partial data of the data D0.
The run length 1/2 compression floating code is arranged in the order of the polarity bit P, the compressed continuous data Q1, the inversion bit T1, the compression remainder data C1, and the mantissa data D1.

The case where the run length L0 is "0" to "28" will be described below with reference to FIG.

When L0 = 0, L1 and F1 are as follows: L1 = int (0/2) = 0 F1 = 0 mod 2 = 0.

Since the run length L1 is "0", there is no compressed continuous data Q1. The compression residue data C1 is “1”. The data D0 is 30 bits, of which the upper 13 bits "ABCDEFGHIJKLM" is the mantissa data D1.
Is. In the run length 1/2 compression floating code, the polarity bit P, the inversion bit T1, the compression remainder data C1 and the mantissa data D1 are arranged in this order, and “P11AB
CDEFGHIJKLM ".

Similarly, the following is obtained. When L0 = 1, L1 = int (1/2) = 0 F1 = 1 mod 2 = 1 Therefore, there is no compressed continuous data Q1 and compressed remainder data C1
Is "0". Upper 13 bits of data D0 "ABC
"DEFGHIJKLM" is the mantissa data D1. Run length 1/2 compression floating code is "P10AB
CDEFGHIJKLM ".

When L0 = 2, L1 = int (2/2) = 1 F1 = 2 mod 2 = 0 Therefore, the continuous data Q1 is "0" and the compression remainder data C1 is "1". Upper 12 bits of data D0 "A
BCDEFGHIJKL ”is the mantissa data D1. Run length 1/2 compression floating code is "P011
ABCDEFGHIJKL ".

When L0 = 3, L1 = int (3/2) = 1 F1 = 3 mod 2 = 1 Therefore, the continuous data Q1 is "0" and the compression remainder data C1 is "0". Upper 12 bits of data D0 "A
BCDEFGHIJKL ”is the mantissa data D1. Run length 1/2 compression floating code is "P010
ABCDEFGHIJKL ".

Further, when L0 = 20, L1 = int (20/2) = 10 F1 = 20 mod 2 = 0 Therefore, the continuous data Q1 is "0000000000" and the compression remainder data C1 is "1". . The upper 3 bits “ABC” of the data D0 are the mantissa data D1. Therefore, the run length 1/2 compression floating code is "P
000000000011 ABC ".

Further, when L0 = 28, L1 = int (28/2) = 14 F1 = 28 mod 2 = 0 Therefore, the continuous data Q1 is "0000000000000000."
The compression remainder data C1 is "1". There is no data D0 and no mantissa data D1. Therefore, the run length 1/2 compression floating code is "P00000.
0000000001 ".

In this way, the linear code (30 bits)
To a run length 1/2 compression floating code (16 bits).

Next, the decompression (decoding) procedure will be described. In the decoding procedure, the polarity bit P is removed from the compressed data, and the run length L1 is obtained from the compressed continuous data Q1 and the inversion bit T1. Further, the compression residue data C1 (1 bit) and the mantissa data D1 immediately after the inversion bit T1 are obtained. A compression residue F1 is obtained by inverting the compression residue data C1.

From these, the run length L0 of the continuous data Q0 of the original data is obtained from L0 = 2 * L1 + F1.

The continuous data Q0 is restored by connecting "0" having the length of the run length L0. An inversion bit T0 is added after the continuous data Q0, and then mantissa data D1 is added. The polarity bit P is added to the head to form the original data. When this code length is less than W0, a fixed value is assigned to the lower order of the mantissa data D1 to set the code length to W0. Decoding processing is performed according to this procedure.

Some cases of the run length L1 will be specifically described below with reference to FIG. 14 (b).

When L1 = 0 and F1 = 0, since L0 = 2 * 0 + 0 = 0, there is no continuous data Q0. The mantissa data D1 is 13 bits and is "ABCDEFGHIJKLM".
At this time, the original data is the polarity bit P and the inversion bit T0.
And mantissa data D1 are arranged, and “P1ABCDEF
GHIJKLM ******************** ”. "*** ..." is a fixed value "011 ..."
Shall be satisfied.

Similarly, when L1 = 10 and F1 = 0, L0 = 2 * 10 + 0 = 20. Therefore, the continuous data Q0 is "0000000000".
0000000000 "and mantissa data D1 is" AB
C ". At this time, the original data is obtained by arranging the polarity bit P, the continuous data Q0, the inversion bit T0, and the mantissa data D1 into “P000000000000000000”.
001ABC ******* ”.

In this way, the run length 1/2 compression floating code (16 bits) to the linear code (30
(Bit) are decoded and decompressed.

Table 3 shows the results summarized in all cases in the same manner as above.

[0066]

[Table 3]

In Table 3, the linear code (28 bits) is a folded binary code, and the floating code is a folded run length 1/2 compression floating code. The run length L0, run length L1 and resolution columns are decimal numbers.

The expression accuracy of the decompressed code obtained by decoding the compressed code and decompressed, that is, the resolution is determined by the rounding accuracy of the linear code in the linear code, and changes depending on the run length L0. From Table 3, a maximum accuracy of 28 to 15 bits can be obtained.

The instantaneous S / N ratio in the case where a linear code is input, compression coding is performed using a run length 1/2 compression floating code, and this code is decoded and a decompressed decompressed code is output will be described. . However, for the sake of simplicity, the instantaneous S / N ratio is the improvement of the S / N ratio of the rectangular wave (about 2 dB).
Is omitted. The input level is based on the maximum sine wave amplitude that can be represented by a code (0 dB). The straight line code "P11
11 ... ”corresponds to this.

The range of the input level from 0 dB to -6 dB is "P1ABC ..." With a straight line code (Table 3).
More resolution is 15 bits. The quantization noise of 15-bit data is -90 dB, where -6 dB per bit. Therefore, the instantaneous S / N ratio is 90 dB to 84 dB in the input level range of 0 dB to -6 dB.

In the input level range of -6 dB to -18 dB, a linear code "P01ABC ..." Or "P0
01ABC ... ”, and the resolution is 16 according to (Table 3).
Is a bit. Quantization noise of 16-bit data is -9
Since it is 6 dB, the instantaneous S / N ratio is 90 dB to 78
It becomes dB.

In the input level range of -18 dB to -30 dB, the linear code is "P0001ABC ..." Or "P00001ABC ...", and the resolution is 17 bits from (Table 3). Since the quantization noise of 17-bit data is -102 dB, the instantaneous S / N ratio is 84d.
B to 72 dB.

Similarly, the instantaneous S / N ratio is obtained in the input level region up to -180 dB. FIG. 16 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run length 1/2 compression floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve X1 in the figure is the run length 1/2 shown in (Table 3).
It represents the instantaneous S / N ratio of the compressed floating code. From the figure, the characteristic curve X1 shows that the input level is 0 dB to −
Hearing detection limit 48 dB of instantaneous S / N ratio in the range of 96 dB
It can be said that it is almost above.

Compared to the conventional linear code (16 bits), an instantaneous S / of about 42 dB at an input level of -96 dB is obtained.
An improvement in N ratio is achieved. The improvement of the instantaneous S / N ratio works over a wide range from the input level of -18 dB to -180 dB. Instantaneous S / N in the range of input level 0 dB to -6 dB
The ratio deteriorates, but the deterioration is 6 dB at most and still 90 d.
It has an instantaneous S / N ratio of B to 84 dB. This area is reserved as a margin and is a range that is rarely used normally, so there is no problem at all.

Further, in comparison with the polygonal line code (16 bits) shown in the characteristic curve Z2 of FIG.
There is an improvement of 6 dB in the range of dB to -12 dB, and an improvement of 18 dB is obtained at -96 dB.

Even if a signal of a minute level is thus amplified, the quantization noise can be made smaller than the auditory sense limit over a wide range up to the input level of -96 dB.
Therefore, the headroom can be sufficiently secured and the recording level can be set, and the recording level can be arbitrarily amplified in the later editing. Further, in order to improve the problem of the quantization noise of the unique spectrum that occurs in a signal of a minute level, it is possible to eliminate the processing such as adding white noise (dither) to disperse the noise spectrum.

In the present technology, the input level is 0 dB to -1.
Although it is difficult to amplify a wide range signal of 80 dB or digitize it with an AD converter, the effects of the present invention will be maximized due to future development of functional elements and circuit technology utilizing high temperature superconductivity. become able to.

In Table 3, the run length 1 /
Consider the increasing properties of a two-compression floating code. In the embodiment, since the compression remainder data C1 is the complement of the compression remainder F1, the numerical value of the upper range is always larger than the lower range at the boundary of the range. Therefore, this code has a monotonically increasing characteristic. If the compressed data is a linear code (1
Even if data is erroneously reproduced as 6 bits), the level inversion or jump does not occur with the monotonically increasing characteristic, which is advantageous. This action is based on the fact that the compression residue data C1 is the complement of the compression residue F1, but it is not necessarily required to be the complement and other expressions may be used.

As described above, it is difficult with the present technology to amplify a wide range of signals from the input level 0 dB to -180 dB or to digitize it with the AD converter. Therefore, when it is not possible to prepare a linear code of 30 bits, the linear code may be shortened as in the first embodiment. Table 4 shows a code decoding apparatus that compresses and expands a linear code (28 bits) into a run length 1/2 compression floating code (16 bits).

[0080]

[Table 4]

In this case, the run length L0 is cut off at a maximum of 26. Inversion bit T when run length L0 = 26
0 is omitted and the remaining data is D0. The encoding is the same, but the compression remainder data C1 is omitted and mantissa data D1, that is, D0 is arranged instead. As the run length L0 is cut off, the instantaneous S / N ratio characteristic is shown in FIG.
The characteristic curve X2 in FIG. Input level-162d
In the range from B to 0 dB, it is the same as X1 in the figure.

In the same manner, the linear code may be shortened to 24 bits. (Table 5) shows that the linear code (24 bits) is converted into the run length 1/2 compression floating code (1
6 shows a code decoding method of compressing and expanding to 6 bits).

[0083]

[Table 5]

In this case, the maximum run length L0 is "1".
Cut off at 8 ”. When the run length L0 = 18, the inversion bit T0 is omitted and the remaining data is D0. Although the encoding is the same, it is known that the maximum value of the run length L1 is "9", so that the inversion bit T1 may be any value. Further, the compression remainder data C1 is omitted and mantissa data D1, that is, D0 is arranged in its place. Instantaneous S / N due to termination of run length L0
The characteristic characteristic is the characteristic curve X3 in FIG. The input level is the same as X1 in the figure in the range of -114 dB to 0 dB. With any of the characteristic curves X1, X2, and X3 described above, the hearing detection limit of the instantaneous S / N ratio can be almost cleared in the range of the input level 0 dB to -96 dB.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 15A is a conceptual diagram showing the structure of the run length 1/4 compression floating code in the second embodiment of the present invention, and FIG. 15B is a diagram showing a concrete example for explaining the conversion processing. Is. In the figure,
The same parts as in the conventional example are given the same symbols.

The procedure of compression (encoding) will be described below with reference to the drawings. In the second embodiment, the linear code (32
It is a coding device that compresses and expands (bit) into a run length 1/4 compression floating code (16 bits).

The compressed continuous data Q1 is continuous data having a length of run length L1 which is an integer obtained by dividing the run length L0 of the continuous data Q0 by "4".

L1 = int (L0 / 4) If the remainder term of integer division is the compression remainder F1, then F1 = L0 mod 4.

The inversion bit T1 is an inversion bit that breaks the run length of the compressed continuous data Q1. The compression residue data C1 is the complement of the compression residue F1.
The mantissa data D1 is partial data on the upper side of the data D0. The run length 1/4 compression floating code has a polarity bit P, compressed continuous data Q1, and inversion bit T.
1, the compression remainder data C1, and the mantissa data D1 are arranged in this order.

The case where the run length L0 is "0" to "28" will be described below with reference to FIG. 15 (b).

When L0 = 0, L1 = int (0/4) = 0 F1 = 0 mod 4 = 0 Since the run length L1 is "0", there is no compressed continuous data Q1. The compression residue data C1 is “11”. The data D0 is 30 bits, and the upper 12 bits "ABCDEFGHIJKL" of the data D0 is the mantissa data D1. In the run length 1/4 compression floating code, the polarity bit P, the inversion bit T1, the compression remainder data C1 and the mantissa data D1 are arranged in this order, and “P111ABC
DEFGHHIJKL ".

Similarly, when L0 = 1, L1 = int (1/4) = 0 F1 = 1 mod 4 = 1 Therefore, there is no compressed continuous data Q1 and compressed residual data C1
Is "10". Upper 12 bits of data D0 "AB
"CDEFGHIJKL" is the mantissa data D1. Run length 1/4 compression floating code is "P110A
BCDEFGHIJKL ”.

When L0 = 3, L1 = int (3/4) = 0 F1 = 3 mod 4 = 3 Therefore, the continuous data Q1 is "0" and the compression remainder data C1 is "00". The upper 12 bits "ABCDEFGHIJKL" of the data D0 is the mantissa data D1. Run length 1/4 compression floating code is "P
100ABCDEFGHIJKL ".

Further, when L0 = 20, L1 = int (20/4) = 5 F1 = 20 mod 4 = 0 Therefore, the continuous data Q1 is “00000” and the compression remainder data C1 is “11”. . The upper 7 bits “ABCDEFG” of the data D0 is the mantissa data D1. Therefore, the run length 1/4 compression floating code is "P
00000111ABCDEFG ".

Further, when L0 = 23, L1 = int (23/4) = 5 F1 = 23 mod 4 = 3 Therefore, the continuous data Q1 is “00000” and the compression remainder data C1 is “00”. . The upper 7 bits “ABCDEFG” of the data D0 is the mantissa data D1. Therefore, the run length 1/4 compression floating code is "P
00000100ABCDEFG ".

In this way, the linear code (32 bits)
To a run length 1/4 compression floating code (16 bits).

Next, the procedure of decompression (decoding) will be described. In the decoding procedure, the polarity bit P is removed from the compressed data, and the run length L1 is obtained from the compressed continuous data Q1 and the inversion bit T1. Further, the compression remainder data C1 (2 bits) and the mantissa data D1 immediately after the inversion bit T1 are obtained. A compression residue F1 is obtained by inverting the compression residue data C1.

From these, the run length L0 of the continuous data Q0 of the original data is obtained from L0 = 4 * L1 + F1. The continuous data Q0 is restored by connecting "0" having the length of the run length L0. An inversion bit T0 is added after the continuous data Q0, and then mantissa data D1 is added. The polarity bit P is added to the head to form the original data. When this code length is less than W0, a fixed value is assigned to the lower order of the mantissa data D1 to set the code length to W0. Decoding processing is performed according to this procedure.

Hereinafter, some cases of the run length L1 will be specifically described with reference to FIG. 15 (b).

When L1 = 0 and F1 = 0, since L0 = 4 * 0 + 0 = 0, there is no continuous data Q0. The mantissa data D1 is 12 bits and is "ABCDEFGHIJKL". At this time, the original data is obtained by arranging the polarity bit P, the inversion bit T0, and the mantissa data D1 into “P1ABCDEFG”.
HIJKL ************** ”.
Note that "*** ..." is a fixed value of "1000 ...".

Similarly, when L1 = 5 and F1 = 0, L0 = 4 * 5 + 0 = 20, so the continuous data Q0 is "0000000000".
0000000000 "and mantissa data D1 is" AB
CDEFG ". At this time, the original data is obtained by arranging the polarity bit P, the continuous data Q0, the inversion bit T0, and the mantissa data D1 into “P0000000000000000”.
0000001ABCDEFG *** ”.

In this way, the run length 1/4 compression floating code (16 bits) is converted into the linear code (32 bits).
(Bit) are decoded and decompressed.

Similar to the above, the results summarized in all cases are shown in (Table 6).

[0104]

[Table 6]

From Table 6, according to the present embodiment, the maximum is 32.
Bit to 14 bit precision is obtained.

The instantaneous S / N ratio in the case where a linear code is input, compression coding is performed using a run length 1/4 compression floating code, and this code is decoded and a decompressed code is output is described. .

The range of the input level from 0 dB to -6 dB is "P1ABC ..." By a straight line code (Table 6).
More resolution is 14 bits. The quantization noise of 14-bit data is -84 dB, which is -6 dB per bit. Therefore, the instantaneous S / N ratio is 84 dB to 78 dB in the input level range of 0 dB to -6 dB.

In the input level range of -6 dB to -12 dB, the linear code is "P01ABC ...", and the resolution is 15 bits from (Table 6). Since the quantization noise of 15-bit data is -90 dB, the instantaneous S / N ratio is 84 dB to 78 dB.

In the input level range of -12 dB to -18 dB, the linear code is "P001ABC ...",
From Table 6, the resolution is 16 bits. Since the quantization noise of 16-bit data is -96 dB, the instantaneous S /
The N ratio is 84 dB to 78 dB.

In the input level range of -18 dB to -30 dB, the linear code is "P0001ABC ..." Or "P00001ABC ...", and the resolution is 17 bits from (Table 6). Since the quantization noise of 17-bit data is -102 dB, the instantaneous S / N ratio is 84d.
B to 72 dB.

Similarly, the instantaneous S / N ratio is obtained in the input level region up to -180 dB. FIG. 17 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compressed code using a run length 1/4 compression floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve Y1 in the figure is the run length 1/4 shown in (Table 6).
It represents the instantaneous S / N ratio of the compressed floating code. The characteristic curve Y1 clearly shows that the input level is 0 dB.
It exceeds the hearing detection limit of 48 dB of the instantaneous S / N ratio in the range of -96 dB.

Compared to the conventional linear code (16 bits), an instantaneous S / N of about 60 dB at an input level of -96 dB.
Ratio improvement is achieved. The improvement of the instantaneous S / N ratio works over a wide range from the input level of -18 dB to -196 dB. Instantaneous S / in the range of input level 0 dB to -12 dB
Although the N ratio is deteriorated, the deterioration is 12 dB at most.
It has an instantaneous S / N ratio of 84 dB to 78 dB. Since this area is a range that is not often used as a margin, there is no problem at all.

Further, in comparison with the polygonal line code (16 bits) shown in the characteristic curve Z2 of FIG.
There is an improvement in the range of 54 dB to -196 dB, -96
An improvement of 36 dB is obtained in dB.

As described above, according to the second embodiment, even if a signal having an input level of -144 dB, which is much smaller than that in the first embodiment, is amplified, the quantization noise is not detected by hearing. Therefore, the headroom can be sufficiently secured and the recording level can be set, and the recording level can be arbitrarily amplified in the later editing.

(Table 7) shows that the linear code (29 bits) is converted into the run length 1/4 compressed floating code (16 bits).
It represents a code decoding method for compressing and decompressing.

[0116]

[Table 7]

In this case, the maximum run length L0 is "20".
Abort with. When the run length L0 = 20, the inversion bit T0 is omitted and the remaining data is D0. The encoding is the same, but the maximum value of the run length L1 is known to be "5", so the inversion bit T1 is omitted. Further, the compression residue data C1 may be any data. Due to the termination of the run length L0, the instantaneous S / N ratio characteristic becomes the characteristic curve Y2 in FIG. Input level-1
In the range of 26 dB to 0 dB, it is the same as Y1 in the figure.

Further, in the same manner, the linear code may be shortened to 26 bits. (Table 8) shows that the linear code (26 bits) is converted into the run length 1/4 compressed floating code (1
6 shows a code decoding method of compressing and expanding to 6 bits).

[0119]

[Table 8]

In this case, the maximum run length L0 is "1".
Cut off at 6 ”. When the run length L0 = 16, the inversion bit T0 is omitted and the remaining data is D0. The encoding is the same, but the run length L1 is known to have a maximum value of 4, so the inversion bit T1 is omitted. Furthermore, the compression residue data C1 may be any data.
Due to the termination of the run length L0, the instantaneous S / N ratio characteristic becomes the characteristic curve Y3 in FIG. Input level-
In the range of 102 dB to 0 dB, it is the same as Y1 in the figure. With any of the characteristic curves Y1, Y2, and Y3 described above, the hearing detection limit of the instantaneous S / N ratio can be completely cleared within the range of the input level 0 dB to -96 dB.

Next, a third embodiment of the present invention will be described. The third embodiment is a coding method for compressing and expanding a linear code (24 bits) into a run length 1/4 compression floating code (8 bits). That is, the number of bits of the code in the second embodiment is changed. Therefore, the procedure for compression (encoding) and decompression (decoding) is the second step.
The description is omitted because it is the same as that of the embodiment.

The results summarized for all the exponents, that is, the ranges are shown in (Table 9).

[0123]

[Table 9]

From Table 9, according to this embodiment, a maximum of 24
Bit or 6-bit precision is obtained.

FIG. 18 shows the run length 1 / third of the third embodiment.
It is an instantaneous S / N ratio characteristic figure of the decompression | restoration code which decoded and expanded the compression code which used the 4-compression floating code. The horizontal axis of the figure shows the input level, and the vertical axis shows the instantaneous S / N ratio. The characteristic curve V1 in the figure represents the instantaneous S / N ratio of the run length 1/4 compression floating code shown in (Table 9).
The characteristic curve Y1 clearly shows a characteristic of a substantially flat instantaneous S / N ratio in a much wider input level range as compared with the linear code (8 bits). If this is the case S
Although it is less than the hearing detection limit of 48 dB for the / N ratio, it is possible to make use of a vast input level range and high resolution by combining with a differential code. It can be used for redundant compression that uses the correlation between samples of image data.

In the first to third embodiments described above, the linear code is a folded binary code, but 2'S.
Other linear codes such as complementary codes and offset binary codes can be applied in exactly the same way only by mutually converting or changing a predetermined logical value. Also, n has been described only in the case of “2” and “4”, but n may be any integer of “2 or more”. In this case, since the number of cases of compression remainder changes according to the value of n,
It goes without saying that the word length of the compressed remainder data may be changed and the shift enable control may be changed. Further, although the circuit configuration using the shift register is used in the embodiment, it may be configured by hardware and software of a DSP (digital signal processor) that performs similar data conversion.

[0127]

As described above, according to the present invention, the exponent is obtained from the compressed continuous data obtained by compressing the upper run length of the original data to about 1 / n, the inversion bit, and the residual data derived when compressing the run length. It generates the codes that make up the part or range. The exponent part, that is, the word length of the range changes according to the run length of the original data. With this operation, when the run length is small, the exponent part, that is, the range is configured with a small word length, and the word length of the mantissa part is increased, so that the expression precision can be maximized. Also, when the run length is large, the exponent part, or range, is configured with a large word length. Therefore, the exponent part, or range, can be subdivided and expressed to widen the input level range, and the space represented by the compression code can be expanded. To be done. As a result, both the accuracy and the input level range are maintained at or above the specified characteristics.When applied to digital recording / playback equipment for business editing, in particular, quantization noise will be heard even if mixing and dubbing involving amplification and attenuation are repeated. It is not detected, and the auditory detection limit of the instantaneous S / N ratio of about 48 dB or more can be secured in a wide range of the input level 0 to -96 dB.

[Brief description of drawings]

FIG. 1 is a run length 1 according to a first embodiment of the present invention.
Schematic block diagram showing the configuration of a 1/2 compression floating encoder

FIG. 2 is a schematic operation timing chart in the first embodiment.

FIG. 3 is a block diagram of an encoding device that compresses an L channel and an R channel.

FIG. 4 is a specific circuit diagram of compression means 3 in FIG.

5A is an internal circuit diagram of the shift register 301 in FIG. 4, and FIG. 5B is a shift register 302 to 31 in FIG.
Internal circuit diagram of 4

6 is a specific circuit diagram of the MSB memory 2 in FIG.

FIG. 7 is a specific circuit diagram of the C1 memory 4 in FIG.

8 is a specific circuit diagram of the timing generator 6 in FIG.

9A is a specific circuit diagram of the input unit 1 in FIG. 1, and FIG. 9B is a specific circuit diagram of the output unit 5 in FIG.

10 is a waveform diagram illustrating input / output data of the compression unit 3 and timing processing of the timing generation unit 6 in FIG.

11 is a waveform diagram illustrating input / output data of the compression unit 3 and timing processing of the timing generation unit 6 in FIG.

FIG. 12 is a waveform diagram illustrating input / output data of the compression unit 3 and timing processing of the timing generation unit 6 in FIG.

13 is a waveform diagram illustrating input / output data of the compression unit 3 and timing processing of the timing generation unit 6 in FIG.

FIG. 14A is a conceptual diagram showing the configuration of a run-length 1/2 compression floating code in the first embodiment of the present invention, and FIG. 14B is an explanatory diagram for explaining the same conversion process.

FIG. 15 (a) is a conceptual diagram showing the configuration of a run length 1/4 compression floating code in the second embodiment of the present invention, and FIG. 15 (b) is an explanatory diagram showing a concrete example for explaining the conversion process.

FIG. 16 is an instantaneous S / N ratio characteristic diagram of a restoration code obtained by decoding and expanding a compression code using a run length 1/2 compression floating code according to the first embodiment of the present invention.

FIG. 17 is an instantaneous S / N ratio characteristic diagram of a restoration code obtained by decoding and expanding a compression code using a run length 1/4 compression floating code according to the second embodiment of the present invention.

FIG. 18 is an instantaneous S / N ratio characteristic diagram of a restored code obtained by decoding and expanding a compression code using a run length 1/4 compression floating code according to the third embodiment of the present invention.

FIG. 19 (a) is a conceptual diagram showing a configuration of a conventional 13-line-line code (12 bits), and FIG. 19 (b) is an explanatory diagram showing a specific example for explaining the conversion method.

FIG. 20 is a characteristic diagram of a restoration code obtained by decoding and expanding a conventional compression code using a polygonal line code.

[Explanation of symbols]

 1 Input Unit 2 MSB Memory 3 Compressing Means 4 C1 Memory 5 Output Unit 6 Timing Generation Unit P Polarity Bit Q0 Continuous Data Q1 Compressed Continuous Data Q2 Range Data L0 Continuous Data Q0 Run Length L1 Compressed Continuous Data Q1 Run Length L2 Range Data Run length of Q2 T0, T1 Inversion bit D0 Remaining part data D1, D2 Mantissa data W0 Code length of original data W1, W2 Code length of compressed data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04N 1/419

Claims (9)

[Claims] 1. An inversion bit T which breaks the continuity of continuous data Q0 and Q0 in which bits of a predetermined logic are continuous in the upper order.
An input unit for inputting a straight line code composed of 0 and lower data D0 after T0; and an inversion bit T1 for storing Q1 in which the run length of Q0 is compressed to 1 / n and for breaking the continuity of Q1. A compression unit that stores the mantissa data D1 obtained by rounding the D0, a C1 memory that stores compression residue data C1 that represents a residue F1 that occurs when the run length of the Q0 is compressed to 1 / n, An output unit for reading the data Q1 and the inversion bit T1, reading the compression remainder data C1 from the C1 memory, reading the mantissa data D1 from the compression means, and outputting compressed data. 1 / n compression floating encoder. However, when the run length of the continuous data Q0 is L0, the run length of the compressed continuous data Q1 is L1, and n is an integer of 2 or more, L1 = int (L0 / n) F1 = L0 mod n. 2. The output unit outputs compressed continuous data Q from the top.
2. The run length 1 / n compression floating coding method according to claim 1, wherein the compressed data is output by arranging 1, inverted bit T1, compressed remainder data C1, and mantissa data D1 in this order. 3. A linear code composed of polarity bits P and inversion bits T0 that breaks the continuity of continuous data Q0 in which bits of a predetermined logic are continuous except for P and P0 and lower data D0 after T0 are input. An input unit for storing Q1 in which the run length of Q0 is compressed to 1 / n, and storing inversion bit T1 for breaking the continuity of Q1 and mantissa data D1 obtained by rounding D0; Cn memory that stores compressed residue data C1 that represents a residue F1 that occurs when compressed to / n, an MSB memory that stores the polarity bit P, the polarity bit P is read from the MSB memory, and the compression unit performs the compression. The continuous data Q1 and the inversion bit T1 are read, the compression remainder data C1 is read from the C1 memory, and the compressed data is compressed. Run length 1 / n compression floating coding apparatus characterized by comprising an output section for outputting the compressed data by reading the mantissa data D1 from the stage. However, the continuous data Q0
Where L0 is the run length, L1 is the run length of the compressed continuous data Q1, and n is an integer of 2 or more, L1 = int (L0 / n) F1 = L0 mod n. 4. Compressed residue data C stored in C1 memory
4. The run length 1 / n compression floating coding device according to claim 1, wherein 1 is a complement of the compression residue F1. 5. The output unit outputs compressed data having a predetermined code length W1.
The run length 1 / n compression floating encoder according to claim 1 or 3, wherein the lower bits of the data D1 are deleted so that 6. The compressing means and the C1 memory are such that when the smaller one of the predetermined limit length LS and the run length L0 is Lmin, L1 and F1 are L1 = int (Lmin / n) F1 = Lmin mod n The run length 1 / n compression floating encoder according to claim 1 or 3. 7. The output unit from the higher order is a polarity bit P, a compression continuous data Q1, an inversion bit T1, and a compression remainder data C.
4. The run length 1 / n compression floating coding method according to claim 3, wherein the compressed data is output by arranging the mantissa data D1 in this order. 8. The compression means and the C1 memory are such that L1 and F1 are L1 = int (Lmin / n) F1 = Lmin mod n, where Lmin is a smaller one of the predetermined limit length LS and the run length L0. The run length 1 / n compression floating encoder according to claim 6, wherein the inversion bit T0 and the inversion bit T1 are omitted when the run length L0 is larger than the limit length LS. 9. The compression means and the C1 memory are such that L1 and F1 are L1 = int (Lmin / n) F1 = Lmin mod n, where Lmin is a smaller one of the predetermined limit length LS and the run length L0. 7. The run length 1 according to claim 6, wherein when the run length L0 is larger than the limit length LS, the inversion bit T0 and the inversion bit T1 are omitted and the compression remainder data C1 representing the compression remainder F1 is set to a predetermined value. / N compression floating encoder.