JPH0795826B2 - Timing signal generation circuit - Google Patents

Description

The present invention relates to a timing signal generation circuit used for driving a CCD (Charge Coupled Device) image pickup device.

[Outline of Invention]

The present invention provides a timing signal for generating at least a clock pulse for driving an output horizontal register of a CCD image sensor and a sampling pulse supplied to a sample hold circuit for extracting only an image signal from a signal obtained from the CCD image sensor. By adding a phase adjusting function of the sampling pulse which can be adjusted from the outside to the generating circuit, it is possible to easily cope with various driving circuits of the CCD image pickup device.

[Conventional technology]

In general, CCD image sensors are driven by multiple pulses,
It realizes two functions, photoelectric conversion and scanning. For example, in the CCD drive circuit system shown in FIG. 2, the CCD image pickup device 20 as shown in the timing chart of FIG.
Drive pulses φH for driving the horizontal output register 20a of
₁ , φH ₂ and a drive pulse φPG for driving the output stage 20b of the horizontal output register 20a are used.

The sampling pulses φH ₁ and φH ₂ are applied to the electrodes 20c constituting the horizontal output register 20a via the drivers 23 and 24, and are used to transfer the signal charges accumulated in the horizontal output register 20a. Further, the drive pulse φPG is supplied to the precharge gate 2 of the output stage 20b via the driver 25.
Applied to 0d. The signal detected in the output stage 20b is transferred to the CDS (Co related
le Sampling) is output to the circuit 21.

The CDS circuit 21 is composed of a buffer amplifier 21a, sample hold circuits 21b, 21c, 21d, a differential amplifier 21e, etc., and uses two sampling pulses SHP, SHD to remove noise from the detection signal and obtain an imaging signal. Take out only.

The sampling pulses SHP and SHD used here are C above.
Although the CD image pickup device 20 is not directly driven, it is an essential pulse in this CCD drive circuit system for extracting the image pickup signal, and the timing signal generation circuit 22 for generating the drive pulses φH ₂ , φH ₁ , and φPG. Supplied by. Further, a plurality of pulses are also required for vertical-direction pulses (not shown), and these horizontal and vertical pulses are supplied from the timing signal generating circuit 22. (Large Scale Integrated
Circuit) is generally made.

The drive pulse group described above needs to satisfy a strict phase relationship in order to guarantee the normal operation, stable operation, margin, noise rejectability, etc. of the CCD image pickup device 20.

By the way, since the CCD image pickup device 20 is a capacitive heavy load, it is impossible to directly supply the drive pulses φH ₁ , φH ₂ , φPG from the timing signal generating circuit-22, and the drivers 23, 24, Supply through 25. At this time, a transmission delay occurs due to these drivers 23, 24, 25. For example, in the timing chart shown in FIG.
The driving pulse φH ₁ is supplied to the CCD image pickup device 20 as a pulse φH ₁ E to which a delay time tdr is added by passing through the driver 24. Similarly, a delay time tdr is added to the drive pulses φH ₂ and φPG, and the above C is used as φH ₂ E and φPGE, respectively.
It is supplied to the CD image pickup device 20.

Further, since the signal S1 obtained from the output stage 20b in the CCD image pickup device 20 is output via the buffer amplifier 20e, the signal with the transmission delay time tbuf added by the buffer amplifier 20e as shown in FIG. It is output as S2.

The CDS circuit 21 that removes noise from the signal S2 and extracts the image pickup signal uses two sampling pulses SHP and SHD, but the sampling pulses SHP and SHD supplied from the timing signal generation circuit 22 are the driver 26. , 27, the transmission delay time is added. Therefore, as shown in FIG. 3, the CDS circuit 21 is supplied with the sampling pulses SHPE and SHDE to which the delay time t'dr is added. In the CDS circuit 21, the sampling pulse S
Using HPE and SHDE, noise is removed from the signal S2 obtained from the CCD image pickup device 20 and a stepwise image pickup signal is output.

As described above, in the CCD drive circuit system, even if the phase relationships of the output pulses at the output terminals of the timing signal generation circuit 22 are exactly the same, the drivers 23, 2
The CCD image sensor 20 or the CDS circuit 21 after passing through 4,25, etc.
At the input terminal of, since the delay time is added by the drivers 23, 24, 25, 26, 27, it is necessary to set the phase relationship in consideration of these delay times.

[Problems to be solved by the invention]

Generally, in a high-resolution CCD image pickup device, the number of elements in the CCD is increasing, and the drive pulse described above is inevitably high in speed. Therefore, with respect to the high-speed drive pulse having a short cycle, the above-mentioned problem of delay becomes more severe, and the timing signal generating circuit outputs the sampling pulse or the like in a uniform phase relationship, and thus the CCD image sensor However, there is a problem that it is difficult to deal with the various drive circuit systems.

The present invention has been made in view of such problems,
It is an object of the present invention to provide a timing signal generation circuit which enables adjustment of the phase of a sampling pulse and the like and a duty ratio and can easily cope with various drive circuit systems.

[Means for solving problems]

In order to achieve the above object, the present invention provides a clock pulse for driving an output horizontal register of a CCD image sensor,
In a timing signal generating circuit for generating at least a sampling pulse supplied to a sample hold circuit for sampling and holding a signal obtained from a CCD image pickup device and extracting a signal portion, a clock generating circuit for generating the clock pulse, A plurality of serially connected delay circuits to which a reference pulse is supplied from the clock generation circuit; a plurality of selection circuits for selecting one pulse from a plurality of pulses having different delay times obtained by the delay circuit; The control circuit includes a logical operation circuit that generates the sampling pulse from a plurality of pulses selected by a plurality of selection circuits, and a control circuit that controls a selection operation of the plurality of selection circuits according to a control signal from the outside. Select operation of the above multiple selection circuits according to external control signals from the circuit It, is characterized in that to adjust the phase and the duty ratio of the sampling pulses.

[Action]

In the timing signal generation circuit of the present invention, the control circuit controls the selection circuit according to an input signal from the outside, the delay circuit selects a pulse having a predetermined delay time, and outputs it as a sampling pulse. To be done.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the timing signal generating circuit of this embodiment. This circuit applies a required drive pulse to the CCD image sensor 20 and the CDS circuit 21 in the general CCD drive circuit system shown in FIG. It corresponds to the timing signal generation circuit 22 to be supplied. That is, the drive pulses φH ₁ and φH ₂ for driving the horizontal output register of the CCD image sensor, the precharge pulse φPG to be supplied to the output stage of the horizontal output register, and the two sampling pulses SHP and SHD for the CDS circuit are output. To do.

As shown in FIG. 1, the timing signal generating circuit includes a clock generating circuit 7, a plurality of delay circuits DL1, DL2, ..., DLN, selectors 9, 10, 11, 12, 13, 14, a decoder 8, an AND circuit. 15,1
It is composed of 6,17 mag.

The drive pulses φH ₁ and φH ₂ are generated in the clock generation circuit 7 and output from the output terminals 1 and 2, respectively. The pulse φ output from this timing signal generating circuit
PG, SHP, SHD are based on the drive pulses φH ₁ and φH ₂ described above.

The reference pulse SDP is supplied from the clock generation circuit 7 to the delay circuit DL1, and the delay circuits DL1, DL2, ..., DL are supplied.
Pulses SDL1, SDL2, ..., SDLN with a predetermined delay amount from N
Is output. These signals SDL1, SDL2, ..., SDLN are supplied to selectors 9 ,.

The selectors 9, 10, ..., 14 are used to input the pulses SDL1, SDL
This is a circuit for selecting and outputting one pulse from 2, ..., SDLN, and its control is performed by a decoder 8. That is, the control data CS1, CS2,
.., 14 are selected according to CS6.

The output signals of the selectors 9 and 10 are supplied to the AND circuit 15, and the pulse φPG for precharging the CCD image pickup device is supplied.
Is output from the output terminal 5.

Further, the output signals of the selectors 11 and 12 are compared with the logical product circuit 16
And the sampling pulse SHP is generated and output from the output terminal 4. Similarly, the selector 13 and
A sampling pulse SHD is generated by passing the output signal of 14 through the AND circuit 17, and is output from the output terminal 3.

Here, the selectors 9 and 10 and the selectors 11 and 1
2. The logical product of the selectors 13 and 14 is to make the duty ratio of each pulse φPG, SHP, SHD variable.

The decoder 8 controls the above-mentioned control data CS1, CS2, based on the data supplied from the switch circuit 18 to the input terminal 6.
…, Output CS6. Therefore, by operating the switch circuit 18, for example, the selectors 9 and 10 are supplied with pulses.
By selecting a pulse having a large delay amount among SDL1, SDL2, ..., SDLN, the drive pulse φPG becomes a pulse whose phase is delayed from the drive pulse φH _{1 and the} like. Further, at this time, for example, if the selector 10 selects a different pulse from the pulse selected by the selector 9, the duty ratio of the drive pulse φPG can be adjusted.

This phase adjustment is performed by observing a signal at a predetermined location while driving the CCD image pickup device, the CDS circuit, etc. by the timing signal generating circuit. This makes it possible to easily set the optimum phase relationship even with respect to, for example, a difference in the CCD image pickup device or a change in the CDS circuit.

The decoder 8 is used instead of the switch circuit 18.
The data to be supplied to the memory may be supplied from a ROM (Read Only Memory). This can be done, for example, by using the empty area of the ROM used for CCD defect correction.

〔The invention's effect〕

As described above, the timing signal generating circuit of the present invention is
The phase and duty ratio of the sampling pulse can be adjusted by controlling the selection operation of the plurality of selection circuits according to the control signal from the outside by the control circuit.
Therefore, it is possible to adjust the phase and duty ratio of the sampling pulse to an optimum state even when the CCD image pickup device is different and the various drive circuit systems such as the CDS circuit are changed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram of a general CCD drive circuit system. FIG. 3 is a timing chart for explaining pulse delay in the CCD drive circuit system shown in FIG. 1,2,3,4,5 …… Output terminal 6 …… Input terminal 7 …… Clock generation circuit 8 …… Decoder 9,10,11,12,13,14 …… Selector 15,16,17 …… Logic Product circuit DL1, DL2, ..., DLN ... Delay circuit

Continuation of the front page (56) References Japanese Patent Laid-Open No. 58-10978 (JP, A) Japanese Patent Laid-Open No. 50-131737 (JP, A) Actual Japanese Laid-Open No. 57-56037 (JP, U)

Claims (1)

[Claims] 1. A clock pulse for driving an output horizontal register of a CCD (Charge Coupled Device) image sensor, and the CC.
In a timing pulse generation circuit that generates at least a sampling pulse supplied to a sample hold circuit for sampling and holding the signal obtained from the image pickup device and extracting the signal portion, a clock generation circuit that generates the clock pulse, A plurality of serially connected delay circuits to which a reference pulse is supplied from the clock generation circuit; a plurality of selection circuits for selecting one pulse from a plurality of pulses having different delay times obtained by the delay circuit; The control circuit includes a logical operation circuit that generates the sampling pulse from a plurality of pulses selected by a plurality of selection circuits, and a control circuit that controls a selection operation of the plurality of selection circuits according to a control signal from the outside. Selective operation of the above selection circuits according to external control signals by the circuit A timing signal generation circuit characterized in that the phase and duty ratio of the sampling pulse are adjusted according to the operation.