JPH0797603B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which power supply wiring is arranged in the lowermost layer and signal wiring is arranged in the uppermost layer. The master slice method is a method of making a different type of custom LSI by changing part of the manufacturing process. The gate array adopts a "wiring process" as a process that differs for each type, and has a high degree of freedom in circuit formation. Semi-custom LS that takes advantage of the efficiency in almost the final process
I. The name "gate array" is based on the fact that NAND and NOR, which are the simplest logic circuits, are used as basic gates, and these are arranged (arrayed) on a semiconductor chip. By wiring the basic gates to each other,
A random logic LSI dedicated to a customer is made.

[0002]

2. Description of the Related Art FIG. 3 is a plan view schematically showing a gate array formed on a semiconductor chip. In FIG. 3, 21 indicates a first-layer power supply wiring, 22 indicates a cell, and interlayer insulation is formed on the wiring. The second layer power supply wiring 23 is formed through the film. Figure 4
3 is a cross-sectional view of a part of the gate array of FIG. 3, in which the same parts as those shown in FIG. 3 are denoted by the same reference numerals, and 20 indicates a semiconductor substrate, and in this substrate 20, A cell is formed. The signal wiring is shown with reference numeral 25.

[0003]

In the gate array of FIG. 3, since the first layer power supply wiring is a fixed wiring, it occupies a wide wiring area regardless of the actual gate usage rate. The reason is that the wiring is formed in advance so that any gate may be used. Next, cells 22a and 22b in FIG.
In the case where the signal wiring 24 is to be connected with the signal wiring, if the signal wiring 24 shown by the dotted line is directly wired between both cells, the signal wiring will cross the first layer power supply wiring 21. Is impossible. Therefore, the first-layer signal wiring 25a is laid in parallel with the first-layer power wiring 21 and the signal wiring is formed in the upper layer (second layer) by using the through hole at the right end of the signal wiring 25a as shown in the figure. 2nd layer signal wiring 25
Wire b to the top of the cell 22b, and then connect to the cell 22b with a through hole. This brings about a problem that the degree of freedom of wiring of the signal wiring is narrowed. Next, referring to FIG. 4, with respect to the signal wiring 25 that passes under the second-layer power supply wiring 23, there is a problem that a parasitic capacitance indicated by C in the drawing occurs.
The present invention has been made in view of such a point, and the area occupied by the fixed power supply wiring is made small, and the parasitic capacitance generated between the signal wiring passing below the power supply wiring and the power supply wiring. It is an object of the present invention to provide a gate array wiring system that reduces the number of wirings and increases the degree of freedom of wiring of signal wirings.

[0004]

SUMMARY OF THE INVENTION In a semiconductor integrated circuit device having a plurality of basic gates arranged in a semiconductor chip, all the power supply wirings for supplying power to the basic gate are provided on the semiconductor chip. To provide a semiconductor integrated circuit device characterized in that it is provided in one layer, and all signal wirings connecting a plurality of the basic gates are provided in a second layer above the power supply wirings with an insulating film interposed therebetween. Will be solved by.

[0005]

That is, in the present invention, all the power supply wirings are provided in the first layer, and all the signal wirings for connecting the basic gates are provided in the second
It is provided in a layer to improve the degree of freedom in designing the signal wiring. Since all the power wiring has been moved to the first layer, the semiconductor chip area can be effectively used, and the signal wiring can be used as a power wiring. The parasitic capacitance of the signal wiring is small because the wiring is provided at the shortest distance regardless of the wiring and the power wiring is not provided in the second layer.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in FIGS. In the figure, 11 is a semiconductor chip, 11A
Is the first layer, 12 is a cell, 13 is a Vcc line, 14 is a V _EE line, 15a,
15b, 15c, 15d, 15e are gates, 16 is the second layer, 17a,
17b, 17c, 17d and 17e are terminals, and 18 is a signal wiring. Referring to FIG. 1, cells 12 are formed in an array on a first layer 11A of a semiconductor chip 11, and these cells are provided with basic gates 15a, 15b ... 15e. These are the same as the conventional example, but in the example shown in the figure, the Vcc line 13 and the V _EE line 14 which are the power supply lines are all formed in the first layer. The wiring for these power supplies is Vcc =
Since OV and V _EE are -3.6 to -5.2V, for example, width 50 to 150
It is formed to a size of μm. Since all the power supply wirings are provided in the first layer 11A and the signal wirings are not provided in the first layer as described above, only the cells and the power supply wirings are provided in the first layer. Because it is good, the area occupied by the power supply wiring can be made small, the chip size can be made small or the number of channels can be made large, and
This has the effect of reducing the number of steps.

In the example of FIG. 1, when it is desired to interconnect the basic gates 15a and 15d and the basic gates 15b and 15e, terminals 17a, 17d and 17b are formed from these basic gates through through holes.
2 and 17e are provided on the second layer 16 formed on the first layer 11A via an insulating film (not shown) as shown in FIG. 2, and then the terminals 17a and 17d and 17b and 17e are connected by the signal wiring 18. To do.
Since the diagonal wiring between the terminals 17b and 17e could not be formed in the conventional example, the signal wiring is shortened and the wiring flexibility is increased. In a typical application, the current flowing in the signal wiring is 200 to 600 μA, V _OH is −0.9 V, and V _{OL is}
Is -1.4 to -1.7V, the width of signal wiring is 5μm
Form to a degree. Since the power supply wiring does not exist in the second layer, the parasitic capacitance C between the signal wiring and the upper power supply wiring shown in FIG. 4 is eliminated, and the parasitic capacitance of the signal wiring is smaller than that in the conventional example. Get smaller. The arrangement of such signal wiring is one example, and the signal wiring is formed in other different patterns.

[0008]

As described above, according to the present invention, since the signal wiring is not provided on the first layer, only the cells and the power wiring are provided, and therefore the area occupied by the power wiring can be made small. It becomes possible to reduce the chip size or increase the number of channels.Since there is no power supply wiring pattern in the signal wiring area, diagonal wiring is possible and the signal wiring is shortened. There is an effect that the parasitic capacitance between the power supply wiring and the signal wiring can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a first layer according to an embodiment of the present invention.

FIG. 2 is a plan view of a second layer of the embodiment of the present invention.

FIG. 3 is a plan view of a conventional example.

FIG. 4 is a sectional view of a main part of a conventional example.

[Explanation of symbols]

11 Semiconductor chip 11A First layer 12 cells 13 V _CC line (power supply line) 14 V _EE line (power supply line) 15a ・ ・ ・ 15e Basic gate 16 Second layer 17a ・ ・ ・ 17e Terminal 18 Signal line 20 Semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display H01L 21/88 Z

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a plurality of basic gates arranged in a semiconductor chip (11), power supply wirings (13, 14) for supplying power to the basic gates (15a ... 15e) are provided. All of the first layer (1
1A), and all the signal wirings (18) connecting between the plurality of basic gates (15a ... 15e) are provided on the second layer above the power supply wirings.
A semiconductor integrated circuit device characterized in that it is provided in (16) via an insulating film.