JPH0797629B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a nonvolatile memory function capable of erasing information by ultraviolet rays (hereinafter referred to as EPROM). That is) applied to effective technology.

[Conventional technology]

A semiconductor integrated circuit device having a MISFET is apt to cause so-called electrostatic breakdown in which the gate insulating film forming the input stage circuit is destroyed by a steep and extremely high excessive voltage induced by artificial handling. Therefore, an electrostatic breakdown prevention circuit (protection circuit) is provided between the external input terminal to which an excessive voltage is input and the input stage circuit.

The electrostatic breakdown prevention circuit is generally a MISFET for clamping in which a protective resistance element and a gate electrode and a source region are grounded.
It consists of and. According to this electrostatic breakdown prevention circuit, the excessive voltage can be alleviated by the time constant circuit of the protective resistance element and the clamp MISFET, and the peak value of the excessive voltage can be reduced, so that electrostatic breakdown can be prevented. Also, MI for clamp
Since the excessive current flows toward the substrate due to breakdown at the Pn junction between the drain region of the SFET and the substrate, electrostatic breakdown can be prevented.

The protective resistance element and the clamping MISFET of this type of electrostatic breakdown prevention circuit are formed in the same manufacturing process as the MISFET forming the internal circuit. That is, it is possible to reduce the number of manufacturing steps for forming the electrostatic breakdown prevention circuit. Regarding the technology for preventing electrostatic breakdown, see, for example, Japanese Patent Application No. 57-1609.
No. 99.

[Problems to be solved by the invention]

However, as a result of the examination in such technology, MISFET
Employing LDD (L ightly D oped D rain ) structure,
It has been found by the present inventors that the following problems occur.

The MISFET of the LDD structure has a low impurity concentration (LDD portion) in the source region or the drain region near the channel formation region. This is because the deterioration of the threshold voltage with time due to hot carriers is suppressed. In the clamp MISFET using this LDD structure, the Pn junction is more likely to be destroyed when an excessive current flows to the substrate side due to breakdown, as compared with the one without the LDD structure. This is because the LDD portion, which has a low impurity concentration, has a high resistance value, so that thermal destruction of the Pn junction portion occurs at this portion. Also, since the breakdown voltage in the LDD part, which has a low impurity concentration, becomes high, P
This is because the electric field breakdown of the n-junction occurs. For this reason, LDD
In the clamp MISFET having the structure, the electrical reliability of the electrostatic breakdown prevention circuit against electrostatic breakdown is lowered.

An object of the present invention is to improve the electrical reliability of an EPROM by suppressing the temporal variation of the threshold voltage due to hot carriers, and to improve the electrostatic breakdown voltage of the input section or the output section. To provide various technologies.

Another object of the present invention is to provide a technique capable of achieving the above object in an EPROM without increasing the number of manufacturing steps.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The following is a brief description of the outline of the typical inventions among the inventions disclosed in the present application.

That is, the present invention relates to a first field effect transistor forming a memory cell having a gate electrode structure including a floating gate electrode and a control gate electrode located above the floating gate electrode, and a gate electrode structure of the memory cell. Is a semiconductor integrated circuit device in which a first and a second field effect transistor having different gate electrode structures are provided on one semiconductor substrate, and the channels of the first, second and third field effect transistors are The region in contact with the formation region has an LDD structure, and the LDD portions of the first and third field effect transistors have a higher impurity concentration than that of the LDD portion of the second field effect transistor. In the field effect transistor of No. 3, its drain region is connected to an external terminal, its source region and gate electrode It is connected to a reference voltage, and has a clamping field effect transistor.

[Action]

By the means described above, the internal circuit is the MISFE of the LDD structure.
Since T (second field effect transistor) can suppress the threshold voltage fluctuation due to hot carriers, it can improve the electrical reliability and also for clamping the electrostatic breakdown prevention circuit.
Since the MISFET (third field effect transistor) can reduce the resistance value of a portion where an excessive current flows to prevent thermal breakdown and lower the breakdown voltage to prevent electric field breakdown,
The electrostatic breakdown voltage can be improved.

Further, since the clamp MISFET can be formed in substantially the same manufacturing process as the field effect transistor of the memory cell, the manufacturing process for forming the electrostatic breakdown prevention circuit can be reduced.

In particular, according to the present invention, the MISFET for clamping has a fine structure with a simple gate structure similar to the internal circuit, instead of matching the gate structure with the memory cell, and sufficiently improves electrostatic breakdown voltage. it can.

[Example I]

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to an EPROM.

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The input portion of the EPROM which is Embodiment I of the present invention is shown in the equivalent circuit diagram of FIG.

The input section of the EPROM is constructed as shown in FIG. That is, external input terminal (bonding pad) BP
An electrostatic breakdown prevention circuit II is provided between the input circuit I and the input stage circuit I of the internal circuit (peripheral circuit).

The input stage circuit I includes an n-channel MISFETQn and a p-channel MISF.
It is composed of an inverter circuit with ETQp. Vcc is a power supply voltage (for example, a circuit operating voltage 5 [V]), and Vss is a reference voltage (for example, a circuit ground voltage [0]). Pout
Is an output signal terminal of the input stage circuit I.

The electrostatic breakdown prevention circuit II includes, for example, a protective resistance element R and a clamp MISFET Qc. The MISFET Qc is composed of a field effect transistor having a gate electrode formed in the same layer as the floating gate electrode or the control gate electrode. In the MISFETQc, the drain region is connected to the external input terminal BP and the input stage circuit I, and the source region and the gate electrode are connected to the reference voltage Vss. This M
Although not shown in FIG. 1, the ISFETQc has the same structure as the source region or the drain region near the channel region of the field effect transistor of the memory cell.

Next, a specific configuration will be described.

Embodiment I of the present invention, MIS for clamping the input part of EPROM
The FET, the field effect transistor of the memory cell, and the MISFET of the internal circuit are shown in the cross-sectional view of the main part of FIG.

In FIG. 2, 1 is a p ⁻ type semiconductor substrate (or well region) made of single crystal silicon, 2 is a field insulating film, and 3 is a p type channel stopper region.

The clamp MISFET Qc of the electrostatic breakdown prevention circuit II is configured as shown on the left side of FIG. That is, MISFET
Qc is a pair of n ⁺ type semiconductor regions used as the gate insulating film 4, the gate electrode 7, and the source region or the drain region.
It consists of 10.

The field effect transistor Qm, which serves as a memory cell, is configured as shown in the central portion of FIG. That is, the field effect transistor Qm includes a pair of n ⁺ type semiconductor regions used as the first gate insulating film 4, the floating gate electrode 5, the second gate insulating film 6, the control gate electrode 7, and the source or drain region. It consists of 10.

N-channel MISFETQ that forms the internal (peripheral) circuit of EPROM
n is configured as shown on the right side of FIG. That is, the MISFETQn is used as a gate insulating film 4, a gate electrode 5, a pair of n ⁻ type semiconductor regions (LDD portions) 9 used as a source region or a drain region near the channel formation region, and a substantial source region or a drain region. A pair of n ^{+ to} use
The semiconductor region 10 of the mold. This MISFETQn is
It is composed of LDD structures.

As described above, in the MISFET Qn of the EPROM, by forming the n ⁻ type semiconductor region 9 having a low impurity concentration in the vicinity of the channel formation region, the electric field strength in the vicinity of the drain region can be relaxed, so that the generation of hot carriers can be suppressed. As a result, the MISFET Qn can suppress the deterioration of the threshold voltage with time, so that the electrical reliability can be improved.

Further, in the field effect transistor Qm, the vicinity of the channel forming region is constituted by a semiconductor region having a higher impurity concentration than the semiconductor region 9, for example, an n ⁺ type semiconductor region 10,
Since the electric field strength in the vicinity of the drain region can be increased, hot carriers can be easily generated. As a result,
In the field effect transistor Qm, the amount of hot electrons that serve as information increases, so that the information writing efficiency can be improved.

In the MISFET Qc of the electrostatic breakdown prevention circuit II, the sole region or the drain region in the vicinity of the channel formation region is composed of the semiconductor region 10 having the same high impurity concentration as the field effect transistor Qm. By thus configuring the MISFET Qc, the resistance value in the current path of the overcurrent is reduced, and the semiconductor region 10 in the avalanche breakdown state is reduced.
Can suppress the heat generation. Therefore, thermal destruction at the pn junction between the semiconductor region 10 and the semiconductor substrate 1 can be prevented. Also,
Since the avalanche breakdown voltage can be reduced and the electric field applied between the semiconductor region 10 and the semiconductor substrate 1 can be weakened, electric field breakdown at the pn junction can be prevented. As a result, an electrostatic breakdown prevention circuit against electrostatic breakdown
The electrical reliability of II can be improved.

In FIG. 2, reference numeral 8 denotes an insulating film that covers the gate electrodes 5 and 7, and is mainly configured to increase the withstand voltage of the end portions of the gate insulating films 4 and 6. Reference numeral 8A is a mask for introducing impurities, which constitutes a semiconductor region 10 which becomes a substantial source region or drain region of the LDD structure MISFET.

Reference numeral 11 is an insulating film that covers the semiconductor element, and 12 is a connection hole. Reference numeral 13 denotes a conductive layer such as an aluminum film, which is configured to be electrically connected to a predetermined semiconductor region 10 through the connection hole 12.

Next, the third embodiment of the method for manufacturing the EPROM, which is Embodiment I of the present invention, will be described.
FIG. 4 is a cross-sectional view of an essential part in each manufacturing process of FIGS.

First, the field insulating film 2, the channel stopper region 3 and the gate insulating film 4 are formed on the semiconductor substrate 1.

After that, a first-layer polycrystalline silicon film is formed on the entire surface,
The conductive layer 5B is formed by performing a predetermined patterning on the polycrystalline silicon film in the field effect transistor Qm and MISFET Qc forming regions. In the same manufacturing process as this conductive layer 5B, the polycrystalline silicon film in the MISFET Qn forming region is patterned to form the gate electrode 5.

Then, the insulating film 8 made of a silicon oxide film formed by a thermal oxidation technique is formed mainly in order to increase the withstand voltage of the end portion of the gate insulating film 4.

After that, as shown in FIG. 3, an n ⁻ type semiconductor region 9 is formed in the main surface portion of the semiconductor substrate 1 in the MISFET Qn formation region in order to form an LDD portion having an LDD structure. The semiconductor region 9 is
For example, phosphorus of about 1 × 10 ¹³ [atoms / cm ² ] is formed by introducing it through the gate insulating film 4 by an ion implantation technique.

After the step of forming the semiconductor region 9 shown in FIG.
Impurity introducing masks 8A are formed on both sides of the gate electrode 5 in the ETQn formation region.

After that, the gate insulating film 6 is formed so as to cover the conductive layer 5B in the field effect transistor Qm and MISFET Qc forming region, and the second-layer polycrystalline silicon film is formed in this region. Then, the second-layer polycrystalline silicon film and the conductive layer 5B are patterned to form the floating gate electrode 5 and the control gate electrode 7.

The floating gate electrode is formed on the same layer as the control gate electrode (not shown in FIG. 5) by removing the control gate electrode of the MISFETQc at the same time when patterning to form the gate electrode or the wiring layer of the peripheral circuit portion. Of the gate electrode 5. next,
As shown in FIG. 4, an insulating film 8 made of silicon oxide formed by a thermal oxidation technique is formed mainly in order to increase the withstand voltage at the end portions of the gate insulating films 4 and 6.

After the step of forming the insulating film 8 shown in FIG. 4, mainly using the field insulating film 2, the gate electrodes 5 and 7 and the impurity introduction mask 8A as a mask, an n-type impurity for forming a source region or a drain region is formed. Is introduced over the entire surface. In the step of introducing the n-type impurity, as shown in FIG.
The n ⁺ type semiconductor region 10 is formed, and the MISFET Qc, the field effect transistor Qm, and the MISFET Qn are formed. Semiconductor area 10
Is formed by introducing arsenic of about 1 × 10 ¹⁶ [atoms / cm ² ] through the insulating film 8 by an ion implantation technique.

In this way, since the MISFET Qc is formed in substantially the same manufacturing process as the field effect transistor Qm serving as the memory cell, the manufacturing process of the electrostatic breakdown prevention circuit II can be reduced. In addition, the protective resistance element R of the electrostatic breakdown prevention circuit II is formed by the step of forming the first-layer or second-layer polycrystalline silicon film or the semiconductor region 10.
Are formed in the same manufacturing process as the process for forming.

After the step of forming the semiconductor region 10 shown in FIG. 5, the insulating film 11, the contact hole 12 and the conductive layer 13 are formed to complete the EPROM of the present Example I.

In the present invention, a high melting point metal film, a high melting point metal silicide film or a polycide film may be used as the gate electrodes 5 and 7.

Example II

This Example II is for clamping like the MISFET of the internal circuit.
It is another embodiment of the present invention in which the MISFET and the field effect transistor of the memory cell have an LDD structure.

Example II of the present invention, MIS for clamping the input part of EPROM
The FET, the field effect transistor of the memory cell, and the MISFET of the internal circuit are shown in a sectional view of the main part of FIG.

The MISFET Qc and the field effect transistor Qm of the present Example II are
The source region or the drain region of the channel forming region is composed of the n-type semiconductor region 14 (LDD portion) having a low impurity concentration. The semiconductor region 14 has a higher impurity concentration than that of the semiconductor region 9 of the MISFET Qn of the internal circuit, for example, 1 × 10 5.
Arsenic of about ¹⁵ [atoms / cm ² ] is introduced through the gate insulating film 4 by the ion implantation technique.

As described above, by configuring the LDD portion of the field effect transistor Qm having the LDD structure with the semiconductor region 14 having an impurity concentration higher than that of the semiconductor region 9 of the MISFET Qn, it is possible to obtain substantially the same effect as that of the first embodiment. .

By configuring the MISFET Qc with the same structure as the source region or the drain region in the vicinity of the channel region of the field effect transistor Qm having the LDD structure, it is possible to obtain substantially the same effect as that of the embodiment I.

Furthermore, the MISFET Qc and the field effect transistor Qm are LDD
Since it is structured, the short channel effect and the like can be suppressed.

Next, a method of manufacturing an EPROM which is Embodiment II of the present invention will be described with reference to FIGS.

First, the gate insulating films 4 and 6, the floating gate electrode 5, and the control gate electrode 7 are formed in the MISFET Qc and field effect transistor Qm formation regions. The gate insulating film 6 and the gate electrode 7 are formed in the MISFET Qn forming region by the same manufacturing process as the process of forming the gate insulating film 6 and the control gate electrode 7. At this time, the floating gate electrode 5 is used as the gate electrode 5 of the MISFET Qc by simultaneously removing the control gate electrode 7 of the MISFET Qc.

After that, the insulating film 8 is formed in the same manner as in Example I.

Then, the LDD structure MISFET Qc and the field effect transistor Q
In order to form m, as shown in FIG. 8, an n-type semiconductor region 14 serving as an LDD portion is formed.

After the step of forming the semiconductor region 14 shown in FIG.
In order to form the MISFET Qn having the structure, as shown in FIG. 8, an n ⁻ type semiconductor region 9 to be an LDD portion is formed.

After the step of forming the semiconductor region 9 shown in FIG.
In order to form a substantial source region or drain region of the ETQc, the field effect transistor Qm and the MISFET Qn, an n ⁺ type semiconductor region 10 is formed as shown in FIG. These semiconductor regions 14, 9, 10 can be formed by introducing impurities by an ion implantation technique.

In the process of forming the semiconductor region 10, the MISFET Qc, the field effect transistor Qm and the MISFET Qn are formed.

After processing the semiconductor region 10 shown in FIG.
By forming the connection hole 12 and the conductive layer 13, the EPROM of the present Example II is completed.

In this embodiment, the diffusion layer region was formed after the gate electrodes of MISFETQc, Qm, Qn were processed, but the semiconductor region 14 was formed after the gate electrode of MISFETQc, Qm was processed, and then the MISFET was formed.
After processing the gate electrode of Qn, the control gate electrode of MISFET Qc may be removed at the same time, and then the semiconductor region 9 of MISFET Qn may be formed.

As described above, according to the novel technology disclosed in the present application, the effects described below can be obtained.

(1) In an EPROM, a field effect transistor of a memory cell is configured with an impurity concentration higher than that of an LDD portion of an LDD structure field effect transistor, and a MISFET for clamping of an electrostatic discharge prevention circuit is used as a channel of the field effect transistor of the memory cell. By using a field effect transistor having the same structure as the source region or the drain region near the region,
The internal circuit can suppress the fluctuation of the threshold voltage due to hot carriers in the MISFET having the LDD structure, so that the electrical reliability can be improved.

(2) Because of the above (1), the clamp MISFET of the electrostatic breakdown prevention circuit can reduce the resistance value of the portion where the excessive current flows to prevent thermal breakdown, and can lower the breakdown voltage to prevent electric field breakdown. The electrostatic breakdown voltage can be improved.

(3) Due to the above (1) and (2), it is possible to improve electrical reliability and electrostatic breakdown voltage.

(4) According to the above (1), the clamp MISFET can be formed in substantially the same manufacturing process as the field effect transistor of the memory cell, so that the manufacturing process for forming the electrostatic breakdown prevention circuit can be reduced.

Although the invention made by the present inventor has been specifically described based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

For example, the present invention may be applied to the output stage of EPROM.
Specifically, the MISFET of the output stage circuit whose drain region is connected to the external output terminal has the same structure as the field effect transistor of the memory cell.

Further, in the above-described embodiment, the gate electrode of the MISFET for clamping is formed in the same layer as the floating gate electrode of the MISFET of the memory cell, but it may be formed in the same layer as the control gate electrode or may be formed in a different layer. Good.

In addition, although the present invention is applied to the semiconductor integrated circuit device having the LDD structure MISFET in the above-described embodiment, the present invention is directed to a double drain including a semiconductor region having a high impurity concentration and a semiconductor region having a low impurity concentration. It may be applied to a semiconductor integrated circuit device having a MISFET having a configuration.

The present invention can also be applied to a microcomputer chip having an EPROM on the same semiconductor substrate.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

Since the MISFET of the electrostatic breakdown prevention circuit is formed in substantially the same process as the transistor of the memory cell, a semiconductor integrated circuit device having a favorable breakdown voltage can be obtained.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an input portion of an EPROM which is Embodiment I of the present invention, FIG. 2 is a sectional view of a main portion of the EPROM of Embodiment I of the present invention, and FIGS. Example I of the present invention EPROM is a cross-sectional view of an essential part in each manufacturing step of the EPROM, FIG. 6 is a cross-sectional view of the essential part of an EPROM of Example II of the present invention, and FIGS. FIG. 9 is a cross-sectional view of essential parts in each manufacturing process of an EPROM that is Example II. In the figure, BP: external input terminal, I: input stage circuit, II:
Electrostatic breakdown prevention circuit, Qn, Qp …… MISFET, Qc …… Clamping MISFET, Qm …… Field effect transistor, R, 1 …… Semiconductor substrate, 4,6 …… Gate insulating film, 5,7 …… Gate electrode ,
9,10,14 …… Semiconductor area.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (1)

[Claims] 1. A first field effect transistor constituting a memory cell having a gate electrode structure comprising a floating gate electrode and a control gate electrode located above the floating gate electrode, and the gate electrode structure of the memory cell. A semiconductor integrated circuit device in which a first and a second field effect transistor having different gate electrode structures are provided on a single semiconductor substrate, and channels of the first, second and third field effect transistors are formed. The region in contact with the region has an LDD structure, and the LDD portions of the first and third field effect transistors have a higher impurity concentration than that of the LDD portion of the second field effect transistor. In the field effect transistor of, the drain region is connected to the external terminal, and the source region and the gate electrode are the reference voltage. It is connected to the semiconductor integrated circuit device, characterized in that it forms a clamping field effect transistor.