JPH0797750B2 - Sequential decoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a sequential decoding method for converting a binary digital data sequence into a signal sequence suitable for magnetic recording or optical recording.

(Prior Art) When information represented by a binary digital data string is to be recorded on a magnetic recording medium such as a magnetic tape or a magnetic disk, the binary digital data string is converted into a signal sequence suitable for magnetic recording. Is done. As a condition required for such conversion into a signal sequence, when the magnetization reversal interval (recording wavelength) of the magnetic recording medium becomes short, interference from the previous and subsequent magnetization reversals causes an increase in detection error.
The minimum magnetization reversal interval is large, the detection window width for detecting the recording bit is large, and the magnetization reversal interval is larger than the period of the demodulation clock signal. However, since it becomes more difficult to generate a demodulation clock signal than a reproduction signal, the maximum magnetization reversal interval must be reduced. These conditions are contradictory to each other and must be optimized to maximize the data recording density on the magnetic recording medium. T.
Horiguchi and K. Morita's paper “An Optimiyation of Mo
dnlation Codes in Digital Recording ″, IEEE Taansa
ctions on Magnetics, Vo1.MAG-12.No.6, Nov.1976, P.
The 740 converts the 2-bit unconstrained data word into a 3-bit constrained codeword to determine the minimum number of "0s" between adjacent "1s" in the codeword sequence d.
There is disclosed a coding / decoding system with a code rate of 2/3, in which the maximum number k of "0" s between adjacent "1" s is 7. However, the coding / decoding method disclosed in the above-mentioned paper is a variable length coding / decoding method in which the data word is 2 bits and 4 bits, and has a drawback that a device for performing the conversion becomes complicated.

Japanese Patent Laid-Open No. 58-212248 discloses an encoding / decoding device capable of sequentially performing conversion in the variable length coding / decoding system. Table 1 shows a conversion table of the encoding / decoding method of the code rate 2/3 adopted in the encoding device and the decoding device in the above patent.

In Table 1, the left column labeled "Data Word" indicates a set of data bits separated from the data string, and the right column labeled "Code Word" indicates a corresponding set of converted code bits. The converted codeword sequence is recorded as magnetization reversal on the magnetic recording medium by reversing the recording signal when the code bit is "1". In Table 1, a lower case "x" in a codeword indicates a bit that becomes "1" or "0" depending on the last bit of the previous codeword, and represents the complement of the previous bit. A decoding device of such an encoding system can be realized by a circuit as shown in FIG. 2 shown in the above patent. The decoding circuit of FIG. 2 is a sequential decoding circuit that outputs 2 bits of data for every 3 bits of a codeword string, and FIG. 3 is a diagram showing waveforms and timings of clocks and control signals.
The code word string is input to the serial input / parallel output shift register 20 in synchronization with the clock B, and is shifted by the clock B. The parallel output of the four stages of the shift register 20 is the AND circuits 211 to 213 and the OR circuit 21.
The code is converted by the logic circuit 21 composed of 4,215 and loaded in parallel to the parallel input shift register 23 operated by the clock A and the load signal. The load operation of the shift register 23 is such that the outputs Ai, Bi, C of the logic circuit 21 are generated when the clock A signal rises when the load signal is at a high level.
This is done by loading i and Di in parallel. When the load signal is low level, the shift register 23 performs a shift operation. The logic circuit 21 performs a logical operation for decoding the code word shown in Table 1 to decode a data word from a code word. It sequentially converts every 3 bits of code bit into 2 bits of data, and sequentially. A code Ci representing the word length for decoding and a code Di for storing the second code bit in the case of a 6-bit long codeword are output. That is, when the data word length is 4 bits, that is, when the code word length is 6 bits, the leading 3 bits are copied. Ci = only when converting the data bit to 2-bit data
If it is 1, Table 1 can be written as shown in Table 2 using Ci ⁻¹ that is 2 bits before the data bit, so Ci ⁻¹ and data bit is 2
With Di ^-1 before bit and code bit XYZW,
The data bits Ai and Bi, the code Ci representing the word length, and the code bit Di to be stored are calculated as follows.

Ci ^-1 and Di ^-1 are data bits and represent the code two bits before. When the load signal is at a high level and the clock A rises, Ci ^-1 is in the B stage of the shift register 23, and Di ^-1 is It is stored in the C stage of the shift register 23. Therefore, the logic circuit 21 is a circuit for realizing the logical operation expression (1). By connecting the AND circuits 211 to 213 and the OR circuits 214 and 215 like the logic circuit 21 of FIG. To be executed. However, in the conventional decoding circuit of FIG. 2 which realizes the decoding device of the encoding / decoding system of Table 1, an extra register for calculating and storing the code representing the word length and the like is required, and the circuit scale is extremely large. There was a drawback that it was large (a) complicated.

(Problems to be Solved by the Invention) As described above, when the encoding / decoding system shown in Table 1 is used to implement this system as a circuit, there is a drawback that the configuration becomes large and complicated. That is, the code conversion as shown in Table 1 above was not suitable for realizing the device. So, this invention
The present invention has been made in view of such circumstances, and an object thereof is to provide a successive decoding method with a small circuit scale that can be used in a decoding device in the variable length coding and decoding system. It is in.

[Structure of Invention]

(Means for Solving the Problems) In the present invention, a binary data string is obtained by removing (0,0) or (1,1) data words selected from four types of 2-bit length data words. The two types of 2-bit length data words and the four types of 4-bit length data words whose upper bits are the 2-bit length data words removed from the selection are divided into the first and second of the three types of 2-bit length data words. A bit
Corresponding to three kinds of 3-bit length codewords which are the same as or complementary to the second and third bits, respectively,
Corresponding to 4 types of 6-bit length data words, the 3rd and 4th bits of the 4 types of 4-bit length data words are the same as or complementary to the 2nd and 6th bits of the codeword, respectively. , The binary data string is converted to a codeword string, and the converted codeword string is converted to 6
When a bit-length codeword is detected, the second bit of the 6-bit length codeword is copied to the fifth bit of the 6-bit length codeword, and every 3-bit code bit of the converted codeword string is copied. Based on the 1-bit value following the 3 bits of the codeword string, the 3-bit code bits of the codeword string are converted into 2-bit data bits, and the converted 2-bit data bits are coded. The sequential decoding method is characterized by outputting a word string as the binary data string and outputting the word string as the binary data string.

(Operation) In the present invention, a binary data string is excluded from three kinds of 2-bit length data words except selection of (0,0) or (1,1) data words selected from four kinds of data words and selection. Burnt 2
The bit length data is divided into four types of 4-bit length data words having upper bits, and the first and second bits of the three types of 2-bit length data words are the same as the second and third bits of the 3-bit length code word, respectively. Or correspond to be the complement. Further, variable length coding and decoding in which the third and fourth bits of the four types of 4-bit length data words are made to be the same as or complementary to the second and sixth bits of the 6-bit length code word, respectively. This is a decoding method for converting a codeword string used in the method into a data string. If the input codeword is detected to be a 6-bit long codeword, the fifth bit of the 6-bit long codeword is replaced with the second bit of the 6-bit long codeword to determine the word length. The register for storing the sign or the like can be dispensed with, and the circuit scale can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a decoding circuit according to the present invention,
Basically, it comprises a D flip-flop 10, a shift register 11, OR circuits 12, 13, 14 AND circuits 15, 16 and a parallel input shift register 17. Table 3 is a conversion table showing the correspondence between codewords and data words that are decoded by the decoding circuit. When decoding a 6-bit long codeword, the first 3 bits of the code bit are converted into 2 bits. Converting the 5th bit of the codeword to the 2nd bit by itself while converting the 5th bit of the codeword to the 2nd data bit, and then converting the latter 3 bits of the code bit to 2 bits of the data bit. Is represented.

The decoding circuit of FIG. 1 is a sequential decoding circuit that outputs 2 bits of data for every 3 bits of a codeword string,
Similar to the conventional example of FIG. 2, it operates in timing relationship with the control signal and clock signal waveforms shown in FIG. The code word string is synchronized with the clock B and the D flip-flop 10
Is input to the OR circuit 12 together with the clock B.
Via a serial input and parallel output shift register 11 operated by clock B. The output of the D flip-flop 10 and the parallel output of three stages of the shift register 11 are logically operated on the data bits by the OR circuits 13 and 14 and the AND circuit 15, and the parallel input shift register is operated by the clock A and the load signal. When the load signal is high level, a specific pattern is detected from the output of the D flip-flop 10 and the parallel output of the shift register 11 when the word length of the code word is 6 bits. The circuit 16 and the OR circuit 12 cause the second bit of the 6-bit long codeword stored in the X stage of the shift register 11 to be the fifth bit of the 6-bit long codeword stored in the w stage of the shift register 11. It is input to the Z stage of the shift register 11 instead of the bit. The load operation of the shift register 17 is performed by loading the data bits which have been logically operated in parallel at the rising edge of the clock A when the load signal is at the high level. When the load signal is low level, shift register
17 performs shift operation. Therefore, in the code conversion according to the present embodiment, for the first 3 bits of the 3-bit length codeword and the 6-bit length codeword, the 3-bit code bits of the codeword before the modification are converted into 2-bit data bits. D flip-flop 10 and shift register for the latter 3 bits of the 6-bit long codeword
It detects that the code bit stored in 11 is a specific pattern, modifies the 5th bit of the 6-bit codeword, and modifies the latter 3 bits of the modified codeword to 2 data bits. It is a sequential decoding circuit adapted to convert to. From Table 3, the data bits Aj and Bj and the input Zj of the shift register 11 for correcting the codeword are calculated as follows with the load signal being L.

Therefore, in the logical operation for executing the equation (2), the output of the D flip-flop 10 and the outputs of the Y and Z stages of the shift register 11 are input to the AND circuit 15, and the output of the AND circuit 15 and the X of the shift register 11 are input. The Q output of the stage is input to the OR circuit 13, the output of the OR circuit 13 is set to Aj, the output of the AND circuit 15 and the Q output of the Y stage of the shift register 11 are input to the OR circuit 14, and the OR circuit is input. By setting the output of 14 to Bj, the load is loaded in parallel to the shift register 17, and the Q output of the X stage, the output of the Y stage and the output of the Z stage of the shift register 11 and the load signal are input to the AND circuit 16. , And the output of the AND circuit 16 and the Q output of the flip-flop are input to the OR circuit 12, and the output of the OR circuit 12 is set to Zj which is added to the input of the shift register 11.

That is, the decoding circuit shown in FIG. 1 can reduce the number of stages of the shift register as compared with the conventional decoding circuit by correcting and decoding the 6-bit long codeword.

As described above, the decoding circuit according to the present embodiment uses the modified codewords shown in Table 3 to sequentially decode 2 data bits for every 3 bit code bits from the codeword string. Since the register for storing the code representing the word length can be dispensed with, the structure of the decoding circuit can be simplified. Therefore, its practical advantages are enormous. The present invention is not limited to the above embodiment. For example, it goes without saying that the code conversion may be performed after each bit of the codeword string is complemented (the codeword string is inverted). At this time, the Q output connected to the AND circuits 15 and 16 and the OR circuits 12 to 14 from the D flip-flop 10 and the shift register 11 of the decoding circuit of FIG. In addition, the OR circuit 12 may be a NOR circuit. Also (2)
Although the AND circuit and the OR circuit are combined to perform the logical operation of the expression, it is needless to say that the NAND circuit and the NOR circuit may be combined, and the correspondence between the code word and the data word in Table 3 is When the bit is made to correspond to its complement, the output of the decoding circuit in FIG. 1 may be inverted. In short, the present invention can be implemented with various modifications without departing from the scope of the invention.

〔The invention's effect〕

According to the present invention, the register for storing the code representing the word length of the decoding circuit can be omitted, the scale of the circuit can be reduced, and the number of gates for integration can be reduced. Becomes

[Brief description of drawings]

1 is a decoding circuit according to an embodiment of the present invention, FIG. 2 is a conventional decoding circuit, and FIG. 3 is a conventional decoding circuit and a decoding circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of waveforms and timings of clocks and control signals to be performed. 10 …… D flip-flop, 11,20 …… Serial input parallel output shift register, 12,13,14,214,215 …… OR circuit, 15,16,211,212,213 …… AND circuit, 17,23 …… Parallel input shift register

Claims (1)

[Claims] 1. A binary data string comprising three types of 2-bit length data words excluding (0,0) or (1,1) data words selected from four types of 2-bit length data words, and The 2-bit length data removed from the selection is divided into four types of 4-bit length data words having upper bits, and the first and second bits of the three types of 2-bit length data words are the second and third bits, respectively. Corresponding to three types of 3-bit length codewords that are the same as or complementary to the bits, the third and fourth bits of the four types of 4-bit length data words are respectively the second and sixth bits of the codeword.
Converting the binary data string into a codeword string in correspondence with four types of 6-bit length data words that are the same as or complementary to the bits, and convert the converted codeword string to a 6-bit length codeword Is detected, the second bit of the 6-bit length codeword is copied to the fifth bit of the 6-bit length codeword, and the code is converted for every 3 bits of the converted codeword sequence. The 3-bit code bit of the codeword string is converted into 2-bit data bit based on the 1-bit value following the 3-bit word string, and the converted 2-bit data bit is converted into the codeword string. A sequential decoding method characterized by outputting as a binary data string.