JPH0797767B2 - Image information receiving device - Google Patents

Description

The present invention relates to an apparatus for receiving image information according to an HDLC (High-level Data Link Control) procedure, and more particularly to an image receiving apparatus having an error resend request function. Is.

[Conventional technology]

As a conventionally known apparatus of this type, a facsimile apparatus having an error resend request function is known. Since this facsimile apparatus receives HDLC-formatted image information, if a reception error occurs even with 1 bit, the frame is determined as an error frame.

When such error frame remains even if the error is retransmitted several times from the transmitting side, for example, the error frame is not reproduced and the preceding and following frames are packed and reproduced: An error frame occurs. The operator is informed of specific information that indicates that:

As described above, in the conventional facsimile device, the error frame information is not reproduced at all.

[Problems to be solved by the invention]

However, when the error bit number contained in the error frame is small, most of the line information can be reproduced by decoding the received signal of the frame and printing out only the correctly received line information. It is possible.

As described above, the conventional facsimile apparatus has a drawback that the image information included in the error frame is uniformly ignored or removed.

Therefore, it is an object of the present invention to, when an error occurs in a frame received in the error resending mode, also decode the image information in the error frame and reproduce the normal image information in the error frame. To provide a device.

[Means for solving problems]

In order to achieve such an object, the present invention is a receiving means for receiving a series of image information divided into a plurality of frames,
When the received frame has an error, means for making an error resend request to the transmitting side, storage means for storing the received image information, and decoding means for decoding the image information stored in the storage means, It has a reproducing means for reproducing the image information decoded by the decoding means, and a means for storing the image information of the normally received frame and the image information of the erroneous frame in the storage means.

[Action]

In the image receiving apparatus according to the present invention, although error resending is requested on a frame-by-frame basis, image information of a normally received frame and image information of an erroneous frame are stored in a storage unit and stored in the storage unit. The image information is decoded and reproduced.

〔Example〕

 Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is an overall configuration diagram of an image information receiving apparatus according to the present invention. As shown in the figure, in the device for receiving the image information according to the HDLC procedure, when the received image information has an error, a means for making an error retransmission request to the transmitting side,
The apparatus further comprises means for reproducing the correctly received image information component of the image information when the reception error is not eliminated even when the error resending request is made a predetermined number of times.

Next, an outline of a facsimile apparatus to which the present invention is applied will be described.

Among the facsimile machines to which the present invention is applied, in the facsimile machine on the transmission side (hereinafter, simply referred to as “transmitter side”), the encoded image information is divided into predetermined lengths, which are HDLC-formatted as one frame, Send multiple frames at once (for example, send 256 frames). In the facsimile machine on the receiving side (hereinafter, simply referred to as "receiver side"), after the reception of a plurality of frames (for example, 256 frames) is completed, the number of the frame having the reception error is transmitted to the transmitter side. The transmitter side retransmits the erroneous frame. Then, when the error frame has disappeared on the receiver side, information to that effect is transmitted to the transmitter side. Then, the transmitter side transmits the next block. Note that, even after the transmitter has retransmitted three times, if the receiver still has an error frame, the frame may be retransmitted or the frame may be retransmitted and the next frame may be interrupted. The transmitter determines whether to transmit the block.

The general operation of the receiver side is as follows.

On the receiver side, first, the data is stored in the temporary buffer, the frame number is identified when the data for one frame is correctly received, and the data is transferred to the corresponding image memory space. Then, as long as the image data is continuously and correctly received, the image reproducing operation is sequentially performed. Also,
When it is recognized that there is an error in the CRC check, the frame data is stored in the temporary buffer and the data is transferred to the corresponding image memory space.
This is the feature of this embodiment, and even if an error frame remains until the end, the frame data can be decoded and reproduced. This makes it possible to reproduce (visualize) most line information when there are few errors contained in the frame data.

FIG. 2 is a block diagram showing the above-mentioned facsimile apparatus.

In FIG. 2, 2 is a network control unit NCU (Network Control Unit),
In order to use the telephone network for data communication, etc., it is connected to the rotating terminal to control the connection of the telephone exchange network and switch to the data communication path. The signal line 2a is a telephone line. The NCU 2 inputs the signal of the signal line 36a, and when the signal level is "0", the telephone line 2a is connected to the telephone side (that is, the signal line 2a is the signal line 2b). Further, the NCU 2 inputs the signal of the signal line 36a, and when the signal level is "1", the telephone line 2a is connected to the facsimile machine side (that is, the signal line 2a is the signal line 2c). In a normal state, the telephone line 2a is connected to the telephone side.

Reference numeral 4 is a telephone.

Reference numeral 6 is a hybrid circuit for separating a transmission system signal and a reception system signal. That is, the transmission signal on the signal line 20a is sent to the telephone line 2a via the signal line 2c and NCU2. The signal sent from the communication partner is output to the signal line 6a via the NCU2 and the signal line 2c.

Reference numeral 8 denotes a reading circuit which sequentially reads image signals for one line in the main scanning direction from a transmission document and creates a signal string representing binary values of white or black. The reading circuit 8 inputs a signal output from an image pickup device (not shown) such as a CCD (charge coupled device), and outputs a binarized signal string representing white or black to a signal line 8a. .

Reference numeral 10 is an encoding circuit, which inputs the data output to the signal line 8a and performs MH (Modified Huffman) encoding,
Alternatively, MR (Modified Read) encoded data is output to the signal line 10a.

Reference numeral 12 is a memory circuit that stores the data output to the signal line 10a. Since the present facsimile apparatus transmits a plurality of pieces of frame information once as one block and then retransmits a frame in which an error has occurred, it is necessary to have a memory for at least one block. This memory circuit
When the frame number information to be transmitted is output to the signal line 36c, the 12 outputs the image information of the frame to the signal line 12a.

Reference numeral 14 is an HDLC circuit, which adds an address field, a control field, an FCF field, and a FIF field (where the current frame number being transmitted is stored) before the encoded data output to the signal line 12a. , HDLC format and output to the signal line 14a. This HDLC circuit 14
Also outputs a flag for control on the transmitter side to the signal line 14a when the signal of the signal level "1" is output to the signal line 34d.

Reference numeral 16 is a modulator that performs modulation based on the well-known CCITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation). The modulator 16 receives the signal on the signal line 14a, modulates the signal, and outputs the modulated data to the signal line 16a.

Reference numeral 18 is a modulator that performs modulation based on the well-known CCITT recommendation V21. The modulator 18 receives the procedure signal on the signal line 36b, modulates the procedure signal, and outputs the modulated data to the signal line 18a.

Reference numeral 20 denotes an adder circuit which inputs signals from the signal line 16a and the signal line 18a and outputs the addition result to the signal line 20a.

22 is a demodulator that performs demodulation based on the well-known CCITT recommendation V21. This demodulator 22 receives the signal on the signal line 6a and outputs V2
1 Demodulates and outputs the demodulated data to the signal line 22a.

Reference numeral 24 is a demodulator that performs demodulation based on the well-known CCITT recommendation V27ter (differential phase modulation) or V29 (quadrature modulation). The demodulator 24 receives the signal on the signal line 6a, demodulates it, and outputs the demodulated data to the signal line 24a.

26 receives the demodulated data output to the signal line 24a and inputs HDL
It is a circuit that performs zero delete of the data converted into C and outputs the data before being HDLC formatted to the signal line 26a. Then, when reception of one frame is completed, a pulse is generated on the signal line 26b. When one frame can be correctly received when the pulse is generated on the signal line 26b, a signal of signal level "1" is output to the signal line 26c.
When one pulse is not correctly received when the pulse is generated on the signal line 26b, a signal of signal level "0" is output to the signal line 26c. The circuit 26 generates a pulse on the signal line 26d every time 1-byte data is output to the signal line 26a.

Reference numeral 28 is a temporary memory circuit that temporarily stores the encoded image information output to the signal line 26a. This memory circuit
28 is composed of a temporary buffer 0 and a temporary buffer 1 (neither of which is shown).
It has a memory space of bytes. These temporary buffers 0 and 1 are 1 sent from the communication partner.
Stores data for frames. The maximum data length of one frame is 256 + 4 (4 bytes of A, C, FCF, and frame number are added) bytes. When data is stored in one temporary buffer (data is input from the signal line 26a), data is output from the other temporary buffer (data is output from the signal line 28a). Here, the start address of temporary buffer 0 is TE
Name it MPBF0SFSTA, and name the start address of temporary buffer 1 TEMPBF1SFSTA. Received data is alternately stored in the temporary buffer 0 and the temporary buffer 1.

An image memory circuit 30 has a memory space for storing at least one block of data. The procedure for storing the data temporarily stored in the temporary memory circuit 28 in the image memory circuit 30 will be described later. The image memory circuit 30 sequentially outputs the information of one block stored in the memory to the signal line 30a when the signal of the signal level "1" is output to the signal line 36j.

Reference numeral 32 is a decoding circuit, which inputs the demodulated data output to the signal line 30a when the signal of the signal level "1" is output to the signal line 36j, and performs MH (Modified Huffman) decoding or MR (Modified Read). The decoded data is output to the signal line 32a.

Reference numeral 34 is an image reproduction (visualization) circuit, which is used when the signal level "1" is output to the signal line 36j.
The signal output to the above is input and recording is sequentially performed for each line.

36 is a control circuit for performing the control shown in FIGS. 3 (A) to (C) and FIG. In order to store the data in the temporary buffer 0.1, the control circuit 36 first uses the TEMPBF0SFSTA or T as the storage address on the signal line 36e.
Outputs EMPBF1SFSTA. When 1 byte of data is received (that is, when a pulse is generated on the signal line 26d),
The data output to the signal line 26a is the temporary memory circuit 2
It is input to 8 and stored in the storage address. Then, the control circuit 36 increments the storage address by one. At this time, the control circuit 36 determines whether the number of data of one frame (64 bytes or 256 bytes of image information data, 4 bytes of A, C, FCF, frame number as other additional information) is not exceeded. Always check.

When the reception of one frame of data is completed, it is checked whether or not the data can be correctly received, and when it is correctly received, the value of the frame number is checked. The frame number is stored in the fourth byte from the beginning of the received data of one frame, and this information is output to the signal line 28b. Then, the control circuit 36 sends the transfer start address to the signal line.
Output to 36f. Further, the control circuit 36 outputs the number of transfer bytes to the signal line 36e after instructing the storage start address (which is output to the signal line 36g) to the image memory circuit 30. Then, a transfer instruction pulse is output to the signal line 36h to transfer the data stored in the temporary memory circuit 28 to the corresponding image memory space.

When the reception of one frame of data is completed and the data is not received correctly (when an error is detected by the CRC check), the number of received data included in the frame is checked and the number of predetermined bytes ( For example, 10
If it is less than or equal to (byte), discard the data. The reason is that it is considered that an error often occurs during continuous flag transmission. Also, the data contained in the frame is a predetermined number of bytes or more (for example, 36 bytes or more when the data of one frame is 64 bytes + 4 bytes, 132 bytes or more when the data of one frame is 256 bytes + 4 bytes) If so, the data is sequentially stored in the image memory circuit 30. If the data does not reach the predetermined number of bytes, it may or may not be stored in the image memory circuit 30 (in this embodiment, the data is discarded).

In addition, while receiving one frame, if the number of frames exceeds a predetermined number of data of one frame, the operation of switching the temporary buffer to be stored is performed, and the stored data is displayed as an image. Transfer to the memory circuit 30.

In this way, the data is stored once in the temporary buffer, and the frame having no error is transferred to the corresponding image memory space, and even if there is an error in the frame if the number of bytes is equal to or more than that, the data is handled. Store in the image memory space. As a result, even when the error frame remains to the end, the data of the frame can be decoded and reproduced (visualized).

3 (A) to 3 (C) and FIG. 4 are control circuits.
36 is a flowchart showing a control procedure to be executed by 36. Here, FIGS. 3A to 3C are main routines, and FIG. 4 is an interacting routine for storing image signals.

Step S40 represents "start of processing".

In step S42, the signal level "0" is applied to the signal line 36a.
Signal is output and the telephone line is connected to the telephone side. The so-called "CML (Connect Modem to Line) off" is set.

In step S44, it is determined whether facsimile reception is selected. When the facsimile reception is selected, the process proceeds to step S48. If the facsimile reception is not selected, the process proceeds to step S46.

In step S46, other processing is performed.

In step S48, the signal level "1" is applied to the signal line 36a.
Signal is output and the telephone line is connected to the facsimile machine side (CML on).

In step S50, the pre-procedure is executed.

In step S52, it is determined whether or not the reception in the error retransmission mode is selected. When the reception in the error retransmission mode is selected, the process proceeds to step S58. If the reception in the error retransmission mode is not selected, the process proceeds to step S54.

In step S54, the image signal is received regardless of the error retransmission mode.

In step S56, a post procedure is performed.

In step S58, "0" is set to the flag indicating whether or not the transmission of the current block is retransmission. When the retransmission flag is "0", it means that the block transmission is not retransmission, and when the retransmission flag is "1", it means that the block transmission is retransmission.

In step S60, C
If there is an RC error, set TRANSFER BYTE used to store the number of received bytes to "0".

In step S62, "0" is set to the counter BYTECOUNT that counts the number of received bytes included in one frame.

In step S64, a flag TEMPBF1 indicating in which temporary buffer the received data is stored
Set "0" to (temporary buffer in).
When TEMPBFI is "0", the received data is stored in the temporary buffer 0, and when TEMPBFI is "1", the received data is stored in the temporary buffer 1.

When the temporary buffer becomes full, the data stored in the temporary buffer is transferred to the image memory capable of storing one block. In step S66, the data stored in which temporary buffer is transferred to the image memory. "0" is set in the flag TEMPBF0 (temporary buffer out) indicating whether to perform. When TEMPBF0 is "0", it is transferred to the image memory when the temporary buffer 0 is full, and when TEMPBFO is 1, it is transferred to the image memory when the temporary buffer 1 is full.

In step S68, a flag TEMPBF0FULL (temporary buffer 0 full) indicating whether or not temporary buffer 0 is full (that is, whether or not data is stored in the temporary buffer) is set to "0". TEMPBF0FUL
When L is "0", it means that no data is stored in temporary buffer 0, and TEMPBF0FULL is "1".
When it indicates, the data is stored in the temporary buffer 0.

In step S70, a flag TEMPBF1FULL (temporary buffer 1 full) indicating whether or not temporary buffer 1 is full (that is, whether or not data is stored in the temporary buffer) is set to "0". TEMPBF1FUL
When L is "0", it means that data is not stored in the temporary buffer 1, and when TEMPBF1FULL is "1", it means that data is stored in the temporary buffer 1.

In step S71, the start address of temporary buffer 0 is stored in the contents of MODEMPTR.

In step S72, the jump address of FIG. 4 is set as the jump address of the image signal storing interrupt. This interrupt occurs when the end of frame is detected (signal line 26
This is executed when a pulse is generated in b) and when 1 byte of data is input (when a pulse is generated in the signal line 26d).

In step S74, the flag LASTFRMDT is set to "1" when the signal at the end of one block is detected.
Set "0" in (Last Frame Detect).

In step S76, it is determined whether the flag LASTFRMDT is "0" (that is, whether the signal at the end of one block is detected). When the flag LASTFRMDT is "0" (that is, when the signal at the end of one block is not detected), the process proceeds to step S78. Also the flag LASTFRM
When DT is "1" (that is, when the signal at the end of one block is detected), the process proceeds to step S100.

In step S78, it is determined whether TEMPBF0 is "0", that is, whether the next temporary buffer "0" should be transferred to the image memory. When TEMPBF0 is "0", that is, when data is transferred from the temporary buffer 0 to the image memory next, the process proceeds to step S80. When TEMPBF0 is "1", that is, when data is transferred from the temporary buffer 1 to the image memory next, the process proceeds to step S94.

In step S80, whether TEMPBF0FULL is "0",
That is, it is determined whether the temporary buffer 0 is full. When TEMPBF0FULL is "0", that is,
If the temporary buffer 0 is not full, step S7
Go to 6. When TEMPBF0FULL is "1", that is, when the temporary buffer 0 is next full, the process proceeds to step S82.

In step S82, TEMPBF0FULL is set to "0".

In step S84, TEMPBF0 is set to "1".

In step S86, it is determined whether or not there is a CRC error when the storage of one frame is completed. If there is a CRC error, the process proceeds to step S88. If there is no CRC error, the process proceeds to step S92.

In step S88, TRANSFER BYTE is a predetermined number or more (36 bytes or more when one frame of data is 64 bytes, 132 bytes when one frame of data is 256 bytes).
Or more bytes). When the above conditions are met, that is, when a CRC error occurs but more than the specified number of bytes of data is received,
When the above condition is not satisfied, that is, when the CRC error occurs and the data of the predetermined number of bytes or more is not received, the process proceeds to step S90.

In step S90, “4 bytes are subtracted from the number of bytes in TRANSFER BYTE (4 is subtracted because each frame contains 4 bytes of address, control, FCF, frame number)” is stored in the temporary buffer. The transferred 5th byte data is transferred to the image memory (the address after adding “1” to the image memory pointer). Also, the image memory pointer is set to the address where the data is stored at the end.

In addition, at the time of retransmission, that is, when the retransmission flag is “1”, when the image memory pointer reaches the delimiter of one frame, the image memory pointer is set to the head address for storing the data to be retransmitted next, and is correctly received. Prevent the frame data from being destroyed.

In step S92, since one correct frame of data has been received, the frame number is checked, and from the data next to A, C, FCF, and frame number, the number of data in one frame (64 bytes or 256 bytes: Determined) is transferred to the corresponding image memory space. Here, the image memory pointer is set to the address where the data is stored at the end.

At the time of retransmission (when the retransmission flag is “1”), the image memory pointer is set to the head address for storing the frame data to be retransmitted next.

In step S94, whether TEMPBF1FULL is "0",
That is, it is determined whether the temporary buffer 1 is full. When TEMPBF1FULL is "0", that is, when the temporary buffer 1 is not full, step S76
Proceed to. When TEMPBF1FULL is "1", that is, when the temporary buffer 1 is full, the process proceeds to step S96.

In step S96, TEMPBF1FULL is set to "0".

In step S98, TEMPBF0 is set to "0".

In step S100, it is determined whether or not there is an error frame. If there is an error frame, step S1
Go to 02. If there is no error frame, the process proceeds to step S108.

In step S102, a signal instructing the retransmission of the error frame is sent to the transmitter side.

In step S104, it is determined whether it is the fourth retransmission instruction. If it is not the fourth retransmission instruction, an error frame is retransmitted from the transmitter side, and the process proceeds to step S110. If it is the 4th retransmission instruction, "Do you want to retransmit the block you have just sent from the transmitter, or if you want to interrupt the retransmission of the block you have just sent and send the next block if there is a next block?" ”Is sent, the process proceeds to step S106.

In step S106, it is determined whether or not there is an instruction from the transmitter side to retransmit the block that has just been sent.If there is an instruction from the transmitter side to retransmit the block that has just been sent, a response is returned. Send signal, step
Proceed to S108. If there is an instruction from the transmitter side that "the retransmission of the block that has just been sent is interrupted and the next block is sent, the next block is sent", a response signal is sent, and the process proceeds to step S112.

In step S108, the retransmission instruction counter determined in step S104 is cleared.

In step S110, since the retransmission block data is stored, the retransmission flag is set to "1".

In step S112, the image signal is reproduced (visualized).

In step S114, it is determined whether the block is the final block. If it is the final block, step S116
Proceed to. If it is not the final block, the process proceeds to step S126.

In step S116, a post procedure is executed.

In step S118, a signal of signal level "0" is output to the signal line 36a to connect the telephone line to the telephone side (CML off).

In step S120, the image signal is reproduced (visualized).

In step S122, it is determined whether the reproduction of the image signal is completed. When the image signal playback is complete,
Proceed to S42. When the image signal playback is not finished,
It proceeds to step S120.

In step S124, it is determined whether the reproduction of the image signal is completed. When the image signal playback is complete,
Proceed to S126. When the image signal playback is not finished,
Proceed to step S128.

In step S126, an intermediate procedure is performed.

In step S128, control for adjusting the speed between the transmitter and the receiver is performed.

In FIG. 4, step S130 represents "start" of the interlabed routine for image signal reception in the error retransmission mode.

In step S132, it is determined whether or not the final frame has been detected, that is, whether or not a pulse has occurred on the signal line 26b. When the final frame is detected, that is, when a pulse is generated on the signal line 26b, the process proceeds to step S144. When the final frame is not detected, that is, when no pulse is generated on the signal line 26b, step S134
Proceed to.

In step S134, 1-byte data is stored in the address indicated by MODEMPTR.

In step S136, the content of MODEMPTR is incremented by 1.

In step S138, the BYTECOUNT value is incremented by 1.

In step S140, the value of BYTECOUNT is 1
When the data of a frame is 64 bytes, it is determined whether it is 68 bytes, and when the data of one frame is 256 bytes, it is determined whether it is 260 bytes. When the above conditions are met, after setting that a CRC error has occurred,
It proceeds to step S150. When the above conditions are not satisfied, the process proceeds to step S142.

Step S142 represents a return to the main routine.

In step S144, it is determined whether the signal at the end of one block is detected. When the signal at the end of one block is detected, the process proceeds to step S146. When the signal at the end of one block is not detected, the process proceeds to step S150.

In step S146, since the signal at the end of one block has been detected, the LASTFRMDT flag is set to "1".

Step S148 represents a return to the main routine.

In step S150, it is determined whether TEMPBFI is "0", that is, whether data is stored in temporary buffer 0 or not. When TEMPBFI is "0", that is, when data is stored in temporary buffer 0, the process proceeds to step S152. When TEMPBFI is "1", that is, when data is stored in the temporary buffer 1, the process proceeds to step S158.

In step S152, TEMPBI is set to "1" to store the data in the temporary buffer 1 this time.

In step S154, since the data is stored in temporary buffer 0, TEMPBF0FULL is set to "1".

In step S156, the temporary buffer 1 is stored in MODEMPTR to store the data in the temporary buffer 1 next time.
Stores the start address of.

In step S158, "0" is set in TEMPBFI to store data in temporary buffer 0 this time.

In step S160, since the data has been stored in the temporary buffer 1, TEMPBF1FULL is set to "1".

In step S162, the temporary buffer 0 is stored in MODEMPTR to store the data in the temporary buffer 0 next time.
Stores the start address of.

In step S164, it is determined whether or not there is a CRC error. If there is a CRC error, step S166
Proceed to. If there is no CRC error, the process proceeds to step S168.

In step S166, TRANSFER BYTE, BYTECOUNT
Stores the value of.

In step S168, BYTECOUNT is set to "0".

Step S170 represents a return to the main routine.

In the embodiment described above, the image memory on the receiver side has a capacity of one block, but it is also possible to have a capacity of two blocks. In this case, when one block data is stored, the data can be read from another block and recorded (visualized).

It is also possible to record (visualize) a frame having no error in real time.

According to these embodiments, in the facsimile device with an error resending function for transmitting image information in HDLC format, when an error frame remains, the receiver side also stores the information of the error frame in the corresponding storage space. It becomes possible to record (visualize) the line information which is decoded and correctly received as a received image.

Therefore, conventionally, even if there is an error of 1 bit in the frame, all the information included in the frame is treated as an error. However, according to the present embodiment, the correct information included in the error frame is used. It becomes possible to record (visualize) the line information. As a result, if the error frame contains a small number of error bits,
It becomes possible to reproduce most of the line information included in the frame.

[Effects of the Invention] As described above, according to the present invention, the image information in the error frame is also decoded and reproduced together with the image information of the normal frame. Therefore, when some image information in the error frame has an error. However, it is possible to properly reproduce the normal image information of the error frame.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an image information receiving apparatus according to the present invention, FIG. 2 is a block diagram showing an embodiment of a facsimile apparatus to which the present invention is applied, and FIGS. 3 (A) to 3 (C). And FIG. 4 is a flow chart showing a control procedure to be executed by the control circuit 36 shown in FIG. 2 ... NCU, 4 ... phone, 6 ... hybrid circuit,
8 ... reading circuit, 10 ... encoding circuit, 12 ... memory circuit, 14 ... HDLC circuit, 16 ... V27ter or V29 modulator, 18 ... V21 modulator, 20 ... adding circuit, 22 ... V21 demodulator, 24 V27ter or V29 demodulator, 26 circuit for restoring HDLC data, 28 ... temporary memory circuit, 30 ... image memory circuit, 32 ... decoding circuit, 34 ...
… Reproduction (visualization) circuit, 36 …… Control circuit.

Claims (1)

[Claims] 1. A receiving means for receiving a series of image information divided into a plurality of frames, a means for making an error resend request to a transmitting side when the received frame has an error, and the received image information. A storage unit that stores the image information, a decoding unit that decodes the image information stored in the storage unit, a reproduction unit that reproduces the image information decoded by the decoding unit, and an image information and an error of the normally received frame. An image information receiving device, comprising: means for storing the image information of the existing frame in the storage means.