JPH079940B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention mainly relates to a semiconductor integrated circuit device which is automatically designed using an electronic computer.

[Technical background of the invention]

Generally, a so-called building block method is adopted for automatic design of this kind of LSI. For the building block method, for example, IEEE Joural
of Solid-State-Circuits CH1726-9 82 pp.111-11
4,1982, and Japanese Patent Application No. 51-74626 by the present applicant.

A conventional example will be described below with reference to FIGS. Here, FIG. 6 is a view of the entire chip, FIG. 7 is a pattern plan view schematically showing a semiconductor integrated circuit device designed by the building block method, and FIG. 8 is a unit cell of FIG. It is the pattern top view which expanded the inverter circuit (area | region A) as an example.

In FIG. 6, reference numeral 1 denotes a chip in which a plurality of cell row groups 2 ... Are formed. Power is supplied to these cell row groups 2 by two power source lines 3 ₁ and 3 ₂ made of aluminum (Al) at both ends of each cell row.

In FIG. 7, 11 ₁ , 11 ₂ , 11 ₃ ... Are cell rows, and these cell rows 11 ₁ , 11 ₂ , 11 ₃ ... are two Al power lines (parallel to the longitudinal direction of the cell rows). Hereinafter referred to as the first power line) 12
It is sandwiched between ₁ and 12 ₂ . Where one power line 12
_One is connected to the power supply line 3 ₁ , and the other power supply line 12 ₂ is connected to the power supply line 3 ₂ . The cell rows 11 _1, 11 _2, 11 ₃ ... between the respective cell rows region (channel region) 13 has become _1, 13 ₂ and so on. The cell row is composed of unit cells 11a, 11b, ... As logic circuit blocks that house certain functional circuits. The wiring between these unit cells 11a, 11b ...
This is mainly performed through the channel regions 13 ₁ , 13 ₂ ... In the figure, 14 is the first layer Al wiring provided in the channel region in parallel with the longitudinal direction of the cell row, and 15 is provided in the channel region and the cell row in a direction orthogonal to the longitudinal direction of the cell row. The second layer is an Al wiring, 16 is a wiring made of polycrystalline silicon (hereinafter referred to as polysilicon wiring) provided in the channel region and the cell row in a direction orthogonal to the longitudinal direction of the cell row, and 17 is a Reference numeral 18 denotes a via contact hole connected to the first-layer and second-layer Al wirings 14 and 15, and 18 denotes a contact hole connected to the first-layer Al wiring 14 and the polysilicon wiring 16.

In FIG. 8, 19 is a high-concentration impurity region provided on the surface of a semiconductor substrate (not shown), and a contact hole 20
And is electrically connected to the Al power source line 12 ₁ (or 12 ₂ ) via the. Reference numeral 21 denotes a polysilicon wiring used as an input, and 22 denotes an Al wiring of the second layer used as an output.

By the way, in the semiconductor integrated circuit device having the above-described configuration, the second layer Al wiring is used for the through wiring which crosses the cell row, and the unit cell is excluded except for the area where the second layer Al wiring is used in the unit cell. Passing above. Further, the center line of each wiring and the origin of generation of the cell are located on the unit grid, and the size (pitch) of the unit grid is not necessarily the same for the first and second Al wirings and the polysilicon wirings.

[Technical background of the invention]

However, according to the conventional technique, there are the following problems.

That is, when the circuit is designed according to the method shown in FIG. 7, the power source is the power source line 3 ₁ , 3 ₂ and the power source line 1 from both ends of the cell rows 11 ₁ , 11 ₂ , 11 ₃ .
It will be supplied via 2 ₁ , 12 ₂ . Therefore, the circuit scale becomes large, or cell rows are restricted due to restrictions on the overall shape.
As the length of 11 ₁ , 11 ₂ , 11 ₃ ... becomes longer, naturally the power supply lines 12 ₁ , 12 ₂ passing through the cell rows also become longer, and the correct voltage level can be given to the unit cells 11a, 11b ... by their wiring resistance. Disappear. As a result, a voltage drop occurs in the cell row direction, and the unit cells 11a, 11b ... Do not function properly.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device which can prevent a voltage drop in the cell row direction by giving a correct voltage level to a unit cell.

[Outline of Invention]

The present invention relates to a semiconductor substrate having a high-concentration impurity region of the first conductivity type and a second conductivity type on the surface, and a plurality of cells formed by a plurality of unit cells provided on the substrate and containing a certain functional circuit. A row, a contact region that divides the cell row at a predetermined position of a boundary of a unit cell, a first power supply line and a first power line that are formed in parallel on the substrate and along the longitudinal direction of the cell row. And a second power supply line formed on the substrate in parallel with each other in a direction intersecting the longitudinal direction of the cell row and intersecting the first power supply line and the first ground line in the contact region. And a second ground line, a first contact hole provided in the contact region, for electrically connecting the first power supply line and the high-concentration impurity region of the first conductivity type, and provided in the contact region. And before A second contact hole for electrically connecting a first ground line and the high-concentration impurity region of the second conductivity type, and a first power line and a second power line which are provided in the contact region are electrically connected to each other. Third to make a physical connection
And a fourth contact hole that is provided in the contact region and electrically connects the first ground line and the second ground line, and each of the high-concentration impurity regions is the semiconductor substrate. The first to fourth contact holes are arranged so as to be located in the contact region, and the first and second contact holes are respectively under the second ground line and the second ground line. The semiconductor integrated circuit device is characterized in that it is located under the second power line and the third and fourth contact holes are located under the second power line and under the second ground line, respectively.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Refer to FIG. 1 to FIG. Here, FIG. 1 is a plan view of a pattern of a semiconductor integrated circuit device, FIG. 2 is a plan view of a macroscopic view of FIG. 1, and FIG. 3 is a partially enlarged pattern of a region B of FIG. FIG. 4 is a plan view, and FIG. 4 is a pattern plan view of cells arranged in the cut open region of the cell row of FIG.
FIG. 5 is a sectional view taken along line XX in FIG. In addition,
The same members as those of the related art are designated by the same reference numerals and the description thereof will be omitted.

In FIGS. 1 and 2, 31 ... Are cell rows 11 ₁ and 1 respectively.
The contact region is in the direction orthogonal to the longitudinal direction of 1 ₂ , 11 _3, ... Each of these contact regions 31 is provided with a cell 32 prepared in advance as shown in FIG. The cell 32 has an N-channel region on the upper side and a P-channel region on the lower side with a line (dashed-dotted line) 33 as a boundary. Then, a P ⁺ type diffusion layer (high concentration impurity region) 34 is provided in the N channel region, and N ⁺ is provided in the other P channel region.
A type diffusion layer (high-concentration impurity region) 35 is provided.

Here, only the P channel region of the cell 32 is
It will be described with reference to the drawings. Reference numeral 36 in the figure is, for example, an N ⁺ type silicon substrate. On the surface of the substrate 36, the N ⁺ type diffusion layer 35 described above is formed. A diffusion layer 35 is formed on the substrate 36.
Insulating film 38 having contact hole 37 in the portion corresponding to
Are formed. A contact hole is formed in the diffusion layer 35.
The first power line 12 ₂ made of Al is connected via 37.
On the insulating film 38 including the power supply line 12 _2, an interlayer insulating film 39 having a via contact hole 17 is provided. In the via contact hole 17, Al connected to GND
A second power supply line 40 made of electric material is provided so as to be electrically connected to the first power supply line 12 ₂ . A second power line 41 made of Al and connected to V _DD is provided on the interlayer insulating film 39. Here, the metal wirings 40 and 41 are arranged in parallel in a direction orthogonal to the longitudinal direction of the cell rows 11 ₁ , 11 ₂ , 11 _3, ... As shown in FIGS. ₁ and ₂ , respectively. Incidentally, in FIG., 42 is a contact hole for connecting the diffusion layer 35 and the power supply line 12 ₂ P ⁺ type.

Therefore, according to the present invention, the cell rows 11 ₁ , 11 ₂ , 11 ₃ ... Are cut at predetermined intervals in the direction orthogonal to the longitudinal direction of the cell rows, and the cells shown in FIG. 32 is provided,
Furthermore, its contact region 32 and channel regions 13 ₁ , 13 ₂
Since the second power supply lines 40 and 41 made of Al are provided in the direction orthogonal to the longitudinal direction of the cell row, even if the cell row becomes long, each unit cell in the cell row is The correct power supply voltage level can be given. as a result,
The unit cell can function properly.

Further, the cell 32 provided in the contact region 31, the diffusion layer 35 of N ⁺ -type is provided on a surface of the N-type silicon substrate 36, the substrate bias through the first power supply line 12 ₂ provided in the contact hole 37 Therefore, latch-up can be prevented.

Example 2 will be described with reference to FIGS. 9 to 11. Here, FIG. 9 is a pattern plan view schematically showing a semiconductor integrated circuit device,
FIG. 10 is a pattern plan view in which a region C of FIG. 9 is partially enlarged, and FIG. 11 is a sectional view taken along line XX of FIG.

The second embodiment is an example in which the number of the second power supply lines corresponding to FIGS. 1 to 4 is one. In this case, “1” level (V _DD ) and “0” level (GND) are alternately passed through the power supply line 51.
In FIG. 11, 52 is a P-well provided on the N-type silicon substrate 36, 53 is a P ⁺ -type diffusion layer provided on the surface of the well 52, and 54 is a diffusion layer 53. a contact hole connecting the second power supply line 12 _2, 55 Al of the first layer
Wiring is shown respectively.

Third Embodiment In this embodiment, as shown in FIG. 12, the second power supply line 61 is not linearly orthogonal to the longitudinal direction of the cell row as in the first and second embodiments, but in the wiring region. It is a part that is diverted without going through contacts.

According to the third embodiment, even if the incision region of each cell row is not positioned linearly in the direction orthogonal to the longitudinal direction of the cell row, the voltage drop in the cell row direction and the latch-up can be prevented. it can.

Although Al is used as the material of the power supply line in the above embodiment, the present invention is not limited to this, and other metal materials may be used.

〔The invention's effect〕

As described above in detail, according to the present invention, it is possible to provide a semiconductor integrated circuit device which can prevent a voltage drop in the cell direction by giving a correct voltage level to a unit cell.

[Brief description of drawings]

1 is a pattern plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a pattern plan view of FIG. 1 macroscopically, and FIG. 3 is a partially enlarged view of FIG. FIG. 4 is a plan view of a pattern, FIG. 4 is a plan view of a cell provided in the incision region of FIG. 2, FIG. 5 is a cross-sectional view taken along line XX of FIG.
FIG. 7 is a view of a conventional semiconductor integrated circuit device viewed from the entire chip, FIG. 7 is a pattern plan view of the conventional semiconductor integrated circuit device, FIG. 8 is a partially enlarged pattern plan view of FIG. 9 is a plan view of a pattern of a semiconductor integrated circuit device according to a second embodiment of the present invention, FIG. 10 is a partially enlarged plan view of FIG. 9, and FIG. 11 is taken along line XX of FIG. Cross section,
FIG. 12 is a pattern plan view of a semiconductor integrated circuit device according to a third embodiment of the present invention. 1 ... Chip, 2 ... Cell group, 3 ₁ , 3 ₂ , 12 ₁ , 12 ₂ ... 1st power supply line, 11 ₁ , 11 ₂ , 11 ₃ ... Cell row, 40, 41, 51, 61 ... 2nd
Power supply line, 13 ₁ , 13 ₂ ... Wiring area (channel area), 14,
15, 22, 55 ... Al wiring, 16, 21 ... Polysilicon wiring, 17 ...
Via contact hole, 18, 20, 37, 44, 54 ... Contact hole, 32 ... Cell, 34, 35, 53 ... Diffusion layer, 36 ... N type silicon substrate, 52 ... Well.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04 8826-4M H01L 21/90 A 8832-4M 27/04 D (56) References Kai 54-93375 (JP, A) JP 58-210636 (JP, A) JP 57-121250 (JP, A)

Claims (1)

[Claims] 1. A semiconductor substrate having a high-concentration impurity region of the first conductivity type and a second conductivity type on its surface, and a plurality of unit cells formed on the substrate and containing a certain functional circuit. A cell row, a contact region that divides the cell row at a predetermined position of a boundary of a unit cell, a first power supply line and a first power line that are formed in parallel on the substrate and along the longitudinal direction of the cell row. And a second power supply formed on the substrate in parallel with each other in a direction intersecting the longitudinal direction of the cell row and intersecting the first power supply line and the first ground line in the contact region. Line and a second ground line, a first contact hole provided in the contact region for electrically connecting the first power supply line and the high-concentration impurity region of the first conductivity type, and the contact region to the contact region. Provided A second contact hole for electrically connecting the first ground line and the high-concentration impurity region of the second conductivity type; and a first power line and a second power line provided in the contact region. A third contact hole for electrical connection; and a fourth contact hole provided in the contact region for electrically connecting the first ground line and the second ground line, the high concentration The impurity regions are for biasing the semiconductor substrate, the first to fourth contact holes are arranged so as to be located in the contact regions, and the first and second contact holes are respectively arranged in the second region. Under the second power supply line, and the third and fourth contact holes are located under the second power supply line and under the second ground line, respectively. Conductor integrated circuit device.