JPH079943B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

The present invention relates to a structure of a charge storage portion in a semiconductor memory device including a capacitor which is a charge storage portion and an insulated gate field effect transistor, and a manufacturing method thereof.

A semiconductor memory cell that stores binary information in the form of electric charge is excellent in high integration, large capacity, and memory cell because of its small cell area. In particular, a memory cell composed of one transistor and one capacitor (hereinafter abbreviated as 1T1C cell) as a memory cell is important as a memory cell for highly integrated memory because it has few constituent elements and a small cell area. By the way, with the decrease in memory cell size due to the high integration of memory, 1T
The area of the capacitance part in the 1C cell structure is decreasing. The decrease in the amount of stored charges due to the decrease in the area of the capacitance part
This causes particle problems and deterioration of the sensitivity of the sense amplifier.

Conventionally, in order to solve such a problem, as a method of forming a large storage capacitor portion despite the reduction of the memory cell area, a groove is provided in the semiconductor substrate, and a capacitor is formed between the side surface of the groove and the semiconductor substrate. It is known how to do it.

FIG. 1 shows an example of a well-known 1T1C cell in which a capacitor is formed by using a groove. In FIG. 1, numeral 3 is a capacitor electrode, and a thin insulating film 2 is provided between the capacitor electrode and the inversion layer 6 to form a memory capacitor portion. Reference numeral 4 denotes a gate electrode of the switching transistor, which is connected to the word line and controls the movement of charges between the diffusion layer 5 and the inversion layer 6 which are connected to the bit line.

However, 1T1C that uses conventional grooves to form the capacitive part
Due to the structure of the cell, a groove serving as a capacitance portion is formed in the element region. Therefore, the cell size inevitably increases by the size of the groove forming region and the margin between the groove and the separation region. If higher integration is required in the future and miniaturization of the cell size is required, the conventional 1T1C cell using a groove has a drawback that the miniaturization of the cell size is limited due to its structure.

It is an object of the present invention to provide a capacitor section structure which is suitable for high integration by extremely reducing the area of the capacitor section in a 1T1C cell in which a capacitor section is formed by using a groove, and a manufacturing method thereof.

According to the present invention, a groove having a two-step depth provided on the surface of the first-conductivity-type semiconductor substrate, a second-conductivity-type region formed on the opposite side wall of the shallow groove of the two-step groove, A region of the first conductivity type having a higher concentration than the substrate formed on the bottom of the deep groove, an insulating material that covers at least the inner wall of the groove, a conductive material that is in contact with the insulating material and is filled with the reference potential to fill the groove, A second conductivity type region which is provided on the surface of the first conductivity type semiconductor substrate, is in contact with the insulating material, and is a source electrode of a MIS transistor formed electrically connected to the second conductivity type region; A semiconductor memory device characterized by the above is obtained.

Furthermore, according to the present invention, the first conductive type semiconductor substrate is formed on the first substrate.
Forming the first groove of the first portion, and forming the first second conductivity type region on the inner wall of the first groove of the capacitance portion forming region,
Etching the bottom of the groove to form a second groove, forming a first conductivity type region having a higher concentration than the second substrate, and forming an insulating film on the surfaces of the first and second grooves. A step of filling the insides of the first and second grooves with a conductive material, a step of covering an upper portion of the conductive material with an insulating material, and electrically connecting to the first and second conductivity type regions. A method for manufacturing a semiconductor memory device is obtained, which includes the step of forming a second second conductivity type region.

Hereinafter, typical embodiments of the present invention will be described in detail with reference to the drawings.
2 (a), (b), (c), (d), (e),
(F), (g), (h), (i), and (j) are schematic cross-sectional views sequentially showing a manufacturing process for forming a capacitor portion using a groove in the present invention.

FIG. 2A shows a thin silicon dioxide film 12, a silicon nitride film 13, and a thick silicon dioxide film on a p-type silicon single crystal substrate 11.
After sequentially forming 14, the resist 15 is covered except for the groove formation region, and the silicon dioxide film 15, the silicon nitride film 14, and the silicon dioxide film 13 are sequentially removed by reactive sputter etching using the register 15 as an etching mask. Subsequently, the state where the first groove A is formed by etching the silicon substrate 11 using the resist 15 and the silicon dioxide film 14 as an etching mask is shown.

FIG. 2 (b) shows that after removing the resist 15, a silicon dioxide film 16 is formed on the surface of the groove A by a thermal oxidation method, and then a resist 17 is applied on the entire surface and silicon is further applied to the surface.
18 shows a state in which 18 is vapor-deposited thinly and the resist 19 covers the region other than the region to be the groove capacitance portion.

FIG. 2C shows a state in which the silicon 18 is etched using the resist 19 as an etching mask, and then the resist 17 is removed by etching using the silicon 18 'as an etching mask. Here, as one means for etching the resist 17, for example, there is a reactive sputter etching technique using oxygen gas.

FIG. 2D shows the silicon dioxide film after removing the silicon 18 'and using the resist 17' as an etching mask.
16 shows a state in which 16 is removed by etching, and a diffusion layer 20 of a conductivity type impurity such as phosphorus, which is different from that of the silicon substrate 11, is formed only in the groove of the capacitance forming region using the silicon dioxide film 14 as a mask.

FIG. 2 (e) shows the silicon substrate by reactive sputter etching using the silicon dioxide film 14 as an etching mask.
After etching 11 to form a deeper groove B, a silicon dioxide film 21 is formed on the surface of the groove by a thermal oxidation method, and then the silicon dioxide film 14 is used as a mask at the bottom of the groove B by an ion implantation method to form a substrate. 11 shows a state in which an impurity layer 22 of the same conductivity type as 11 is formed.

FIG. 2 (f) shows a state in which after the resist is formed on the entire surface, the resist 23 is left only in the groove by the reactive sputter etching using oxygen gas as described above.

FIG. 2 (g) shows a state in which the silicon dioxide film 14, the silicon nitride film 13 and the silicon dioxide film 12 are sequentially removed by etching using the resist 23 as a mask.

FIG. 2 (h) shows the resist 23 and the silicon dioxide film 21.
After removing the silicon dioxide film 24 and silicon nitride film 2 on the entire surface of the wafer
5 shows a state in which phosphorus-doped polycrystalline silicon 26 is sequentially formed. Here, the phosphorus-doped polycrystalline silicon 26 is formed thick enough to fill the groove sufficiently.

2 (i) shows that the phosphorus-doped polycrystalline silicon 26 is etched from the surface to leave the phosphorus-doped polycrystalline silicon 26 'only in the groove, and then the silicon-nitride film 25 is used as a mask to fill the groove. The state where the silicon dioxide film 27 is formed on the groove by oxidizing the crystalline silicon 26 'is shown. Since the silicon nitride film 25 is formed thin, when the phosphorus-doped polycrystalline silicon 26 is oxidized, the silicon nitride film 25 is completely oxidized, but the phosphorus-doped polycrystalline silicon 26 'and the silicon nitride film 25 are oxidized. There is a large difference in the rate, and there is a large difference between the silicon dioxide film thickness 27 'on the device region and the silicon dioxide film thickness on the isolation region.

FIG. 2 (j) shows that after removing the silicon dioxide film 27 'on the device region, a thin silicon dioxide film 28 is formed on the device region by the thermal oxidation method, and then the switching transistor connected to the word line is formed. Diffusion layers 30A, 30A 'and diffusion layer 2 which form gate electrodes 29, 29' and are then connected to bit lines
It shows a state in which the diffusion layers 30B and 30B 'electrically connected to 0'are simultaneously formed by the ion implantation method.

FIG. 2 (j) is a schematic sectional view of a semiconductor memory device formed according to the present invention. The operation of the semiconductor memory device according to the present invention will be described below using this. When storing electric charges, by turning on the switching transistor connected to the word line, electric charges are accumulated from the diffusion layer 30A connected to the bit line to the diffusion layer 20 'formed on the side wall of the groove and the stored state is obtained. Become. However, the phosphorus-doped polycrystalline silicon 26 'filled in the groove is grounded.
At this time, the storage capacitance is almost equal to the capacitance of the insulating film formed between the phosphorus-doped polycrystalline silicon 26 'which is the capacitance electrode and the diffusion layer 20' and the depletion layer capacitance spread from the diffusion layer 20 'into the silicon substrate 11. Composed of sum. To read the stored charge, switch the switching transistor connected to the word line.
The charges accumulated in the diffusion layer 20 'are transferred to the diffusion layer 30A which is turned on and connected to the bit line to perform reading.

Thus, the operation of the semiconductor memory device according to the present invention is the same as the conventional one. Then, similarly to the conventional case, the storage capacity can be increased easily by increasing the depth of the groove to be formed. However, the semiconductor memory device according to the present invention has the trench formed in the isolation region. That is, the point that the separation region doubles as the capacitance portion is a great difference from the conventional one. By forming the groove in the isolation region, the size thereof can be significantly reduced as compared with the conventional semiconductor memory device in which the groove is formed in the element region. Since the phosphorus-doped polycrystalline silicon filled in the groove is grounded, sufficient isolation characteristics between elements can be obtained. Further, since phosphorus-doped polycrystalline silicon, which is a capacitor electrode, is buried in the groove, it has a feature that the device surface is flat.

As described above, according to the present invention, since a large storage capacity can be obtained even in a fine area, a semiconductor memory device suitable for high integration can be easily obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a 1T1C cell in which a capacitive portion is formed by using a conventional groove, and FIGS. 2 (a), (b), (c),
(D), (e), (f), (g), (h), (i),
(J) is a typical sectional view showing the embodiment of the present invention step by step. In the figure, each symbol indicates the following. 1,11: Silicon substrate, 2,12,14,16,21,24,27,27 ', 28: Silicon dioxide film, 3,26': Capacitance electrode, 4,29,29 ': Connected to word line Switching transistor gate electrode,
5,30A, 30A ': Diffusion layer connected to bit line, 6: Inversion layer, 13,25: Silicon nitride film, 15,17,17', 19,23: Resist, 1
8, 18 ': Silicon, 20, 20', 30B, 30 ': Conductive impurity diffusion layer different from substrate, 22: Same conductive impurity diffusion layer as substrate, A, B: Grooves.

Claims (2)

[Claims] 1. A device provided on the surface of a first conductivity type semiconductor substrate.
A groove having a step depth, a second conductivity type region formed on opposite sidewalls of the shallow groove of the two-step groove, and a first conductivity type region having a higher concentration than the substrate formed on the bottom of the deep groove. An insulating material that covers at least the inner wall of the groove, a conductive material that is in contact with the insulating material and that is filled with the reference potential and is provided on the surface of the first conductivity type semiconductor substrate, and is in contact with the insulating material. A semiconductor memory device comprising a second conductivity type region which is a source electrode of a MIS transistor electrically connected to the second conductivity type region. 2. A step of forming a first groove on a first conductivity type semiconductor substrate, wherein a first groove is formed on an inner wall of the first groove in a capacitance portion forming region.
Forming a second conductivity type region, etching the first groove bottom to form a second groove, and forming a first conductivity type region having a higher concentration than the substrate on the second groove bottom. Process,
Forming an insulating film on the surfaces of the first and second trenches, filling the insides of the first and second trenches with a conductive material, covering the upper part of the conductive material with an insulating material, A method of manufacturing a semiconductor memory device, comprising a step of forming a second second conductivity type region so as to be electrically connected to the first second conductivity type region.