JPH0812539B2 - Display device and manufacturing method thereof - Google Patents
Display device and manufacturing method thereofInfo
- Publication number
- JPH0812539B2 JPH0812539B2 JP60013418A JP1341885A JPH0812539B2 JP H0812539 B2 JPH0812539 B2 JP H0812539B2 JP 60013418 A JP60013418 A JP 60013418A JP 1341885 A JP1341885 A JP 1341885A JP H0812539 B2 JPH0812539 B2 JP H0812539B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- display device
- address line
- drain
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/48—Flattening arrangements
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、薄膜トランジスタ(TFT)アレイを用いた
表示装置に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a display device using a thin film transistor (TFT) array.
近年、多結晶または非晶質半導体薄膜を用いたTFTア
レイを集積形成して駆動回路基板とした液晶表示装置が
注目されている。特にこの種の表示装置は、半導体薄膜
が低温で形成できることからガラス基板を用いることが
でき、従って低コスト化が可能であり、また従来の露光
技術、エッチング技術等をそのまま適用して大面積化を
図ることができるといった利点を有する。In recent years, a liquid crystal display device in which a TFT array using a polycrystalline or amorphous semiconductor thin film is integrally formed and used as a drive circuit substrate has attracted attention. In particular, this type of display device can use a glass substrate because the semiconductor thin film can be formed at a low temperature, and therefore can reduce the cost, and can increase the area by directly applying the conventional exposure technology, etching technology, etc. Has the advantage that
第3図に従来の駆動回路基板の一画素部分の構造を示
す。(a)は平面図であり、(b)はそのA−A′断面
図である。(1)はガラス基板であり、この上にゲート
電極(2)が形成され、この上にプラズマSiO2膜等によ
るゲート絶縁膜(3)を介して例えば非晶質シリコン
(a−Si)膜(4)が形成されている。a−Si膜(4)
には、ドレイン電極(5)、ソース電極(6)が形成さ
れ、ソース電極(6)は透明導電膜からなる表示画素電
極(7)に接続されている。ゲート電極(2)は、マト
リクスの行方向に配設されるアドレス線Xiと一体形成さ
れ、これにより行方向のTFTのゲート電極は全て共通接
続される。またドレイン電極(5)は、マトリクスの列
方向に配設されるデータ線Yjと一体形成され、これによ
る列方向のTFTのドレイン電極は全て共通接続される。FIG. 3 shows the structure of one pixel portion of a conventional drive circuit board. (A) is a plan view and (b) is an AA 'sectional view thereof. Reference numeral (1) is a glass substrate, on which a gate electrode (2) is formed, and an amorphous silicon (a-Si) film, for example, is formed on the glass substrate via a gate insulating film (3) such as a plasma SiO 2 film. (4) is formed. a-Si film (4)
A drain electrode (5) and a source electrode (6) are formed on the substrate, and the source electrode (6) is connected to the display pixel electrode (7) made of a transparent conductive film. The gate electrode (2) is integrally formed with the address line Xi arranged in the row direction of the matrix, whereby the gate electrodes of the TFTs in the row direction are all commonly connected. Further, the drain electrode (5) is integrally formed with the data line Yj arranged in the column direction of the matrix, and the drain electrodes of the TFTs in the column direction thereby are all commonly connected.
図では省略したが、実際にはこの駆動回路基板は表示
画素電極(7)の部分を除いてSiO2等の保護膜でおおわ
れている。そしてこの駆動回路基板と、全面に対向電極
を形成した対向基板との間に液晶を挾持してマトリクス
形液晶表示装置が構成される。Although not shown in the figure, this drive circuit substrate is actually covered with a protective film such as SiO 2 except for the display pixel electrode (7). Then, a matrix type liquid crystal display device is constructed by sandwiching liquid crystal between the drive circuit substrate and a counter substrate having a counter electrode formed on the entire surface.
ところでこの種の液晶表示装置が大面積化するに伴っ
て、ゲート電極段差部における絶縁膜の耐圧不良、ある
いはピンホール等によりアドレス線とデータ線のショー
トが増大する。By the way, as the area of this type of liquid crystal display device becomes large, short-circuiting between the address line and the data line increases due to a poor withstand voltage of the insulating film in the gate electrode step portion, a pinhole or the like.
この種の原因にともない線欠陥が発生し、表示品位を
著しく低下させる。A line defect is generated due to this type of cause, and the display quality is significantly deteriorated.
[発明の目的] 本発明は、上記の点に注目してなされたもので、アド
レス線の厚みで生じる段差をなくすことにより、この上
に形成する絶縁膜の膜厚を十分なものとして耐圧不良を
防ぎ、表示品位の低下を防止した表示装置を提供するこ
とを目的とする。また、このような表示品位の低下を防
止した表示装置を容易に形成できる表示装置の製造方法
を提供することも目的とする。[Object of the Invention] The present invention has been made by paying attention to the above points. By eliminating the step caused by the thickness of the address line, the insulating film formed thereon has a sufficient film thickness, and the withstand voltage defect is caused. It is an object of the present invention to provide a display device which prevents the deterioration of display quality. It is another object of the present invention to provide a method of manufacturing a display device, which can easily form a display device that prevents such deterioration of display quality.
[発明の概要] 本発明は、基板と、この基板上に上下2層形成された
絶縁膜と、この絶縁膜上にソース及びドレインが形成さ
れ前記絶縁膜を介してゲート電極が形成された薄膜トラ
ンジスタと、前記絶縁膜を介して上下に且つ互いに直交
する方向に配置された、前記ゲート電極と一体形成され
たアドレス線及び前記ソース又はドレインの一方と一体
形成されたデータ線と、前記上の絶縁膜上に形成され前
記ソース又はドレインの他方に接続された表示電極とを
有する表示装置において、前記下の絶縁膜に形成された
孔部を有し、前記アドレス線がこの孔部に埋設され前記
下の絶縁膜と略同一厚であることを特徴とする表示装置
を提供するものである。SUMMARY OF THE INVENTION The present invention is a thin film transistor in which a substrate, an insulating film formed in two layers on the substrate, a source and a drain are formed on the insulating film, and a gate electrode is formed through the insulating film. An address line formed integrally with the gate electrode and a data line formed integrally with one of the source and the drain, which are vertically arranged in a direction orthogonal to each other through the insulating film, In a display device having a display electrode formed on a film and connected to the other of the source and the drain, the display device has a hole formed in the lower insulating film, and the address line is embedded in the hole. The present invention provides a display device having a thickness substantially the same as that of an underlying insulating film.
また、本発明は基板と、この基板上に上下2層形成さ
れた絶縁膜と、この絶縁膜上にソース及びドレインが形
成され前記絶縁膜を介してゲート電極が形成された薄膜
トランジスタと、前記絶縁膜を介して上下に且つ互いに
直交する方向に配置され前記ゲート電極と一体形成され
たアドレス線及び前記ソース又はドレインの一方と一体
形成されたデータ線と、前記上の絶縁膜上に形成され前
記ソース又はドレインの他方に接続された表示電極とを
有する表示装置におけるアドレス線の製造方法におい
て、前記基板上に前記下の絶縁膜を形成する工程と、こ
の下の絶縁膜上にマスクを形成する工程と、このマスク
上から前記下の絶縁膜をエッチング除去して孔部を形成
する工程と、前記下の絶縁膜上及び前記マスクの全面に
前記下の絶縁膜と略同一厚の金属層を形成する工程と、
前記孔部以外の不要な前記金属層を前記マスクと共に除
去して前記アドレス線を形成する工程と、前記下の絶縁
膜及び前記アドレス線の全面に前記上の絶縁膜を形成す
る工程とを具備することを特徴とする表示装置の製造方
法を提供するものである。Further, the present invention provides a substrate, an insulating film formed on the substrate in upper and lower two layers, a thin film transistor in which a source and a drain are formed on the insulating film, and a gate electrode is formed through the insulating film, An address line which is arranged above and below and in a direction orthogonal to each other through a film, and which is integrally formed with the gate electrode, and a data line which is integrally formed with one of the source or the drain, and the data line which is formed on the insulating film above. In a method of manufacturing an address line in a display device having a display electrode connected to the other of a source and a drain, a step of forming the lower insulating film on the substrate, and forming a mask on the lower insulating film. A step of etching and removing the lower insulating film from the mask to form a hole, and a step of forming the hole on the lower insulating film and on the entire surface of the mask with the lower insulating film. Forming a thick metal layer,
A step of removing the unnecessary metal layer other than the holes together with the mask to form the address line; and a step of forming the upper insulating film on the entire surface of the lower insulating film and the address line. The present invention provides a method for manufacturing a display device.
[発明の効果] 本発明の第1の発明によれば、基板の絶縁性膜の凹部
にアドレス線を埋設することによって、基板上に形成す
る層間絶縁膜の下地の段差を軽減することができ、従っ
て層間絶縁膜の一部が薄くなることで生じる耐圧不良や
ピンホール等によるアドレス線とデータ線間のショート
もしくはリーク電流の発生を防止し、高い表示品位の表
示装置を提供することができる。また、アドレス線の厚
みとは無関係にショートもしくはリーク電流の発生を防
止できるため、配線の厚み設計の自由度が増し、アドレ
ス線の厚みを通常よりも厚くしてライン抵抗を低抵抗化
し、大面積化に最適した表示装置を提供することができ
る。[Effect of the Invention] According to the first aspect of the present invention, by burying the address line in the recess of the insulating film of the substrate, it is possible to reduce the step difference of the base of the interlayer insulating film formed on the substrate. Therefore, it is possible to provide a display device with high display quality by preventing occurrence of short circuit or leak current between the address line and the data line due to poor withstand voltage or pinhole or the like caused by thinning of a part of the interlayer insulating film. . Also, since it is possible to prevent the occurrence of short circuit or leakage current regardless of the thickness of the address line, the degree of freedom in designing the thickness of the wiring is increased, and the thickness of the address line is made thicker than usual to lower the line resistance and increase the resistance. It is possible to provide a display device that is most suitable for increasing the area.
また、第2の発明によれば、基板上の絶縁膜に凹部を
形成した後、凹部内にアドレス線を埋設する工程を経る
ため、凹部を形成したマスクをそのままアドレス線を埋
め込むマスクに使うこと(リフトオフ法)ができ、凹部
に自己整合したアドレス線によって確実に平坦化され表
示品位に優れた特性の表示装置を複雑な工程を経ること
なく容易に形成することができる。Further, according to the second aspect of the invention, since the step of forming the recess in the insulating film on the substrate and then burying the address line in the recess is performed, the mask in which the recess is formed is used as it is as the mask for burying the address line. (Lift-off method) is possible, and it is possible to easily form a display device which is flattened by the address line self-aligned with the concave portion and has excellent display quality without complicated steps.
[発明の実施例] 第1図は、本発明の一実施例のTFTアレイ部の一部を
製造工程順の断面図で示したものである。第2図は、第
1図で示した製造工程の続きの製造工程を経て形成され
るTFTアレイ部の断面図である。また第2図は、第1図
に示したTFTアレイ部を第3図(a)のA−A′断面に
対応する断面図で示したもので、第3図と対応する部分
には同一符号を付けている。[Embodiment of the Invention] FIG. 1 is a sectional view showing a part of a TFT array portion of an embodiment of the present invention in the order of manufacturing steps. FIG. 2 is a cross-sectional view of a TFT array portion formed through a manufacturing process subsequent to the manufacturing process shown in FIG. 2 is a cross-sectional view of the TFT array section shown in FIG. 1 corresponding to the AA ′ cross section of FIG. 3 (a). Is attached.
まず、第1図に沿って製造方法を説明する。ガラス基
板(1)上に第1絶縁膜SiO2(31)を3000オングストロ
ーム(以下、Aと省略する)堆積する(第1図
(a))。First, the manufacturing method will be described with reference to FIG. A first insulating film SiO 2 (31) is deposited on the glass substrate (1) at 3000 Å (hereinafter, abbreviated as A) (FIG. 1A).
この後、レジストをコートしこれを所望のパターンに
露光・エッチングを行なって、レジストマスク(101)
を形成する(第1図(b))。After that, a resist is coated and the desired pattern is exposed and etched to form a resist mask (101).
Are formed (FIG. 1 (b)).
次いで、このレジストマスク(101)上からSiO2(3
1)をエッチングし、凹部を形成する。さらにこのレジ
ストマスク(101)上からAl(2)2000A,Mo(21)1200A
を連続してスパッターする(第1図(c))。Then, SiO 2 (3
1) is etched to form a recess. Further, from above the resist mask (101), Al (2) 2000A, Mo (21) 1200A
Are continuously sputtered (FIG. 1 (c)).
その後、レジストマスク(101)を剥離することによ
って、このマスク上の不要なAlとMoをリフトオフ法で除
去すると共に、凹部に埋め込んだAl(2)とMo(21)を
ゲート電極として残す(第1図(d))。After that, by removing the resist mask (101), unnecessary Al and Mo on the mask are removed by a lift-off method, and Al (2) and Mo (21) embedded in the recess are left as a gate electrode (first). Figure 1 (d)).
この後、SiO2(31)及びゲート電極の全面にゲート絶
縁膜(3)としてSiO2を2000A、a−Si膜(4)を3000A
連続成膜し、a−Si膜(4)を島形状にエッチングし、
さらに表示用透明導電膜を1200Aスパッター形成した後
にエッチングで形状の加工を行なって、表示電極(7)
を形成した。さらに、Alを1μm蒸着し、パターニング
を行なってソース電極(6)、ドレイン電極(5)を形
成する。このソース電極(6)は表示電極(7)に接続
されており、またドレイン電極はデータ線と一体形成さ
れたものである。ここで、薄膜トランジスタと表示電極
の製造工程が終了した(第2図)。上述した様に第3図
のA−A′断面に対応する部分のみこの第1図、第2図
で説明したために、凹部に埋め込んだゲート電極のみが
第1図で示されただけであるが、実際には、ゲート電極
と同一の配線材料層(Al/Mo積層膜)から形成されるア
ドレス線もゲート電極と同一の製造工程を経て凹部に埋
め込み形成されている。Then, SiO 2 (31) and the gate electrode are covered with 2000 A of SiO 2 and 3000 A of a-Si film (4) on the entire surface of the gate electrode.
Continuous film formation, a-Si film (4) is etched into an island shape,
Furthermore, after forming a transparent conductive film for display by 1200 A by sputtering, the shape is processed by etching, and the display electrode (7)
Was formed. Further, Al is vapor-deposited with a thickness of 1 μm and patterned to form a source electrode (6) and a drain electrode (5). The source electrode (6) is connected to the display electrode (7), and the drain electrode is integrally formed with the data line. At this point, the manufacturing process of the thin film transistor and the display electrode is completed (FIG. 2). As described above, only the portion corresponding to the AA 'cross section of FIG. 3 has been described with reference to FIGS. 1 and 2, so that only the gate electrode embedded in the recess is shown in FIG. Actually, the address line formed of the same wiring material layer (Al / Mo laminated film) as the gate electrode is also embedded and formed in the recess through the same manufacturing process as the gate electrode.
この様な製造工程によって作成された装置のアドレス
線はMo/Al3000Aと厚くできているため、ライン抵抗が低
抵抗化されており、大面積化に最適である。又ゲート電
極の段差を少く耐圧も向上し、アドレス線とデータ線と
の層間ショートが従来法に比べ数本と少ない結果を得
た。従来法のショートの原因はゲート電極段差部での耐
圧不良、あるいは段差部でのピンホール等が考えられ
る。Since the address line of the device manufactured by such a manufacturing process is thick as Mo / Al3000A, the line resistance is reduced, which is most suitable for increasing the area. In addition, the step difference of the gate electrode was improved and the breakdown voltage was improved, and the interlayer short between the address line and the data line was as small as several lines as compared with the conventional method. The cause of the short circuit in the conventional method is considered to be a poor withstand voltage at the stepped portion of the gate electrode or a pinhole at the stepped portion.
以上のように本発明構造を用いることにより耐圧が向
上し、アドレス線とデータ線のショートの原因が減少
し、又ゲート電極を厚く出来る為ライン抵抗を下げる事
が容易であり大面積表示装置に最適であり、なお表示品
位を著しく向上する。As described above, by using the structure of the present invention, the breakdown voltage is improved, the cause of the short circuit between the address line and the data line is reduced, and since the gate electrode can be thickened, it is easy to reduce the line resistance, and the large area display device Optimal, yet significantly improves the display quality.
第1図は本発明実施例のリフト・オフによるゲート電極
形成を示す断面図、第2図は本発明実施例のTFTアレイ
部と画素部を示す断面図、第3図は従来例の平面図及び
断面図を示す図である。 1……ガラス基板 2……ゲート電極(Al) 21……ゲート電極(MO) 3……ゲート絶縁膜(SiO2) 31……第1絶縁膜(SiO2) 4……a−Si膜 5,6……ソース・ドレイン電極(Al) 7……表示電極(ITφ) 101……レジストFIG. 1 is a sectional view showing a gate electrode formation by lift-off according to an embodiment of the present invention, FIG. 2 is a sectional view showing a TFT array portion and a pixel portion according to an embodiment of the present invention, and FIG. 3 is a plan view of a conventional example. It is a figure which shows and sectional drawing. 1 …… Glass substrate 2 …… Gate electrode (Al) 21 …… Gate electrode (MO) 3 …… Gate insulating film (SiO 2 ) 31 …… First insulating film (SiO 2 ) 4 …… a-Si film 5 , 6 …… Source / drain electrode (Al) 7 …… Display electrode (ITφ) 101 …… Resist
Claims (4)
絶縁膜と、この絶縁膜上にソース及びドレインが形成さ
れ前記絶縁膜を介してゲート電極が形成された薄膜トラ
ンジスタと、前記絶縁膜を介して上下に且つ互いに直交
する方向に配置された、前記ゲート電極と一体形成され
たアドレス線及び前記ソース又はドレインの一方と一体
形成されたデータ線と、前記上の絶縁膜上に形成され前
記ソース又はドレインの他方に接続された表示電極とを
有する表示装置において、前記下の絶縁膜に形成された
孔部を有し、前記アドレス線がこの孔部に埋設され前記
下の絶縁膜と略同一厚であることを特徴とする表示装
置。1. A substrate, an insulating film formed in two layers above and below the substrate, a thin film transistor in which a source and a drain are formed on the insulating film and a gate electrode is formed through the insulating film, and the insulating film. An address line integrally formed with the gate electrode and a data line integrally formed with one of the source and the drain, which are vertically arranged through a film and are orthogonal to each other, and formed on the insulating film above. And a display electrode connected to the other of the source and the drain, the display device having a hole formed in the lower insulating film, and the address line embedded in the hole, the lower insulating film. And a display device having substantially the same thickness as the display device.
ン、ポリイミドの少なくとも一種類を使ったことを特徴
とする特許請求の範囲第1項記載の表示装置。2. The display device according to claim 1, wherein the insulating film is made of at least one of silicon dioxide, silicon nitride and polyimide.
属層を積層したことを特徴とする特許請求の範囲第1項
記載の表示装置。3. The display device according to claim 1, wherein the address line is formed by laminating at least one metal layer.
絶縁膜と、この絶縁膜上にソース及びドレインが形成さ
れ前記絶縁膜を介してゲート電極が形成された薄膜トラ
ンジスタと、前記絶縁膜を介して上下に且つ互いに直交
する方向に配置され前記ゲート電極と一体形成されたア
ドレス線及び前記ソース又はドレインの一方と一体形成
されたデータ線と、前記上の絶縁膜上に形成され前記ソ
ース又はドレインの他方に接続された表示電極とを有す
る表示装置におけるアドレス線の製造方法において、前
記基板上に前記下の絶縁膜を形成する工程と、この下の
絶縁膜上にマスクを形成する工程と、このマスク上から
前記下の絶縁膜をエッチング除去して孔部を形成する工
程と、前記下の絶縁膜上及び前記マスクの全面に前記下
の絶縁膜と略同一厚の金属層を形成する工程と、前記孔
部以外の不要な前記金属層を前記マスクと共に除去して
前記アドレス線を形成する工程と、前記下の絶縁膜及び
前記アドレス線の全面に前記上の絶縁膜を形成する工程
とを具備することを特徴とする表示装置の製造方法。4. A substrate, an insulating film formed on the substrate in upper and lower two layers, a thin film transistor in which a source and a drain are formed on the insulating film, and a gate electrode is formed through the insulating film, and the insulating film. An address line which is arranged above and below and in a direction orthogonal to each other through a film, and which is integrally formed with the gate electrode, and a data line which is integrally formed with one of the source or the drain, and the data line which is formed on the insulating film above. In a method of manufacturing an address line in a display device having a display electrode connected to the other of a source and a drain, a step of forming the lower insulating film on the substrate, and forming a mask on the lower insulating film. A step of forming a hole by etching and removing the lower insulating film from above the mask, and substantially the same as the lower insulating film above the lower insulating film and on the entire surface of the mask Forming an address line by removing the unnecessary metal layer other than the hole together with the mask, and forming the address line on the entire surface of the lower insulating film and the address line. And a step of forming an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60013418A JPH0812539B2 (en) | 1985-01-29 | 1985-01-29 | Display device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60013418A JPH0812539B2 (en) | 1985-01-29 | 1985-01-29 | Display device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61173286A JPS61173286A (en) | 1986-08-04 |
| JPH0812539B2 true JPH0812539B2 (en) | 1996-02-07 |
Family
ID=11832583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60013418A Expired - Lifetime JPH0812539B2 (en) | 1985-01-29 | 1985-01-29 | Display device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812539B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01229229A (en) * | 1988-03-09 | 1989-09-12 | Seikosha Co Ltd | Thin-film transistor of amorphous silicon and production thereof |
| JPH02143462A (en) * | 1988-11-24 | 1990-06-01 | Sony Corp | Thin film transistor |
| JPH07113726B2 (en) * | 1989-01-10 | 1995-12-06 | 富士通株式会社 | Method of manufacturing thin film transistor matrix |
| JP2552365B2 (en) * | 1989-08-11 | 1996-11-13 | シャープ株式会社 | Active matrix display |
| US5859444A (en) * | 1991-08-08 | 1999-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JPH0651350A (en) * | 1992-08-03 | 1994-02-25 | Alps Electric Co Ltd | Display device |
| JP2008103653A (en) * | 2006-09-22 | 2008-05-01 | Tohoku Univ | Semiconductor device and manufacturing method of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58162133U (en) * | 1982-04-22 | 1983-10-28 | 旭光学工業株式会社 | Drive transmission device for camera and winder |
| JPS59119379A (en) * | 1982-12-27 | 1984-07-10 | 株式会社東芝 | Thin display |
-
1985
- 1985-01-29 JP JP60013418A patent/JPH0812539B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61173286A (en) | 1986-08-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |