JPH0812599B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Outline Industrial field of application Conventional technology (Figs. 3 to 5) Problems to be solved by the invention (Fig. 6) Means for solving the problems Action Implementation Example One embodiment of the present invention (FIGS. 1 and 2) Effect of the invention [Overview] A data processing device for pipeline processing microprogram control, wherein pipeline processing is effective even during processing of a conditional branch instruction. A plurality of microinstructions including a conditional branch instruction and a branch destination instruction of the conditional branch instruction are stored, and each microinstruction is fetched by addressing for the purpose of providing a data processing device that does not reduce the processing speed. Storage means and, when one microinstruction is fetched from the storage means, first address generation for generating a sequential address designating the next microinstruction following the microinstruction Means, decoding means for decoding the instruction type of the fetched microinstruction, execution means for executing processing to determine whether or not the condition is satisfied when the decoded instruction type is a conditional branch instruction, and conditional branch instruction Second address generating means for generating the address of the branch destination instruction of 1) and the first address generating means when the condition is not satisfied, while the second address generating means is selected and stored in the storing means when the condition is satisfied. Selecting means for giving an address for fetching a microinstruction, and when the decoded instruction type is a conditional branch instruction, the first address generating means until the branch condition is satisfied or not is determined. If the micro instruction based on the generated sequential address is executed and the branch condition is not satisfied, the processing of the micro instruction based on the sequential address is continued and the If the conditions are satisfied, the generated from the second address generating means, characterized in that the processing of microinstructions based on the address of the branch destination instruction is carried out.

[Industrial applications]

The present invention relates to a data processing device, and more particularly to a data processing device that pipelines microprogram control, and more particularly to a data processing device that avoids processing delay when a conditional branch instruction is not branched.

Generally, processing in a computer or the like is performed through a plurality of processing stages. For example, in instruction execution control, (I) fetching of micro instruction, (II) decoding, (III) address calculation, (IV) operand fetching, V) Execution, multi-step processing such as Basically, these processes are sequentially performed in the order of (I) → (II) ... (V), and such a sequential process is still used in a simple system even now. However, such sequential processing has a problem in processing speed. FIG. 3 is a conceptual diagram of sequential processing. In the figure, the process A corresponds to the above (I), the process B corresponds to the (II), the process C corresponds to the (III), the process D corresponds to the (IV), and the process E. Corresponds to (V). For example, the processing speed when an instruction is processed after the instruction is as follows. That is, the instruction is process A
In t _A, t _B in the process B, the process C t _C, t _D in the process D, t _E in the process E, cause the processing delay made, total processing delay T from the processing A to the processing E is t _A + t _B
It becomes + t _C + t _D + t _E. This is also true for the processing of instructions, so there is a T
There is a gap in [time], which is a big problem to meet the recent demand for high speed.

[Conventional technology]

Pipeline control is used as a solution to the problem of such sequential processing. FIG. 4 is a conceptual diagram showing pipeline processing. In the figure, the instruction fetched in the process A is moved to the process B in the next cycle, and at the same time, the process A fetches the next instruction. When the instruction moves to the process C, the instruction moves to the process B in parallel with this, and the process A fetches the next-higher-order instruction.

That is, in the pipeline control in which the processes A to E are performed in parallel, the processes A to E have to be performed until the execution result of the first instruction is obtained. Therefore, the same process as the sequential process is performed. Speed T (T = t _A ＋ t _B ＋ t _C ＋ t _D ＋
t _E ), but after the instruction, the execution result is obtained for each processing cycle. If this system is synchronous, t _A
= T _B = t _C = t _D = t _E = processing cycle, the processing delay is shortened to the time t corresponding to one processing stage,
It is possible to perform extremely high-speed processing.

Also in the micro program control, pipeline control is performed similarly to the above-mentioned instruction execution control, and each process of the micro program control, that is, (I ') fetching of micro instruction (II') decoding (III ') execution (IV ') Pipeline each process of storing execution results. FIG. 5 is a conceptual diagram of the pipeline processing. In FIG. 5, treatment 1 corresponds to the above (I '), treatment 2 corresponds to the above (II') and (III '), and treatment 3 corresponds to the above (IV').

[Problems to be solved by the invention]

However, in such a conventional data processing device using pipeline processing, when an instruction is being executed in the process 3, the next instruction following this instruction is processed 2
In addition to the decoding and address calculation processing performed in step 1, the next-higher-order instruction is fetched in step 1. Therefore, for example, a conditional branch instruction with condition determination (hereinafter simply referred to as a branch instruction) is executed in step 3. If it is medium, whether to process the next instruction (non-branch side processing) or another branch destination instruction (branch side processing) until the execution result (that is, the determination result) is obtained. Has not been finalized. Therefore, it is meaningless to process the next and next instructions until the branch instruction moves from the processing 1 to the processing 3 to obtain a result, and normally, the no-operation instruction (NO
P) is the next and subsequent instruction following the branch instruction.

FIG. 6 is a conceptual diagram of conventional pipeline processing in which a NOP is inserted after a branch instruction. In the figure, the condition judgment of the branch instruction A is performed in the execution process of the process 3, and if the condition is not satisfied, the A is fetched again in the process 1 and the processes 1 to 3 are repeated and continued. Then, when the condition is satisfied, the address of the micro instruction is switched, a predetermined branch destination instruction is fetched in the process 1, and thereafter the branch side process is continued. Thus, after the branch instruction A, a plurality of NOPs corresponding to the number of processing stages are
Therefore, there is a problem that the effect of the pipeline processing is substantially lost during the processing of the branch instruction, and the processing speed is reduced to almost the same level as the above-mentioned sequential processing.

The present invention has been made in view of such problems,
An object of the present invention is to provide a data processing device in which pipeline processing is effectively performed even during processing of a conditional branch instruction and the processing speed does not decrease.

[Means for solving problems]

In order to achieve the above object, the present invention stores a plurality of microinstructions including a conditional branch instruction and a branch destination instruction of the conditional branch instruction, and stores each microinstruction by addressing, and the storing means. When a microinstruction is fetched from the first microinstruction, a first sequential address that specifies the next microinstruction following the microinstruction is generated.
Address generating means, decoding means for decoding the instruction type of the fetched microinstruction, and execution means for executing processing to determine whether or not the condition is satisfied when the decoded instruction type is a conditional branch instruction. The second address generating means for generating the address of the branch destination instruction of the conditional branch instruction and the first address generating means when the condition is not satisfied are selected, while the second address generating means is selected when the condition is satisfied. Selecting means for giving an address for fetching a microinstruction to the storing means, and when the decoded instruction type is a conditional branch instruction, the first address until the branch condition is determined to be satisfied or not satisfied. If the microinstruction based on the sequential address generated by the generating means is executed and the branch condition is not satisfied, the processing of the microinstruction based on the sequential address is continued. Together, if the branch condition is satisfied, the generated from the second address generating means, characterized in that the processing of microinstructions based on the address of the branch destination instruction is carried out.

[Operation] In the present invention, until the result of the conditional judgment of the conditional branch instruction is obtained, the micro-instructions on the non-branch side are continuously fetched by the sequential addresses from the first address generating means.

Therefore, since there is no blank in the processing of the instruction following the conditional branch instruction, the pipeline processing works effectively and the processing speed is not reduced.

When the condition is satisfied, the branch side micro instruction (branch destination instruction) is generated by the address from the second address generating means.
Is taken in and the necessary branching processing is performed.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 and 2 are diagrams showing an embodiment of a data processing device according to the present invention, which is an example applied to a next address type data processing device for pipeline processing of microprogram control.

First, the configuration will be described. In FIG. 1, a data processing device 1 includes an instruction fetch processing unit 2 for fetching microinstructions in pipeline processing, and an execution processing unit 3 for performing processing other than instruction fetch processing in pipeline processing. The instruction fetch processing unit 2 includes a micro ROM 4 and a micro RO.
The MBNA 5, the selecting means 6 and the delay circuit 7 are included.

The micro ROM 4 has a function as a storage unit and a first address generation unit, is configured by a ROM (Read Only Memory) or a PLA (Programmable Logic Array), and stores a micro program including many micro instructions MO inside. In addition, the next address information NA is stored corresponding to each of these many micro instructions MO. Address information AD is input to the micro ROM 4, one micro instruction MO is fetched by addressing the address information AD, and next address information NA corresponding to the fetched micro instruction MO is output. The many micro instructions MO include so-called conditional branch instructions and branch destination instructions of these conditional branch instructions.

Here, the conditional branch instruction is an instruction that determines the subsequent branch processing depending on whether or not a predetermined condition is satisfied. For example, a multiplication instruction (MUL instruction), a division instruction (DIV instruction), or a load multi-register instruction. (LDM instruction) and so on. For example, the MUL instruction of A = n × m repeats this addition for m loops by adding A = n + A as one loop, and when A = n × m is finally obtained, the branch side processing is performed as the condition is satisfied. It is an instruction. Therefore, when A ≠ n × m where the condition is not satisfied, the non-branching side process is executed and A = n +
Since the addition of A is repeated, the branch side processing occurs once in one MUL instruction, whereas the non-branch side processing occurs m times. That is, if the non-branching side processing can be continuously processed without interruption, the effect of the pipeline processing can be effectively exhibited.

The above-mentioned next address information NA is the microinstruction MO of the non-branch side processing to be processed next to the corresponding microinstruction MO.
Indicates the storage address of this, and the next address information NA
When the determination result signal S _J described later is on the non-branching side, the address information AD is input to the micro ROM 4.

The micro ROMBNA5 has a function as a second address generating means, is constituted by a ROM or a PLA, and is branch destination address information for designating a branch destination instruction of the conditional branch instruction.
BNA is stored internally. The delay address information AD _-n before n processing cycles is input to the micro ROM BNA5, and the branch destination address information BNA is output according to the address designation of the delay address information AD _-n .

The selecting means 6 receives the input terminal 6a to which the next address information NA from the micro ROM 4 as the first address generating means is input, and the branch destination address information BNA from the micro ROM BNA5 as the second address generating means. The selected input terminal 6b and the branch destination address information BNA are selected by selecting the input terminal 6a when the branch is not established according to the determination result signal S _J described later, and when the branch is established. The output terminal 6c outputs either one as the fetched address information AD.

The delay circuit 7 comprises, for example, n stages of latch circuits, holds the address information AD for n processing cycles, and outputs it as delay address information AD _-n . The number n of latch stages may be one.

The execution processing unit 3 has a function as a decoding unit and an execution unit, and decodes the instruction type of the microinstruction MO fetched by the instruction fetch processing unit 2, calculates an address, fetches an operand, and executes an instruction. And the like are executed in parallel for each processing cycle. Further, when the instruction type of the micro instruction MO is a conditional branch instruction, the execution processing unit 3 performs an execution process for determining whether or not a given condition is satisfied, and outputs the determination result signal S _J. The execution processing unit 3 is provided with a plurality of registers # φ to #m and at least one counter (not shown), and is connected with an I / O such as a memory via a data bus to execute instructions. Data is exchanged between the memory and the register, and the counter value is manipulated according to the execution process.

 Next, the operation will be described.

In FIG. 1, the fetch operation of the micro instruction MO in the instruction fetch processing section 2 is performed as follows. That is, when a predetermined microinstruction MO is taken out, the next address information NA corresponding to this microinstruction MO is output, and the next address information NA is selected by the selecting means 6.
Input terminal 6a. At this time, the judgment result signal S _J
Indicates the non-branching side, the next address information NA is output to the output terminal 6c as the address information AD.
Therefore, in the fetch processing of the micro instruction MO (hereinafter, processing 1), while the determination result signal S _J indicates the non-branch side, the next address information NA is added to the micro ROM 4 as the address information AD again. Repeatedly, the so-called next address type micro instruction fetch processing is performed, and the micro instruction MO is processed every processing cycle.
Are taken out continuously.

On the other hand, when a branch condition is determined as a result of the branch condition determination process (hereinafter referred to as process 3) in the execution processing unit 3, the selection unit 6 selects the branch destination address information BNA according to the determination result information S _J indicating that the branch condition is satisfied. , And outputs this branch destination address information BNA as address information AD. Therefore, micro
The branch destination instruction specified by the branch destination address information BNA is fetched from the ROM 4, and the execution processing unit 3 executes the necessary processing according to the fetched branch destination instruction.

FIG. 2 is a conceptual diagram of pipeline processing during LDM instruction processing, for example. In FIG. 2, a process 1 represents a microinstruction fetching process, a process 2 represents a microinstruction decoding process and a partial execution process, a process 3 represents a microinstruction execution process such as condition determination, and a square box. The letters A, B, and X in the frame represent microinstructions corresponding to LDM instructions. For example, A is an instruction to set an initial value (for example, 3) to the counter, B is a non-branch side instruction to store the data from the memory in the register of the number corresponding to the counter value and to decrement the counter,
X is a branch target instruction that ends the processing of the LDM instruction when the condition is satisfied.

In process 1, the determination result signal S _J from the execution processing unit 3
Indicates the non-branching side, so the next address information NA
The micro-instruction MO specified by is continuously fetched every processing cycle. That is, it is the instruction of A and the instruction of B of each loop continuous to the right of this instruction of A. The instruction A sets the counter value to the initial value (for example, 3) in the process 2. The instruction of B is the processing 2 of the first loop.
In step 3, the data is read from the memory, the counter value is decremented, and the processing unit 3 stores the read data in the # 2 register corresponding to the counter value. Then, in the process 3, it is also determined whether or not the counter value has reached “0”, and when it has reached, the determination result signal S _J is output as a signal indicating that the branch has been taken. If not, the determination result signal S _J is output as a signal indicating non-establishment. That is, in the process 3 of the first loop, since the counter value is still 2, the branch is not taken and the determination result signal S _J is output as a signal indicating non-branch. As a result, the instruction of B on the non-branch side specified by the next address information NA is fetched from the micro ROM 4, and the second loop is performed. Then, also in the processes 2 and 3 of the second loop, the counter value is decremented, the data is stored, and the condition is determined in the same manner as in the first loop, and in such a loop, the counter value reaches "0". Is repeated until. As a result, when the counter value becomes “0”, the data from the memory is stored in all the registers of # φ to # 2, and the processing of the LDM instruction is completed. That is, since the counter value becomes "0" in the process 3 of the third loop, the condition for the branch is satisfied in the process 3 and the determination result signal S _J indicating the branch is output.

The selecting means 6 selects the input terminal 6b on the side of the branch destination address information BNA in accordance with this determination result signal S _J , adds the BNA as address information AD to the micro ROM 4, and from the micro ROM 4,
The branch destination instruction (X instruction) specified by the BNA is fetched. Then, the subsequent processing is performed with respect to this X instruction, and for example, the processing is stopped or another processing is started. When the condition for branching is satisfied in the process 3 of the third loop, the process 2 of the fourth loop which is being executed in parallel is canceled and becomes invalid.

As described above, in the present embodiment, in process 3, it is determined whether or not the branch condition is satisfied, and at the same time, the determination result signal S _J indicating the result of this determination is output to the selecting means 6, and when the branch is not satisfied, the next condition is determined. Select address information NA and select micro ROM 4
On the other hand, when the branch is taken, the branch destination address information BNA is selected and added to the micro ROM 4. Therefore, when the branch is not taken, the fetch operation of the micro instruction MO in the process 1 is continuously performed without interruption, and the effect of the pipeline processing can be effectively exerted to increase the speed. When a branch is taken, switching from NA to BNA leaves a blank for one processing cycle. However, since the branch is taken only once in multiple loops, one processing cycle is required for the speed-up effect when not branching. Blanks have little effect,
It doesn't matter.

〔The invention's effect〕

According to the present invention, even during processing of a conditional branch instruction,
A pipeline processing can be effectively performed, and a data processing device in which the processing speed does not decrease can be realized.

[Brief description of drawings]

1 and 2 are diagrams showing an embodiment of a data processing apparatus according to the present invention, FIG. 1 is a block diagram of the main part thereof, FIG. 2 is a conceptual diagram of its pipeline processing, and 3 to 6 FIG. 3 is a diagram for explaining a conventional data processing device, FIG. 3 is a conceptual diagram showing its sequential processing, FIG. 4 is a conceptual diagram showing pipeline processing in its instruction execution control, and FIG. 5 is its microprogram. FIG. 6 is a conceptual diagram showing pipeline processing in control, and FIG. 6 is a conceptual diagram for explaining the problem. 3 ... Execution processing unit (decoding means, execution means), 4 ... Micro ROM (storage means, first address generation means), 5 ... Micro ROM BNA (second address generation means), 6 ... selection means .

Claims (1)

[Claims] 1. A storage means for storing a plurality of microinstructions including a conditional branch instruction and a branch destination instruction of the conditional branch instruction, and each microinstruction is fetched by addressing, and one microinstruction is fetched from the storage means. When
First address generating means for generating a sequential address designating the next microinstruction following the microinstruction, decoding means for decoding the instruction type of the fetched microinstruction, and the decoded instruction type is a conditional branch instruction. At this time, executing means for executing processing for judging whether the condition is satisfied or not, second address generating means for generating an address of a branch destination instruction of the conditional branch instruction, and first address generating means when the condition is not satisfied. On the other hand, when the condition is satisfied, the second address generating unit is selected and the storing unit is provided with an address for fetching the microinstruction, and when the decoded instruction type is a conditional branch instruction, Until the branch condition is determined to be satisfied or not satisfied, the microinstruction based on the sequential address generated by the first address generating means is executed, and When the condition is not satisfied, the processing of the micro instruction based on the sequential address is continued, and when the branch condition is satisfied, the address of the branch destination instruction generated from the second address generating means. A data processing device characterized in that processing of a microinstruction based on is performed.