JPH0812626B2 - Shift path diagnostic method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a shift path diagnosis method, and more particularly to a shift path failure diagnosis method in an information processing apparatus.

2. Description of the Related Art Generally, an information processing device includes a large number of storage elements that are circuit configuration units that form a logic circuit network.
A so-called shift path configuration is adopted for failure diagnosis of these storage elements. This shift path has a shift register structure in which a plurality of storage elements are connected in series to each other.
Predetermined data that is predetermined in the shift mode is sequentially transferred from the storage element at the frontmost stage to the storage element at the final stage, and failure diagnosis of the shift path is performed based on the shiftout data.

In this type of information processing device, the field replaceable unit (FRU) is 1 when the hardware fails.
More than one is typically included for each shift path. Therefore, if a failure occurs in the shift path, there will be multiple replacement units, and the average repair time (Mean Time To Repai)
There is a drawback that r: MTTR) becomes large.

As a conventional technique for compensating for the above-mentioned drawbacks, the device is kept in an initial state, data is output by using a shift register function for one shift unit including a faulty exchange unit, and the data is output in the initial state of the device. There is a way to indicate the failing exchange unit by comparing it with the data. When a shift register fails in a device that uses the function of the shift register to initialize the device, the above method cannot set the device to the initial state. It has the drawback of increasing the repair time (MTTR).

Further, since it is necessary to store the initial state in advance and compare this with the data in which all bits are output by using the shift register function, there is a disadvantage that it takes time to indicate the exchange unit.

OBJECT OF THE INVENTION The present invention has been made to solve the above drawbacks of the prior art, and its object is to make it possible to point out a maintenance replacement unit in which a failure has occurred very easily when the system is down. An object of the present invention is to provide a shift path diagnosis method for an information processing device capable of shortening the average restoration time in the above.

The shift path diagnosis method of the present invention is a failure diagnosis method of a shift path obtained by connecting a plurality of maintenance diagnosis unit blocks in which a plurality of storage elements are connected to each other in cascade, In each of the plurality of maintenance diagnosis unit blocks, a unit for writing data representing a logic “0” or “1” from the outside of the block to the frontmost storage element, and the logic “0” according to the shift path verification mode. Alternatively, there are provided means for sequentially shifting and controlling the data representing "1" in the shift mode to transfer to the last storage element, and determination means for determining whether or not the storage data at the last portion of the storage element is normal. A plurality of maintenance diagnosis unit blocks are provided to simultaneously perform a failure diagnosis.

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, storage element groups 3a and 3b each composed of a plurality of storage elements (only two storage element groups 3a and 3b are shown in the figure for simplification, but between these two storage element groups Other storage element groups are also arranged in parallel), and by connecting these storage element groups to each other according to a predetermined relationship, it is necessary for the data processing of the information processing device. A logic circuit network 2 is formed.

Each of the plurality of storage element groups 3a, 3b also constitutes a shift register in which storage elements which are constituent elements are connected in series to each other in order to configure a shift path for failure diagnosis. To do. In this case, data input is performed from the shift-in SI terminal, and data output is performed from the shift-out SO terminal. The shift mode is supplied to the shift mode SM terminal and the clock pulse is applied to the clock CLK terminal, so that the shift path is activated.

The shift register designating circuit 4 includes a plurality of shift registers 3
This is a circuit for designating any of a and 3b, and the decoder 5 is for selectively supplying the clock by the clock supply circuit 6 to the shift register designated by the shift register designating circuit 4. is there. A shift-in input control circuit 7 is provided for serially inputting data to the shift registers 3a and 3b in response to the supply of this clock, and the output of the shift register designated in response to the supply of the clock is the multiplexer 8 It is selected by.

The data selected by the multiplexer 8 is supplied to the shift buffer 13 via the shift-out output control circuit 9. The output of the shift buffer 13 is supplied to the shift-in input control circuit 7, and the maintenance diagnostic device 14
Is also supplied to. Data can be input from the maintenance diagnosis device 14 to the shift buffer 13.

A shift mode designating circuit 10 is provided to enable the shift-in input and shift-out output functions of the shift registers 3a and 3b.
Is provided, and when a clock is supplied to the shift registers 3a, 3b without activating the shift mode of the shift mode designating circuit 10, the 1-input circuit 12a, 12b or 0-input is performed via the switching circuits 37a, 37b. "1" or "0" data is written from the circuits 11a and 11b to a plurality of predetermined storage elements, respectively. The writing of "1" or "0" is performed by the switching circuits 37a and 37b respectively selected according to the mode designated by the shift path verification mode designating means 36. The 0-input circuit, the 1-input circuit, and the switching circuit are provided corresponding to each of the shift registers 3a and 3b.

The 0/1 determination circuits 32a and 32b determine the values of a plurality of predetermined storage elements different from the plurality of storage elements in which “0” or “1” is written at a predetermined timing in the shift mode. This is provided for each shift register 3a, 3b.

The shift path verification mode designating means 36 designates whether the verification of the shift path is performed in the 0 mode or in the 1 mode, and for the switching circuits 37a and 37b, from the 0 input circuits 11a and 11b at the time of the 0 mode verification. "1" data from the 1-input circuits 12a and 12b at the time of one-mode verification. 0/1 judgment circuits 32a, 32b judgment outputs are the maintenance diagnostic device 14
The shift path is diagnosed by being introduced into.

FIG. 2 is a diagram showing the shift registers 3a and 3b in FIG. 1 in more detail. MCP (Multi-Chip Package)
It is composed of a card C10 equipped with the shift register 3a shown in FIG. 1 in which nine maintenance replacement units MCP0 to MCP8 called as are mounted. This card C10 forms a logic circuit network 2 composed of a plurality of storage elements 1a, which are cascade-connected to one shift register 3a in FIG.
Be deployed to.

The shift registers 3a and 3b connect the shift-in (SI) terminal and the shift-out (SO) terminal of each MCP unit to each other, and the shift-in (SI) terminal of the shift registers 3a and 3b shifts the MCP8. The in (SI) terminal corresponds, and the shift out (SO) terminal of the shift register corresponds to the shift out (SO) terminal of MCP0.

In addition, 1 bit of the frontmost memory element closest to the shift-in (SI) terminal side of each MCP does not enable the shift mode of the shift mode designation circuit 10 in FIG. 1 and clocks the shift registers 3a and 3b. , The 1-input circuit 11a and the 0-input circuit 11b depend on the value of the shift path verification mode.
Therefore, "1" or "0" is input via the switching circuits 37a and 37b. That is, if the shift path verification mode is 1 when a clock is supplied to the shift registers 3a and 3b without enabling the shift mode of the shift mode designating circuit 10 on the shift registers 3a and 3b,
If the shift path verification mode is 0, the storage element set to 0 is placed at a position closest to the shift-in terminal of each MCP by 9 bits. In addition, one bit of the last storage element closest to the shift-out (SO) terminal side of each MCP is set by the “0/1” determination circuits 32a and 32b in FIG.
The data shifted in at a predetermined timing in the shift mode is checked.

In such a configuration, a procedure for deriving the contents of the shift register 3a to the shift buffer 13 when there is no failure in each storage element forming the shift register 3a will be described below.

First, the shift register designating circuit 4 selects a desired shift register 3a, the shift mode designating circuit 10 sets the shift mode (SM) to "1", and the clock supply circuit 6 supplies a clock to the shift register 3a. Therefore, by using the shift-out output control circuit 9, the shift-out (S
Data is taken into the shift buffer 13 bit by bit from the (O) terminal.

Next, a procedure for transferring the contents of the shift buffer 13 to the shift register 3a after scanning out will be described. First, the shift register designating circuit 4 selects a desired shift register 3a, the shift mode designating circuit 10 sets the shift mode (SM) to "1", and the clock supply circuit 6 supplies a clock to the shift register 3a for shifting. The data is transferred from the shift buffer 13 to the shift register 3a by using the shift-in (SI) input control circuit 7 bit by bit from the IN (SI) terminal.

After the scan-out operation and the scan-in operation, the diagnostic device 14 reads the contents of the shift buffer 13 by using the signal line 31 forming the data bus, so that the arbitrary shift registers 3a and 3b forming the logic circuit network 2 are read. The contents of can be displayed. Furthermore, after the scan-out operation, the maintenance diagnostic device 14
Desired data is transferred to the shift buffer 13 using the data bus 30, and then the scan-in operation is performed. As a result, desired data can be set in any of the shift registers 3a and 3b forming the logic circuit network 2.

Next, the procedure for pointing out the replacement unit assuming that the storage element on the shift path has failed in the "0" mode will be described. First, when the shift mode designating circuit 10 is not activated, that is, when the shift mode is not designated and the shift path verification mode is 1, the clock supply circuit 6 shifts the shift register.
Supply clock once to 3a. At this time, the switching circuit 37a
Is controlled by the shift path verification mode designating means 36 so as to select "1" data which is the output of the 1-input circuit 12a. As a result, "1" is set in the frontmost memory element of each MCP by the function of the 1-input circuit 12a.

Then, the shift mode designating circuit 4 sets the shift mode to "1" and the clock is supplied from the clock supply circuit 6 to the shift register 3a (shift-out operation). At that time, the 0/1 determination circuit 32a counts the number of clocks supplied after the shift-out is started, that is, after the shift mode is set to "1". The MCPs mounted on the card C10 each include a 0/1 determination circuit, and each 0/1 determination circuit stores the number of storage elements mounted on the corresponding MCP. Check the number of memory elements held in advance, and
When the number of clocks supplied in the shift mode reaches 14 (the number of storage elements mounted on MCP0) 14 times, the 0/1 determination circuit determines that the last storage element located on the SO side is "1". Check if it takes a value. If the above 1 bit is different from a predetermined value (that is, 1), the shift-out ends abnormally and the maintenance diagnostic device 14 is notified of the information that the MCP0 is a failure FRU. This is because the bit A (see Fig. 2) supplied with the clock in the non-shift mode is "1".
If the clock is supplied only once after switching to the shift mode (the number of storage elements mounted on the MCP0), the bit B at the end is the initial bit of the foremost bit. The value (“1”) should be set. However, if any of the memory elements mounted on the MCP0 has a failure that causes it to be stuck at "0", the value of bit B becomes "0", and the 0/1 determination circuit 32 determines It is identified whether MCP0 has failed.

Similar checks are performed in MCP1 to MCP8 in parallel with the failure detection process of MCP0. That is, in the non-shift mode, the value of "1" is set to the frontmost bit of each MCP by the 1-input circuit 12a, and the 0/1 determination circuit 32 in each MCP is set.
a is the number of memory elements mounted in each MCP in shift mode-if the clock is supplied only once, each MC
By checking whether the value of the last bit of P is "1", it is possible to detect the 0 failure of the memory element mounted on the MCP.

The procedure for pointing out the exchange unit assuming that the storage element on the shift path has failed in the mode of "1" is the same as the above except that the shift path verification mode is "0". That is, when the clock is supplied to the shift register 3a once by the clock supply circuit 6 in the non-shift mode and the shift path verification mode is "0", it is located at the frontmost position of each MCP by the function of the 0 input circuit 11a. "0" is set in the memory element. At this time, the switching circuit 37a inputs the output "0" of the 0 input circuit 11a so that the shift path verification mode designating means
Controlled from 36.

Then, the shift mode is set to "1" to perform the shift-out operation for the shift register 3a, and the 0/1 determination circuit 32a
It is determined whether the last bit of each MCP is "0" by a predetermined timing, that is, when the number of supplied clocks reaches (the number of storage elements mounted in MCP0) -1. Similar checks are performed in parallel in MCPs 1 to 8 as in the case where the shift path verification mode is "1".

According to the above method, whether the shift path verification mode is "0" or "1", the number of clocks required in the shift mode for the shift path verification is (the memory element of each MCP mounted on the card C10 The maximum value among the numbers) -1 times. That is, {(MAX value of the number of storage elements mounted on each MCP on the card C10) -1} × clock supply (during shift mode), whether all MCPs on the card C10 are normal or abnormal. For example, it is possible to know which MCP has a failure and the type of failure (0 failure or 1 failure).

In the above method, the verification is performed for each card. However, if the output data of the multiplexer at the time of verification is not required, the shift path verification can be performed simultaneously for all the cards. At this time, the shift register designating circuit 4 designates all the shift registers 3a to 3b as the shift registers to be the target of the shift operation, and at this time, the clock is distributed to all the shift registers. The number of clocks required for verification (in shift mode) is {(MAX value of the number of storage elements mounted in each MCP mounted on the device)-
1} × 2 times is the same.

By doing so, even if a shift path is configured by a plurality of maintenance diagnosis block units, it is possible to easily determine which maintenance diagnosis unit block in the shift path has a failure with a small number of clocks.

As described above, according to the present invention, "0" or "1" data is written to the frontmost storage element for each maintenance diagnosis block constituting the shift path, and this write data is written to the shift path. It is possible to determine which block of the maintenance diagnosis block has a failure by sequentially transferring the data by sequentially determining the data stored in the last storage element at the timing when this data arrives at the last storage element. There is an effect that detection can be performed easily and quickly.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram illustrating a specific configuration example of the storage element groups 3a and 3b in FIG. Description of main part code 1 …… Maintenance diagnosis unit block 3a, 3b …… Memory element group 11a, 11b …… 0 input circuit 12a, 12b …… 1 input circuit 14 …… Maintenance diagnosis device 32a, 32b …… 0 / 1 Judgment circuit 36 …… Shift path verification mode designating means 37a, 37b …… Switching circuit

Claims (1)

[Claims] 1. A failure diagnosis method for a shift path, which is obtained by cascading a plurality of maintenance diagnosis unit blocks in which a plurality of storage elements are connected to each other in cascade, wherein the plurality of maintenance diagnosis units are provided. In each of the blocks
According to the shift path verification mode, a means for writing data representing logic "0" or "1" from the outside of the block to the frontmost memory element, and the data representing logic "0" or "1" depending on the shift mode. A means for sequentially shifting and transferring the data to the last storage element, and a determination means for determining whether or not the stored data in the last storage element are normal are provided, and the plurality of maintenance diagnosis unit blocks simultaneously A shift path diagnostic method characterized by performing fault diagnosis.