JPH0646389B2 - Shift path failure diagnosis device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift path failure diagnosis apparatus, and more particularly to a diagnosis when a shift path failure occurs in an information processing apparatus.

2. Description of the Related Art Conventionally, in information processing apparatuses, a shift path is configured by connecting a plurality of maintenance replacement units (FIELD REPLACEABLE UNITs) in a hardware failure in cascade. for that reason,
If a failure occurs in this shift path, it is necessary to replace a plurality of maintenance replacement units, and there is a drawback that the average repair time (MEAN TIME TO REPAIR) of this shift path becomes long.

A method to compensate for this drawback is to leave the device in the initial state, output the data of the shift path by using the shift register function of the shift path including the failed maintenance exchange unit, and set this data and the initial state of the device. There is a way to point out the failed maintenance replacement unit by comparing it with the data in. However, in a device in which the initial state is set using this shift register function, if a failure occurs in the maintenance replacement unit that constitutes the shift path,
There is a drawback in that the initial state cannot be set using the shift register function of the shift path, a plurality of maintenance replacement units must be replaced, and the average restoration time of this shift path becomes long.

In addition, since it is necessary to compare the pre-stored data indicating the initial state with the data in which all bits are output by using the shift register function, it takes time to indicate the maintenance replacement unit having the failure. There was a drawback.

The object of the present invention is to eliminate the above-mentioned drawbacks of the conventional ones, and it is possible to easily point out a maintenance / replacement unit having a failure, and to shorten the failure repair time when the system is down. It is an object of the present invention to provide a shift path failure diagnosis device capable of shortening the average repair time.

Configuration of the Invention A shift path failure diagnosis apparatus according to the present invention is a failure diagnosis of a shift path configured by cascade-connecting a plurality of shift registers as a maintenance replacement unit configured by cascade-connecting a plurality of storage elements. A plurality of switching means provided corresponding to each of the shift registers and selectively deriving an input signal and an output signal of the corresponding shift register to be an input of a next-stage circuit; Means for controlling at least one of the means to control the input signal of the corresponding shift register to be input to the next stage circuit so as to bypass the shift register and perform a failure diagnosis, and a failure is detected by the failure diagnosis. And a means for pointing out the maintenance replacement unit in which the failure is detected.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, an information processing apparatus according to an embodiment of the present invention includes a shift register 1 to 3 and a shift mode designating circuit 4.
, Shift-in input control circuit 5, shift register designation circuit 6, decoders 7 and 17, and clock supply circuit 8
, Selectors 9 to 11, and shift-out output control circuit 1
2, a maintenance diagnosis device 13, a shift buffer 14, an input / output control circuit 15, and an input / output connection circuit 16.

The shift registers 1 to 3 are storage elements 1-1 to 1-1, respectively.
2-1 to 2-m and 3-1 to 3-n are connected in cascade. The shift registers 1 to 3 are respectively connected in cascade to form one shift path, and each of the shift registers 1 to 3 corresponds to a maintenance exchange unit of the information processing apparatus.

A shift mode designating circuit 4 is provided for each of the shift registers 1 to 3.
The shift mode signal 102 from is input and the shift mode is designated. Clock signal from clock supply circuit 8
The decoder 124 is distributed to each of the shift registers 1 to 3 by the decoder 7 according to the control signal 123 from the shift register designating circuit 6. That is, the decoder 7 supplies the clock signals 103 to 105 to the shift registers 1 to 3 designated by the control signal 123 from the shift register designating circuit 6, respectively.

The shift-in input 101 is input from the shift-in input control circuit 5 to the shift-in terminal of the shift register 1.
The shift-out outputs 106, 108 and 110 from the shift-out terminals of the shift registers 1 to 3 are selector 9-, respectively.
11 is input.

The shift-in input 101 from the shift-in input control circuit 5 and the shift-out output 106 from the shift register 1 are input to the selector 9, and the selector switching signal 120 from the decoder 17 inputs the shift-in input 101 and the shift-out output 10.
6 is switched and output as a shift-in signal 107 to the shift register 2 and the selector 10.

The shift-in signal 107 from the selector 9 is sent to the selector 10.
And the shift-out signal 108 from the shift register 2 are input, and the shift-in signal 107 and the shift-out output 108 are switched by the selector switching signal 121 from the decoder 17 to the shift register 3 and the selector 11 as the shift-in signal 109. Output.

The selector 11 receives the shift-in signal 109 from the selector 10.
And the shift-out signal 110 from the shift register 3 are input, and the shift-in signal 109 and the shift-out output 110 are switched by the selector switching signal 122 from the decoder 17 and output to the shift-out output control circuit 12 as the shift-out signal 111. To do.

The shift-out output control circuit 12 checks the shift-out signal 111 from the selector 11, writes the shift-out signal 113 in the shift buffer 14, and outputs the check result to the maintenance diagnostic device 13 as an error report signal 112.

The maintenance diagnosis device 13 knows the occurrence of a failure in the shift registers 1 to 3 from the error report signal 112 from the shift-out output control circuit 12, and outputs the control signal 116 to the input / output control circuit 15. Further, the maintenance / diagnosis device 13 uses the data buses 114, 11
Data is written to and read from the shift buffer 14 via 5.

The input / output control circuit 15 is a control signal from the maintenance diagnostic device 13.
A control signal 118 is output to the shift mode designation circuit 4, the shift-in input control circuit 5, the shift register designation circuit 6, and the input / output connection circuit 16 in accordance with 116. By inputting the control signal 118, the shift mode designating circuit 4 shifts the shift register 1
3 to 3, a shift-in input control circuit 5 controls a shift-in input to the shift register 1, a shift register designating circuit 6 designates the shift registers 1 to 3 to which a clock is to be supplied, The input / output connection circuit 16 outputs a connection instruction signal 119 to the decoder 17 to output the decoder 1
Selector selector signals 120-122 from selectors 9-
The switching operation of 11 is controlled.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.

First, the storage elements 1-1 to 1 of each of the shift registers 1 to 3
-L, 2-1 to 2-m, and 3-1 to 3-n have no fault, the procedure for extracting the contents from the shift path formed by the shift registers 1 to 3 and storing them in the shift buffer 14 will be described. To do.

In the shift register designating circuit 6, desired shift registers 1 to
3 is selected and designated, the shift mode designation circuit 4 sets the shift mode to "1", and the clock signals 103 to 105 are supplied from the clock supply circuit 8 to the shift registers 1 to 3 via the decoder 7 respectively. Shift register 1
The shift path composed of 3 to 3 is caused to perform the shift operation.

By this shift operation, the contents of the shift path are stored in the shift buffer 14 via the shift-out output control circuit 12. At this time, “0” from the shift-in input control circuit 5 is input to the shift-in terminal of the shift register 1.

Further, the input / output control circuit 15 outputs selector switching signals 120 to 122 to the selectors 9 to 11 via the input / output connection circuit 16 and the decoder 17, and the selectors 9 to 11 shift out of the shift registers 1 to 3 respectively. The control is performed so as to select the shift-out outputs 106, 108, 110 from the terminals.

All memory elements 1-1 to 1- of shift registers 1 to 3 respectively
When the clocks are supplied by the number of 1, 2-1 to 2-m, and 3-1 to 3-n, all the storage elements 1-1 to 1-1 due to the above operation.
The contents of 1-1, 2-1 to 2-m, and 3-1 to 3-n are transferred to the shift buffer 14.

At this time, all the storage elements 1-
"0" from the shift-in input control circuit 5 should be stored in 1-1 to 1-1, 2-1 to 2-m, and 3-1 to 3-n. In order to check this, the clock is further supplied only once to the shift registers 1 to 3, and the shift-out output control circuit 12 checks that the bit output from the shift path by the supply of this clock is "0". .

When the bit output from this shift path is "1", the storage element in the shift registers 1 to 3 is "1".
It is determined that there is a failure in the mode that is fixed to, so that a so-called "1" stack failure can be detected.

When it is determined by the check in the shift-out output control circuit 12 that the shift registers 1 to 3 are normal, the clock is supplied to the shift registers 1 to 3 only once, and " 1 "
Enter. As a result, in the shift register 1, the storage element 1-1 on the shift-in terminal side is "1" for only 1 bit,
The contents of the other storage elements 1-2 to 1-1 are all "0". "1" stored in the storage element 1-1 is called a last digit, and the operation of transferring the contents of the shift path to the shift buffer 14 in the above-described procedure is called a scan-out operation.

Next, this scan-out operation causes the shift buffer 1
A procedure for transferring the contents stored in No. 4 to the shift registers 1 to 3 will be described.

In the shift register designating circuit 6, desired shift registers 1 to
3 is selected and designated, the shift mode designation circuit 4 sets the shift mode to "1", and the clock signals 103 to 105 are supplied from the clock supply circuit 8 to the shift registers 1 to 3 via the decoder 7 respectively. Shift register 1
The shift path composed of 3 to 3 is caused to perform the shift operation.
At this time, the data input from the shift-in input control circuit 5 to the shift-in terminal of the shift register 1 is the data stored in the shift buffer 14, and the shift-in terminal receives 1 data via the shift-in input control circuit 5. The contents of the shift buffer 14 will be transferred bit by bit.

All storage elements 1-1 to 1-1 of the shift registers 1 to 3 and 2
When clocks are supplied by the numbers -1 to 2-m and 3-1 to 3-n, whether 1-bit data finally output from the shift path is "1" or "0". Is checked by the shift-out output control circuit 12.

When the bit output from this shift path is "0", the storage element in the shift registers 1 to 3 is "0".
It is determined that there is a failure in the mode that is fixed to, so that a so-called "0" stack failure can be detected.

When there is no failure in the shift registers 1 to 3, the last digit "1" which is shift-in input in advance during the scan-out operation is output from the shift path. This operation described above is called a scan-in operation.

When a "1" stack fault or a "0" stack fault of a storage element is detected in the shift registers 1 to 3 during the above scan-out operation and scan-in operation, the shift-out output control circuit 12 maintains the error report signal 112. This is output to the diagnostic device 13 and the maintenance diagnostic device 13 is notified of the occurrence of this failure.

The maintenance diagnostic device 13 detects a control signal 11 by detecting this failure.
6 is output to the input / output control circuit 15, and this control signal 116 instructs the input / output control circuit 15 to which of the shift registers 1 to 3 the input / output connection is changed.

First, if an input / output connection change instruction is output to the shift register 1, the input / output control circuit 15 outputs the control signal 11
8 instructs the input / output connection circuit 16 to change the input / output connection to the shift register 1. The input / output connection circuit 16 outputs a connection instruction signal 119 to the decoder 17, and the decoder 17
Outputs a selector switching signal 120 to the selector 9 according to this connection instruction signal 119. That is, it instructs to switch the output from the selector 9 from the shift-out output 106 from the shift register 1 to the shift-in input 101 to the shift register 1.

Further, the input / output control circuit 15 outputs the control signal 118 to the shift register designating circuit 6 and instructs the shift register designating circuit 6 not to supply the clock to the shift register 1. In response to this instruction, the shift register designating circuit controls the decoder 7 by the control signal 123 so that the shift register 1 is not supplied with a clock.

Further, the input / output control circuit 15 outputs a control signal 118 to the shift mode designating circuit 4 and controls the shift mode designating circuit 4 so that the shift register 1 is not placed in the shift mode.

When the scan-out operation and the scan-in operation are performed after controlling the shift register specifying circuit 6 and the shift mode specifying circuit 4 by the control signal 118 of the input / output control circuit 15, the scan-out operation and the scan-in operation are The shift register 1 is bypassed, and the shift path composed of the shift registers 2 and 3 is performed.

That is, the storage elements 1-1 to 1-1 of the shift register 1
Even if any one of them has a "1" stack fault or a "0" stack fault, since the shift register 1 is bypassed, the scan-out operation and the scan-in operation for the shift path constituted by the shift registers 2 and 3 are performed. It ends normally, and it is found that the shift register 1 has a failure. Since each of the shift registers 1 to 3 corresponds to the maintenance / replacement unit, the malfunctioning maintenance / replacement unit can be easily pointed out by performing the above operation.

As described above, by configuring each shift register configured by connecting a plurality of storage elements in cascade to be capable of bypass control, a shift path configured by connecting a plurality of shift registers in cascade Since the failure diagnosis is performed, it is possible to easily identify and indicate the failure of the shift register, which is a maintenance replacement unit.
In this way, since it is possible to easily point out the shift register having a failure, it is possible to replace all of the plurality of maintenance replacement units that conventionally constitute a shift path when a failure occurs in a system down state. The failure repair time can be shortened, and since the failure repair only needs to be performed on the failure-caused one, the average repair time can be shortened.

In the embodiment of the present invention, the case in which a faulty shift register is bypassed for fault diagnosis has been described, but it is also possible to bypass another shift register for fault diagnosis for only one shift register. Is obvious.

As described above, according to the present invention, at least one of the shift registers, which is a plurality of maintenance exchange units constituting the shift path, is bypassed to perform a failure diagnosis, thereby making it possible to detect a failure in the shift path. There is an effect that it is possible to easily point out the generated maintenance replacement unit, and it is possible to shorten the failure repair time when the system is down and shorten the average repair time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Description of symbols of main parts 1-3 ... shift register 4 ... shift mode designating circuit 5 ... shift-in input control circuit 6 ... shift register designating circuit 9 to 11 ... selector 13 ... maintenance diagnostic device

Claims (1)

[Claims] 1. A failure diagnosis device for a shift path, comprising a plurality of shift registers as a maintenance exchange unit, which are constituted by a plurality of storage elements connected in series, and which are connected in series. Controlling at least one of a plurality of switching means provided corresponding to each of the registers and selectively deriving an input signal and an output signal of the corresponding shift register to input to the next stage circuit. Then, by inputting the input signal of the corresponding shift register to the input of the next-stage circuit, the shift register is bypassed to perform control for performing the fault diagnosis, and the fault is detected when the fault is detected by the fault diagnosis. And a means for pointing out the detected maintenance / replacement unit.