JPH0812911B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a compound semiconductor device suitable for an integrated circuit.

(Prior Art) A compound semiconductor typified by GaAs has various advantages such as 1) high electron mobility, 2) fast electron saturation rate, 3) semi-insulation, and 4) excellent anti-reflection line characteristics. Have. For this reason, research and development of integrated circuits using compound semiconductors have been activated, and some have been commercialized. Active devices used in these integrated circuits include bipolar devices such as heterojunction bipolar transistors (HBTs) and unipolar devices such as field effect transistors (FETs). Generally, bipolar devices have excellent current drive capability, high speed, and low 1 / f noise characteristics, but have the drawback of large power consumption. On the other hand, unipolar devices have low power consumption and low high-frequency noise characteristics, but their current drive capability is poor.
It has the drawback that the 1 / f noise is large. For this reason, Si
Similar to BiCMOS (Bi-Cymos) in devices, research and development is being conducted to maximize the advantages of both by integrating compound bipolar devices and compound unipolar devices on the same semiconductor chip and compensating for their weaknesses. .

FIG. 4 shows a conventional hybrid integrated circuit of AlGaAs / GaAs HBT and GaAs FET. In this figure, n ⁺ -GaAs layer 32, n ^-- GaAs layer 33, p ⁺ -GaAs layer grown on the semi-insulating GaAs substrate 30 by the selective epitaxial growth method by MOCVD method.
33, p ⁺ -GaAs layer 34, n-AlGaAs layer 35, n ⁺ -GaAs layer 36 on the crystal structure of AuGeNi emitter electrode 37, AuMn
A base electrode 39 made of Ni and a collector electrode 32 made of AuGeNi are formed to form an HBT. Further GaA
On the other part of the substrate 30, an n-GaAs layer 31 selectively epitaxially grown by MOCVD is provided, and a Schottky gate electrode 41 made of Al and a source electrode 40 and a drain electrode 42 made of AuGe-Ni are provided. And a GaAs FET is constructed.

(Problems to be Solved by the Invention) In the conventional example described above, the active layers of the HBT and the FET are formed by selective epitaxial growth. However, in the selective epitaxial growth method, the uniformity is obtained for a fine structure having a different shape. Is not sufficient, and especially, the threshold voltage VT of the FET varies, and there is a drawback that the manufacturing process becomes long and the cost becomes high.

The object of the present invention is to eliminate the above-mentioned drawbacks and to improve the compound HBT, FE by using only the whole-surface epitaxial growth technique, which has good uniformity and can shorten the process regardless of the selective epitaxial growth technique.
To provide a T hybrid integrated circuit.

(Means for Solving the Problems) In order to achieve the above object, a compound semiconductor device of the present invention is a semiconductor device in which a heterojunction bipolar transistor and a field effect transistor are formed on the same semiconductor chip. A first conductive layer serving as a collector layer is formed at a predetermined position on a semiconductor substrate on which a first conductive type first semiconductor layer and a high-concentration first conductive type second semiconductor layer are sequentially formed on a compound semiconductor substrate. -Type third semiconductor layer, a high-concentration second-conductivity-type fourth semiconductor layer that serves as a base layer, and a first-conductivity-type fifth semiconductor layer that has a wider bandgap than the fourth semiconductor layer and serves as an emitter layer. A heterojunction bipolar transistor comprising a semiconductor layer of 1) and a sixth semiconductor layer of the first conductivity type having a high concentration to be a cap layer, and the second semiconductor layer at another predetermined position on the semiconductor substrate. But A Schottky metal serving as a gate electrode is provided on the removed and exposed first semiconductor layer, and a drain electrode and a source electrode are formed on the second semiconductor layer sandwiching the gate electrode and adjoining in parallel. A field effect transistor including an ohmic metal is formed, and an element isolation region is formed between these transistors. Further, a manufacturing method for realizing the above structure is as follows: a first conductive type first semiconductor layer, a high-concentration first conductive type second semiconductor layer, a first conductive type Third semiconductor layer, high-concentration second-conductivity-type fourth semiconductor layer, first-conductivity-type fifth semiconductor layer having a wider band gap than the fourth semiconductor layer, high-concentration first-conductivity type The step of sequentially forming the sixth semiconductor layer, and the fourth semiconductor layer provided with a base electrode by etching the sixth and fifth semiconductor layers except a predetermined position where the emitter electrode of the heterojunction bipolar transistor is provided. Exposing the emitter electrode,
A step of etching the fourth and third semiconductor layers to expose the second semiconductor layer except the position where the base electrode is provided; and an emitter electrode on each of the sixth and fourth semiconductor layers, Depositing an ohmic metal to be a base electrode and further depositing an ohmic metal to be a collector electrode on the second semiconductor layer at a position adjacent to the third semiconductor layer, and providing a gate electrode of a field effect transistor. Etching the second semiconductor layer at a predetermined position to expose the first semiconductor layer and depositing a Schottky metal on this position; and a step of sandwiching the Schottky metal and adjoining in parallel with each other. A step of depositing an ohmic metal to be a drain electrode and a source electrode on the semiconductor layer, and second and first semiconductors around the heterojunction bipolar transistor and the field effect transistor. It is characterized by comprising the step of isolation ion implantation or the second and the first semiconductor layer is removed by layer etching.

(Function) In the present invention, the first conductivity type first semiconductor serving as the active layer of the FET is formed below the high-concentration first conductivity type second semiconductor layer serving as the subcollector layer in the HBT crystal structure. Since the HBT has the layer, the first semiconductor layer does not hinder the operation of the HBT, and the second semiconductor layer of the FET is used as a high-concentration layer for ohmic contact reduction, and the FET is formed by the recess gate structure. realizable. For this reason, all crystal structures can be formed by full-face epitaxial growth without relying on selective epi-growth, which has the great merit that not only the uniformity is improved but also the crystal growth process can be shortened.

(Embodiment) FIGS. 1 and 2 are embodiments relating to a compound semiconductor device of the present invention, and FIG. 3 is an embodiment of the present invention relating to a manufacturing method thereof.

In Fig. 1, n ⁺ -GaAs layer (concentration 5 × 10 ¹⁸ cm ^-3 , thickness
1000 Å) 6 is provided with an emitter electrode 7 made of n-Al
P ⁺ -GaAs (concentration 4 × 10 ¹⁹ cm ^-3 , thickness 600) that forms a heterojunction with the GaAs layer (concentration 3 × 10 ¹⁷ cm ^-3 , thickness 1500 Å) 5.
Å) A base electrode 8 made of AuMnNi is provided on the surface of 4. n-GaAs layer (concentration 5 × 10 ¹⁶ cm ^-3 , thickness 3000 Å)
The collector layer composed of 3 is an n ⁺ -GaAs layer (concentration 5 × 10 ¹⁸ c
n ^-3 , thickness 4000 Å) 2 sub-collector layer in contact with n
^{+ −} On the surface of the GaAs layer 2, a collector electrode 9 made of AuGeNi
Is provided to form an AlGaAs / GaAs HBT. n ⁺ −GaAs
Below the layer 2 is the n-GaAs layer 1, which is
It does not affect the operation of the HBT. Between the thickness D _{1 of} this n-GaAs layer 1 and the concentration n There is a relationship. In equation (1), ε _S is the dielectric constant of GaAs,
q is the electron charge, V _bi is the Schottky junction internal voltage of Al and GaAs of about 0.75 V, k is the Boltzmann constant, T is the temperature, and V _T is the threshold voltage of the GaAs FET. n-GaAs layer 1
Has a thickness of 1570Å and a concentration of 1 × 10 ¹⁷ cm ^-3 . V _{T in} this case is −1V. The GaAs layer 2 is also used as a high concentration layer for low ohmic contact of a GaAs FET, and a source electrode 11 made of AuGeNi and a drain electrode 13 also made of AuGeNi are provided on this layer. The gate electrode 10 of the GaAs FET is made of Al and has a recess structure.
It is provided on the surface of the As layer 1. As the element isolation region 15, boron is ion-implanted around the HBT and FET to be insulated. In the embodiment shown in FIG. 2, the element isolation region
The device isolation is realized by etching around the HBT and FET as 14. The reference numbers in FIG. 2 are common to those in FIG.

FIG. 3 shows a manufacturing method according to an embodiment of the present invention. In FIG. 3A, the n-GaAs layer 1 and the n ⁺ -GaAs layer 2 are formed on the semi-insulating GaAs substrate 12 by the MBE (Molecular Beam Epitaxy) method. , N
-GaAs layer 3, p ⁺ -GaAs layer 4, n-AlGaAs layer 5, n ⁺ -GaAs
Layer 6 is grown in sequence. In (b), an emitter mesa and a base mesa are formed using a photoresist or the like as a mask. Next, in (c), n ⁺ − which becomes the emitter cap layer
An emitter electrode 7 made of AuGeNi is formed on the GaAs layer 6 and a collector electrode 9 made of AuGeNi is sequentially formed on the p ⁺ -GaAs layer 4 serving as a base layer by the photo resist lift-off method. Further, in (d), the n ⁺ -GaAs layer 2 is etched using the photoresist 16 as a mask, and then Al10 which is a Schottky metal is vapor-deposited from the vertical direction. After that, Al on the resist is removed by a photo resist lift-off method. Next, in (e), the AuGe
A source electrode 11 made of Ni and a drain electrode 13 made of AuGeNi are simultaneously formed.

Finally, in (f), boron is selectively ion-implanted around the device 13 using the photoresist as a mask. Or use the same photoresist as a mask around the device
Etch 13.

(Effect of the Invention) In the compound semiconductor device and the manufacturing method thereof according to the present invention, the selective epitaxial growth technique is not used,
A compound HBT and a compound FET can be formed on the same semiconductor chip by mixing using only uniform epitaxial growth. Therefore, not only the device characteristics are uniform, but also the crystal growth process can be shortened, and a high-performance integrated circuit can be provided at low cost.

Although GaAs is used as the compound semiconductor substrate in the embodiments of the present invention, the material is not limited to GaAs and may be InP or the like. Further, it goes without saying that the degree of integration of elements is not limited to two and can be applied to any number.

Although n ⁺ -GaAs is used for the HBT cap layer, the cap layer may be a semiconductor such as n ⁺ -InGaAs or n ⁺ -Ge. Also
A graded structure may be used for the emitter / base junction, the base layer, and the emitter / cap junction of the HBT.

[Brief description of drawings]

1 and 2 are cross-sectional views of a compound semiconductor device of an embodiment of the present invention, FIGS. 3 (a) to 3 (f) are views showing a manufacturing method which is an embodiment of the present invention, and FIG. FIG. 6 is a sectional view of a conventional compound semiconductor device. In these figures, 1 ... n-GaAs layer, 2,32 ... n ⁺ -GaAs layer, 3,33 ... n-
GaAs layer, 4,34 ... p ⁺ -GaAs layer, 5,35 ... n-AlGaAs layer,
6,36 ... n + -GaAs layer, 7,37 ... Emitter electrode, 8,38 ...
… Base electrode, 9,39 …… Collector electrode, 10,41 …… Gate electrode, 11,40 …… Source electrode, 13,42 …… Drain electrode, 31 …… n-GaAs layer, 12 …… Semi-insulating property GaAs substrate, 14,1
5 …… Element separation area, 16 …… Photoresist, 101 …… Al
GaAs / GaAs HBT, 102 ... GaAs FET.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/095 29/205 29/73 29/812 H01L 29/72 29/205

Claims (2)

[Claims] 1. In a semiconductor device in which a heterojunction bipolar transistor and a field effect transistor are formed on the same semiconductor chip, the heterojunction bipolar transistor is formed on a semi-insulating compound semiconductor substrate in order of the first conductivity type first. The semiconductor layer, the third semiconductor layer of the first conductivity type serving as the collector layer, and the high level semiconductor serving as the base layer are provided at predetermined positions on the semiconductor substrate on which the second semiconductor layer of the high-concentration first conductivity type is formed. A second semiconductor layer of a second conductivity type having a high concentration, and a first semiconductor layer having a wider bandgap than the fourth semiconductor layer and serving as an emitter layer.
The field effect transistor has a structure including a conductive type fifth semiconductor layer and a high-concentration first conductive type sixth semiconductor layer serving as a cap layer. The second semiconductor layer is removed, a Schottky metal serving as a gate electrode is provided on the exposed first semiconductor layer, and a drain electrode and a source are provided on both sides of the gate electrode and on the second semiconductor layer. A compound semiconductor device comprising a structure in which an ohmic metal to be an electrode is formed, and an element isolation region is formed between these transistors. 2. A first conductivity type first semiconductor layer, a high concentration first conductivity type second semiconductor layer, a first conductivity type third semiconductor layer, on the entire surface of a semi-insulating compound semiconductor substrate. A high-concentration second-conductivity-type fourth semiconductor layer, a first-conductivity-type fifth semiconductor layer having a wider band gap than the fourth semiconductor layer, and a high-concentration first-conductivity-type sixth semiconductor layer. The step of sequentially forming and etching the sixth and fifth semiconductor layers except a predetermined position where the emitter electrode of the heterojunction bipolar transistor is provided to expose the fourth semiconductor layer where the base electrode is provided, and the emitter is further provided. A step of exposing the second and third semiconductor layers by etching the fourth and third semiconductor layers except positions where electrodes and base electrodes are provided; and emitters on the sixth and fourth semiconductor layers, respectively. Ohmic gold used as electrodes and base electrodes And an ohmic metal serving as a collector electrode on the second semiconductor layer at a position adjacent to the third semiconductor layer, and at a predetermined position for providing a gate electrode of the field effect transistor. Etching the second semiconductor layer to expose the first semiconductor layer and depositing a Schottky metal at this position, and a drain electrode and a source on the adjacent second semiconductor layer on both sides of the Schottky metal. The step of depositing an ohmic metal to be an electrode and the second and first semiconductor layers around the heterojunction bipolar transistor and the field effect transistor are removed by etching, or the isolation is performed in the second and first semiconductor layers. The method for manufacturing a compound semiconductor device according to claim 1, further comprising a step of performing ion implantation.